{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 06 16:58:42 2010 " "Info: Processing started: Sun Jun 06 16:58:42 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off FFT -c FFT " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FFT -c FFT" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "ADD add T_control.v(10) " "Info (10281): Verilog HDL Declaration information at T_control.v(10): object \"ADD\" differs only in case from object \"add\" in the same scope" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 10 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "ADD_WN add_wn T_control.v(11) " "Info (10281): Verilog HDL Declaration information at T_control.v(11): object \"ADD_WN\" differs only in case from object \"add_wn\" in the same scope" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 11 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "rdata_out Rdata_out T_control.v(9) " "Info (10281): Verilog HDL Declaration information at T_control.v(9): object \"rdata_out\" differs only in case from object \"Rdata_out\" in the same scope" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 9 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "idata_out Idata_out T_control.v(9) " "Info (10281): Verilog HDL Declaration information at T_control.v(9): object \"idata_out\" differs only in case from object \"Idata_out\" in the same scope" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 9 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "T_control.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file T_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 T_control " "Info: Found entity 1: T_control" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "block.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file block.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 block " "Info: Found entity 1: block" {  } { { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "butterfly.v(42) " "Warning (10268): Verilog HDL information at butterfly.v(42): Always Construct contains both blocking and non-blocking assignments" {  } { { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 42 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "butterfly.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file butterfly.v" { { "Info" "ISGN_ENTITY_NAME" "1 butterfly " "Info: Found entity 1: butterfly" {  } { { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "s2p.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file s2p.v" { { "Info" "ISGN_ENTITY_NAME" "1 s2p " "Info: Found entity 1: s2p" {  } { { "s2p.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/s2p.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "p2s.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file p2s.v" { { "Info" "ISGN_ENTITY_NAME" "1 p2s " "Info: Found entity 1: p2s" {  } { { "p2s.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/p2s.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "block_new.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file block_new.v" { { "Info" "ISGN_ENTITY_NAME" "1 block_new " "Info: Found entity 1: block_new" {  } { { "block_new.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/block_new.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "makeup_sign.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file makeup_sign.v" { { "Info" "ISGN_ENTITY_NAME" "1 makeup_sign " "Info: Found entity 1: makeup_sign" {  } { { "makeup_sign.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/makeup_sign.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ctrl_fft.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ctrl_fft.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ctrl_fft-one " "Info: Found design unit 1: ctrl_fft-one" {  } { { "ctrl_fft.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 ctrl_fft " "Info: Found entity 1: ctrl_fft" {  } { { "ctrl_fft.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reset_ctrl.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file reset_ctrl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reset_ctrl-rtl " "Info: Found design unit 1: reset_ctrl-rtl" {  } { { "reset_ctrl.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/reset_ctrl.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 reset_ctrl " "Info: Found entity 1: reset_ctrl" {  } { { "reset_ctrl.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/reset_ctrl.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "block " "Info: Elaborating entity \"block\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "T_control T_control:inst46 " "Info: Elaborating entity \"T_control\" for hierarchy \"T_control:inst46\"" {  } { { "block.bdf" "inst46" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 304 368 624 592 "inst46" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_ram_dq0.v 1 1 " "Warning: Using design file lpm_ram_dq0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_ram_dq0 " "Info: Found entity 1: lpm_ram_dq0" {  } { { "lpm_ram_dq0.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_ram_dq0.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ram_dq0 T_control:inst46\|lpm_ram_dq0:ram1 " "Info: Elaborating entity \"lpm_ram_dq0\" for hierarchy \"T_control:inst46\|lpm_ram_dq0:ram1\"" {  } { { "T_control.v" "ram1" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 165 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram T_control:inst46\|lpm_ram_dq0:ram1\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"T_control:inst46\|lpm_ram_dq0:ram1\|altsyncram:altsyncram_component\"" {  } { { "lpm_ram_dq0.v" "altsyncram_component" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_ram_dq0.v" 78 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "T_control:inst46\|lpm_ram_dq0:ram1\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"T_control:inst46\|lpm_ram_dq0:ram1\|altsyncram:altsyncram_component\"" {  } { { "lpm_ram_dq0.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_ram_dq0.v" 78 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_n4a1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_n4a1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_n4a1 " "Info: Found entity 1: altsyncram_n4a1" {  } { { "db/altsyncram_n4a1.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/altsyncram_n4a1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_n4a1 T_control:inst46\|lpm_ram_dq0:ram1\|altsyncram:altsyncram_component\|altsyncram_n4a1:auto_generated " "Info: Elaborating entity \"altsyncram_n4a1\" for hierarchy \"T_control:inst46\|lpm_ram_dq0:ram1\|altsyncram:altsyncram_component\|altsyncram_n4a1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reset_ctrl reset_ctrl:inst5 " "Info: Elaborating entity \"reset_ctrl\" for hierarchy \"reset_ctrl:inst5\"" {  } { { "block.bdf" "inst5" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 336 -344 -248 432 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ctrl_fft ctrl_fft:inst3 " "Info: Elaborating entity \"ctrl_fft\" for hierarchy \"ctrl_fft:inst3\"" {  } { { "block.bdf" "inst3" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 336 -120 40 464 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_fifo0.v 1 1 " "Warning: Using design file lpm_fifo0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_fifo0 " "Info: Found entity 1: lpm_fifo0" {  } { { "lpm_fifo0.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_fifo0.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_fifo0 lpm_fifo0:inst24 " "Info: Elaborating entity \"lpm_fifo0\" for hierarchy \"lpm_fifo0:inst24\"" {  } { { "block.bdf" "inst24" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { -160 1344 1504 -16 "inst24" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/scfifo.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/scfifo.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo " "Info: Found entity 1: scfifo" {  } { { "scfifo.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/scfifo.tdf" 236 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo lpm_fifo0:inst24\|scfifo:scfifo_component " "Info: Elaborating entity \"scfifo\" for hierarchy \"lpm_fifo0:inst24\|scfifo:scfifo_component\"" {  } { { "lpm_fifo0.v" "scfifo_component" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_fifo0.v" 85 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_fifo0:inst24\|scfifo:scfifo_component " "Info: Elaborated megafunction instantiation \"lpm_fifo0:inst24\|scfifo:scfifo_component\"" {  } { { "lpm_fifo0.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_fifo0.v" 85 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_7r31.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/scfifo_7r31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_7r31 " "Info: Found entity 1: scfifo_7r31" {  } { { "db/scfifo_7r31.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/scfifo_7r31.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_7r31 lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated " "Info: Elaborating entity \"scfifo_7r31\" for hierarchy \"lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\"" {  } { { "scfifo.tdf" "auto_generated" { Text "e:/altera/72/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_e141.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_e141.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_e141 " "Info: Found entity 1: a_dpfifo_e141" {  } { { "db/a_dpfifo_e141.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/a_dpfifo_e141.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_e141 lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo " "Info: Elaborating entity \"a_dpfifo_e141\" for hierarchy \"lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\"" {  } { { "db/scfifo_7r31.tdf" "dpfifo" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/scfifo_7r31.tdf" 37 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_b6f.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_b6f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_b6f " "Info: Found entity 1: a_fefifo_b6f" {  } { { "db/a_fefifo_b6f.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/a_fefifo_b6f.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_b6f lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|a_fefifo_b6f:fifo_state " "Info: Elaborating entity \"a_fefifo_b6f\" for hierarchy \"lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|a_fefifo_b6f:fifo_state\"" {  } { { "db/a_dpfifo_e141.tdf" "fifo_state" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/a_dpfifo_e141.tdf" 42 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_tk7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_tk7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_tk7 " "Info: Found entity 1: cntr_tk7" {  } { { "db/cntr_tk7.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cntr_tk7.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_tk7 lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|a_fefifo_b6f:fifo_state\|cntr_tk7:count_usedw " "Info: Elaborating entity \"cntr_tk7\" for hierarchy \"lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|a_fefifo_b6f:fifo_state\|cntr_tk7:count_usedw\"" {  } { { "db/a_fefifo_b6f.tdf" "count_usedw" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/a_fefifo_b6f.tdf" 38 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_fv01.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dpram_fv01.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_fv01 " "Info: Found entity 1: dpram_fv01" {  } { { "db/dpram_fv01.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/dpram_fv01.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_fv01 lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|dpram_fv01:FIFOram " "Info: Elaborating entity \"dpram_fv01\" for hierarchy \"lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|dpram_fv01:FIFOram\"" {  } { { "db/a_dpfifo_e141.tdf" "FIFOram" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/a_dpfifo_e141.tdf" 43 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_avj1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_avj1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_avj1 " "Info: Found entity 1: altsyncram_avj1" {  } { { "db/altsyncram_avj1.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/altsyncram_avj1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_avj1 lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|dpram_fv01:FIFOram\|altsyncram_avj1:altsyncram1 " "Info: Elaborating entity \"altsyncram_avj1\" for hierarchy \"lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|dpram_fv01:FIFOram\|altsyncram_avj1:altsyncram1\"" {  } { { "db/dpram_fv01.tdf" "altsyncram1" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/dpram_fv01.tdf" 36 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_fjb.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_fjb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_fjb " "Info: Found entity 1: cntr_fjb" {  } { { "db/cntr_fjb.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cntr_fjb.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_fjb lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|cntr_fjb:rd_ptr_count " "Info: Elaborating entity \"cntr_fjb\" for hierarchy \"lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|cntr_fjb:rd_ptr_count\"" {  } { { "db/a_dpfifo_e141.tdf" "rd_ptr_count" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/a_dpfifo_e141.tdf" 44 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "p2s p2s:inst28 " "Info: Elaborating entity \"p2s\" for hierarchy \"p2s:inst28\"" {  } { { "block.bdf" "inst28" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 64 1808 2008 192 "inst28" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "butterfly butterfly:inst48 " "Info: Elaborating entity \"butterfly\" for hierarchy \"butterfly:inst48\"" {  } { { "block.bdf" "inst48" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 240 1488 1672 432 "inst48" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "ADD_17.v 1 1 " "Warning: Using design file ADD_17.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ADD_17 " "Info: Found entity 1: ADD_17" {  } { { "ADD_17.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ADD_17.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADD_17 butterfly:inst48\|ADD_17:add_real " "Info: Elaborating entity \"ADD_17\" for hierarchy \"butterfly:inst48\|ADD_17:add_real\"" {  } { { "butterfly.v" "add_real" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 67 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub butterfly:inst48\|ADD_17:add_real\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"butterfly:inst48\|ADD_17:add_real\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "ADD_17.v" "lpm_add_sub_component" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ADD_17.v" 67 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "butterfly:inst48\|ADD_17:add_real\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"butterfly:inst48\|ADD_17:add_real\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "ADD_17.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ADD_17.v" 67 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_vmg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_vmg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_vmg " "Info: Found entity 1: add_sub_vmg" {  } { { "db/add_sub_vmg.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_vmg.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_vmg butterfly:inst48\|ADD_17:add_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_vmg:auto_generated " "Info: Elaborating entity \"add_sub_vmg\" for hierarchy \"butterfly:inst48\|ADD_17:add_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_vmg:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "SUB_17.v 1 1 " "Warning: Using design file SUB_17.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 SUB_17 " "Info: Found entity 1: SUB_17" {  } { { "SUB_17.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/SUB_17.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SUB_17 butterfly:inst48\|SUB_17:sub_real " "Info: Elaborating entity \"SUB_17\" for hierarchy \"butterfly:inst48\|SUB_17:sub_real\"" {  } { { "butterfly.v" "sub_real" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 69 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "SUB_17.v" "lpm_add_sub_component" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/SUB_17.v" 65 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "SUB_17.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/SUB_17.v" 65 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_4qe.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_4qe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_4qe " "Info: Found entity 1: add_sub_4qe" {  } { { "db/add_sub_4qe.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_4qe.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_4qe butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated " "Info: Elaborating entity \"add_sub_4qe\" for hierarchy \"butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_OUTDATED_CLEARBOX" "C:/Documents and Settings/wangwei/桌面/FFT last edition/complex_mult.v C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v " "Warning: Clear box output file C:/Documents and Settings/wangwei/桌面/FFT last edition/complex_mult.v is not compatible with the current compile. Used regenerated output file C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v for elaboration" {  } {  } 0 0 "Clear box output file %1!s! is not compatible with the current compile. Used regenerated output file %2!s! for elaboration" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/complex_mult.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file db/complex_mult.v" { { "Info" "ISGN_ENTITY_NAME" "1 complex_mult_altmult_complex_q5p " "Info: Found entity 1: complex_mult_altmult_complex_q5p" {  } { { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 46 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 complex_mult " "Info: Found entity 2: complex_mult" {  } { { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 554 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "complex_mult butterfly:inst48\|complex_mult:mult " "Info: Elaborating entity \"complex_mult\" for hierarchy \"butterfly:inst48\|complex_mult:mult\"" {  } { { "butterfly.v" "mult" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 72 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "complex_mult_altmult_complex_q5p butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component " "Info: Elaborating entity \"complex_mult_altmult_complex_q5p\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\"" {  } { { "db/complex_mult.v" "complex_mult_altmult_complex_q5p_component" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 583 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "dffe5a complex_mult.v(68) " "Warning (10036): Verilog HDL or VHDL warning at complex_mult.v(68): object \"dffe5a\" assigned a value but never read" {  } { { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 68 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/altmult_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/altmult_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altmult_add " "Info: Found entity 1: altmult_add" {  } { { "altmult_add.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/altmult_add.tdf" 360 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add1 " "Info: Elaborating entity \"altmult_add\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add1\"" {  } { { "db/complex_mult.v" "mult_add1" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 148 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add1 " "Info: Elaborated megafunction instantiation \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add1\"" {  } { { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 148 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_dqa1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_add_dqa1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_dqa1 " "Info: Found entity 1: mult_add_dqa1" {  } { { "db/mult_add_dqa1.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/mult_add_dqa1.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_dqa1 butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add1\|mult_add_dqa1:auto_generated " "Info: Elaborating entity \"mult_add_dqa1\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add1\|mult_add_dqa1:auto_generated\"" {  } { { "altmult_add.tdf" "auto_generated" { Text "e:/altera/72/quartus/libraries/megafunctions/altmult_add.tdf" 535 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ded_mult_1t51.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/ded_mult_1t51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ded_mult_1t51 " "Info: Found entity 1: ded_mult_1t51" {  } { { "db/ded_mult_1t51.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/ded_mult_1t51.tdf" 30 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ded_mult_1t51 butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add1\|mult_add_dqa1:auto_generated\|ded_mult_1t51:ded_mult1 " "Info: Elaborating entity \"ded_mult_1t51\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add1\|mult_add_dqa1:auto_generated\|ded_mult_1t51:ded_mult1\"" {  } { { "db/mult_add_dqa1.tdf" "ded_mult1" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/mult_add_dqa1.tdf" 32 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_b3c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dffpipe_b3c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_b3c " "Info: Found entity 1: dffpipe_b3c" {  } { { "db/dffpipe_b3c.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/dffpipe_b3c.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_b3c butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add1\|mult_add_dqa1:auto_generated\|ded_mult_1t51:ded_mult1\|dffpipe_b3c:pre_result " "Info: Elaborating entity \"dffpipe_b3c\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add1\|mult_add_dqa1:auto_generated\|ded_mult_1t51:ded_mult1\|dffpipe_b3c:pre_result\"" {  } { { "db/ded_mult_1t51.tdf" "pre_result" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/ded_mult_1t51.tdf" 51 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add6 " "Info: Elaborating entity \"altmult_add\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add6\"" {  } { { "db/complex_mult.v" "mult_add6" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 296 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add6 " "Info: Elaborated megafunction instantiation \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add6\"" {  } { { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 296 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_ie81.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_add_ie81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_ie81 " "Info: Found entity 1: mult_add_ie81" {  } { { "db/mult_add_ie81.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/mult_add_ie81.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_ie81 butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add6\|mult_add_ie81:auto_generated " "Info: Elaborating entity \"mult_add_ie81\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add6\|mult_add_ie81:auto_generated\"" {  } { { "altmult_add.tdf" "auto_generated" { Text "e:/altera/72/quartus/libraries/megafunctions/altmult_add.tdf" 535 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ded_mult_2a21.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/ded_mult_2a21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ded_mult_2a21 " "Info: Found entity 1: ded_mult_2a21" {  } { { "db/ded_mult_2a21.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/ded_mult_2a21.tdf" 30 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ded_mult_2a21 butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add6\|mult_add_ie81:auto_generated\|ded_mult_2a21:ded_mult1 " "Info: Elaborating entity \"ded_mult_2a21\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add6\|mult_add_ie81:auto_generated\|ded_mult_2a21:ded_mult1\"" {  } { { "db/mult_add_ie81.tdf" "ded_mult1" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/mult_add_ie81.tdf" 32 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_d3c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dffpipe_d3c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_d3c " "Info: Found entity 1: dffpipe_d3c" {  } { { "db/dffpipe_d3c.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/dffpipe_d3c.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_d3c butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add6\|mult_add_ie81:auto_generated\|ded_mult_2a21:ded_mult1\|dffpipe_d3c:pre_result " "Info: Elaborating entity \"dffpipe_d3c\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add6\|mult_add_ie81:auto_generated\|ded_mult_2a21:ded_mult1\|dffpipe_d3c:pre_result\"" {  } { { "db/ded_mult_2a21.tdf" "pre_result" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/ded_mult_2a21.tdf" 46 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:add_sub7 " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:add_sub7\"" {  } { { "db/complex_mult.v" "add_sub7" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 352 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:add_sub7 " "Info: Elaborated megafunction instantiation \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:add_sub7\"" {  } { { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 352 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_esf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_esf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_esf " "Info: Found entity 1: add_sub_esf" {  } { { "db/add_sub_esf.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_esf.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_esf butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:add_sub7\|add_sub_esf:auto_generated " "Info: Elaborating entity \"add_sub_esf\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:add_sub7\|add_sub_esf:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "aclr " "Warning: Variable or input pin \"aclr\" is defined but never used" {  } { { "db/add_sub_esf.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_esf.tdf" 24 2 0 } } { "lpm_add_sub.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 352 0 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 583 0 0 } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 72 0 0 } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 240 1488 1672 432 "inst48" "" } } } }  } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "clken " "Warning: Variable or input pin \"clken\" is defined but never used" {  } { { "db/add_sub_esf.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_esf.tdf" 25 2 0 } } { "lpm_add_sub.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 352 0 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 583 0 0 } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 72 0 0 } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 240 1488 1672 432 "inst48" "" } } } }  } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:adder1 " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:adder1\"" {  } { { "db/complex_mult.v" "adder1" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 380 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:adder1 " "Info: Elaborated megafunction instantiation \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:adder1\"" {  } { { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 380 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_5ii.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_5ii.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_5ii " "Info: Found entity 1: add_sub_5ii" {  } { { "db/add_sub_5ii.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_5ii.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_5ii butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:adder1\|add_sub_5ii:auto_generated " "Info: Elaborating entity \"add_sub_5ii\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:adder1\|add_sub_5ii:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "aclr " "Warning: Variable or input pin \"aclr\" is defined but never used" {  } { { "db/add_sub_5ii.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_5ii.tdf" 24 2 0 } } { "lpm_add_sub.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 380 0 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 583 0 0 } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 72 0 0 } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 240 1488 1672 432 "inst48" "" } } } }  } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "clken " "Warning: Variable or input pin \"clken\" is defined but never used" {  } { { "db/add_sub_5ii.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_5ii.tdf" 25 2 0 } } { "lpm_add_sub.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 380 0 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 583 0 0 } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 72 0 0 } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 240 1488 1672 432 "inst48" "" } } } }  } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:adder2 " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:adder2\"" {  } { { "db/complex_mult.v" "adder2" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 409 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:adder2 " "Info: Elaborated megafunction instantiation \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:adder2\"" {  } { { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 409 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_6ii.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_6ii.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_6ii " "Info: Found entity 1: add_sub_6ii" {  } { { "db/add_sub_6ii.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ii.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_6ii butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:adder2\|add_sub_6ii:auto_generated " "Info: Elaborating entity \"add_sub_6ii\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:adder2\|add_sub_6ii:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "aclr " "Warning: Variable or input pin \"aclr\" is defined but never used" {  } { { "db/add_sub_6ii.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ii.tdf" 24 2 0 } } { "lpm_add_sub.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 409 0 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 583 0 0 } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 72 0 0 } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 240 1488 1672 432 "inst48" "" } } } }  } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "clken " "Warning: Variable or input pin \"clken\" is defined but never used" {  } { { "db/add_sub_6ii.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ii.tdf" 25 2 0 } } { "lpm_add_sub.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 409 0 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 583 0 0 } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 72 0 0 } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 240 1488 1672 432 "inst48" "" } } } }  } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1 " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\"" {  } { { "db/complex_mult.v" "subtractor1" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 438 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1 " "Info: Elaborated megafunction instantiation \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\"" {  } { { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 438 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_6ji.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_6ji.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_6ji " "Info: Found entity 1: add_sub_6ji" {  } { { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_6ji butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated " "Info: Elaborating entity \"add_sub_6ji\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "aclr " "Warning: Variable or input pin \"aclr\" is defined but never used" {  } { { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 24 2 0 } } { "lpm_add_sub.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 438 0 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 583 0 0 } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 72 0 0 } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 240 1488 1672 432 "inst48" "" } } } }  } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "clken " "Warning: Variable or input pin \"clken\" is defined but never used" {  } { { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 25 2 0 } } { "lpm_add_sub.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 438 0 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 583 0 0 } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 72 0 0 } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 240 1488 1672 432 "inst48" "" } } } }  } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor2 " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor2\"" {  } { { "db/complex_mult.v" "subtractor2" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 467 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor2 " "Info: Elaborated megafunction instantiation \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor2\"" {  } { { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 467 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_5ji.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_5ji.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_5ji " "Info: Found entity 1: add_sub_5ji" {  } { { "db/add_sub_5ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_5ji.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_5ji butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor2\|add_sub_5ji:auto_generated " "Info: Elaborating entity \"add_sub_5ji\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor2\|add_sub_5ji:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "aclr " "Warning: Variable or input pin \"aclr\" is defined but never used" {  } { { "db/add_sub_5ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_5ji.tdf" 24 2 0 } } { "lpm_add_sub.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 467 0 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 583 0 0 } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 72 0 0 } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 240 1488 1672 432 "inst48" "" } } } }  } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "clken " "Warning: Variable or input pin \"clken\" is defined but never used" {  } { { "db/add_sub_5ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_5ji.tdf" 25 2 0 } } { "lpm_add_sub.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 467 0 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 583 0 0 } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 72 0 0 } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 240 1488 1672 432 "inst48" "" } } } }  } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor3 " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor3\"" {  } { { "db/complex_mult.v" "subtractor3" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 496 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor3 " "Info: Elaborated megafunction instantiation \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor3\"" {  } { { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 496 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_i5j.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_i5j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_i5j " "Info: Found entity 1: add_sub_i5j" {  } { { "db/add_sub_i5j.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_i5j.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_i5j butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor3\|add_sub_i5j:auto_generated " "Info: Elaborating entity \"add_sub_i5j\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor3\|add_sub_i5j:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "aclr " "Warning: Variable or input pin \"aclr\" is defined but never used" {  } { { "db/add_sub_i5j.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_i5j.tdf" 24 2 0 } } { "lpm_add_sub.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 496 0 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 583 0 0 } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 72 0 0 } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 240 1488 1672 432 "inst48" "" } } } }  } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "clken " "Warning: Variable or input pin \"clken\" is defined but never used" {  } { { "db/add_sub_i5j.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_i5j.tdf" 25 2 0 } } { "lpm_add_sub.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 496 0 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 583 0 0 } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 72 0 0 } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 240 1488 1672 432 "inst48" "" } } } }  } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "dataa " "Warning: Variable or input pin \"dataa\" is defined but never used" {  } { { "db/add_sub_i5j.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_i5j.tdf" 27 2 0 } } { "lpm_add_sub.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 496 0 0 } } { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 583 0 0 } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 72 0 0 } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 240 1488 1672 432 "inst48" "" } } } }  } 0 0 "Variable or input pin \"%1!s!\" is defined but never used" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/lpm_compare.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/lpm_compare.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_compare " "Info: Found entity 1: lpm_compare" {  } { { "lpm_compare.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_compare.tdf" 266 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_compare butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_compare:comparator1 " "Info: Elaborating entity \"lpm_compare\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_compare:comparator1\"" {  } { { "db/complex_mult.v" "comparator1" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 526 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_compare:comparator1 " "Info: Elaborated megafunction instantiation \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_compare:comparator1\"" {  } { { "db/complex_mult.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v" 526 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_1cg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_1cg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_1cg " "Info: Found entity 1: cmpr_1cg" {  } { { "db/cmpr_1cg.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cmpr_1cg.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_1cg butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_compare:comparator1\|cmpr_1cg:auto_generated " "Info: Elaborating entity \"cmpr_1cg\" for hierarchy \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_compare:comparator1\|cmpr_1cg:auto_generated\"" {  } { { "lpm_compare.tdf" "auto_generated" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_compare.tdf" 280 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "s2p s2p:inst6 " "Info: Elaborating entity \"s2p\" for hierarchy \"s2p:inst6\"" {  } { { "block.bdf" "inst6" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 288 936 1136 416 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "D.v 1 1 " "Warning: Using design file D.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 D " "Info: Found entity 1: D" {  } { { "D.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/D.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "D D:inst16 " "Info: Elaborating entity \"D\" for hierarchy \"D:inst16\"" {  } { { "block.bdf" "inst16" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 688 1504 1696 784 "inst16" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom1.v 1 1 " "Warning: Using design file lpm_rom1.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom1 " "Info: Found entity 1: lpm_rom1" {  } { { "lpm_rom1.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_rom1.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom1 lpm_rom1:inst2 " "Info: Elaborating entity \"lpm_rom1\" for hierarchy \"lpm_rom1:inst2\"" {  } { { "block.bdf" "inst2" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 704 1040 1200 800 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram lpm_rom1:inst2\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"lpm_rom1:inst2\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom1.v" "altsyncram_component" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_rom1.v" 76 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_rom1:inst2\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"lpm_rom1:inst2\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom1.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_rom1.v" 76 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qq71.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_qq71.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qq71 " "Info: Found entity 1: altsyncram_qq71" {  } { { "db/altsyncram_qq71.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/altsyncram_qq71.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qq71 lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated " "Info: Elaborating entity \"altsyncram_qq71\" for hierarchy \"lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom0.v 1 1 " "Warning: Using design file lpm_rom0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom0 " "Info: Found entity 1: lpm_rom0" {  } { { "lpm_rom0.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_rom0.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom0 lpm_rom0:inst1 " "Info: Elaborating entity \"lpm_rom0\" for hierarchy \"lpm_rom0:inst1\"" {  } { { "block.bdf" "inst1" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 592 1040 1200 688 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram lpm_rom0:inst1\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"lpm_rom0:inst1\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom0.v" "altsyncram_component" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_rom0.v" 76 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_rom0:inst1\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"lpm_rom0:inst1\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom0.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_rom0.v" 76 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_oh91.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_oh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_oh91 " "Info: Found entity 1: altsyncram_oh91" {  } { { "db/altsyncram_oh91.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/altsyncram_oh91.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_oh91 lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated " "Info: Elaborating entity \"altsyncram_oh91\" for hierarchy \"lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "makeup_sign makeup_sign:inst32 " "Info: Elaborating entity \"makeup_sign\" for hierarchy \"makeup_sign:inst32\"" {  } { { "block.bdf" "inst32" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 704 272 464 800 "inst32" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom2.v 1 1 " "Warning: Using design file lpm_rom2.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom2 " "Info: Found entity 1: lpm_rom2" {  } { { "lpm_rom2.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_rom2.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom2 lpm_rom2:inst19 " "Info: Elaborating entity \"lpm_rom2\" for hierarchy \"lpm_rom2:inst19\"" {  } { { "block.bdf" "inst19" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 688 96 256 784 "inst19" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram lpm_rom2:inst19\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"lpm_rom2:inst19\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom2.v" "altsyncram_component" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_rom2.v" 76 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_rom2:inst19\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"lpm_rom2:inst19\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom2.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_rom2.v" 76 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_kfa1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_kfa1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_kfa1 " "Info: Found entity 1: altsyncram_kfa1" {  } { { "db/altsyncram_kfa1.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/altsyncram_kfa1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_kfa1 lpm_rom2:inst19\|altsyncram:altsyncram_component\|altsyncram_kfa1:auto_generated " "Info: Elaborating entity \"altsyncram_kfa1\" for hierarchy \"lpm_rom2:inst19\|altsyncram:altsyncram_component\|altsyncram_kfa1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_counter0.v 1 1 " "Warning: Using design file lpm_counter0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter0 " "Info: Found entity 1: lpm_counter0" {  } { { "lpm_counter0.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_counter0.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter0 lpm_counter0:inst4 " "Info: Elaborating entity \"lpm_counter0\" for hierarchy \"lpm_counter0:inst4\"" {  } { { "block.bdf" "inst4" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 640 -232 -88 704 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 248 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter lpm_counter0:inst4\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.v" "lpm_counter_component" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_counter0.v" 64 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_counter0.v" 64 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_qkh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_qkh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_qkh " "Info: Found entity 1: cntr_qkh" {  } { { "db/cntr_qkh.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cntr_qkh.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_qkh lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qkh:auto_generated " "Info: Elaborating entity \"cntr_qkh\" for hierarchy \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_qkh:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 272 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "block_new block_new:inst45 " "Info: Elaborating entity \"block_new\" for hierarchy \"block_new:inst45\"" {  } { { "block.bdf" "inst45" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 208 1848 2032 368 "inst45" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd 7 2 " "Info: Found 7 design units, including 2 entities, in source file e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_signaltap_pack " "Info: Found design unit 1: sld_signaltap_pack" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 62 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_signaltap_lib " "Info: Found design unit 2: sld_signaltap_lib" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 70 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_signaltap_lib-body " "Info: Found design unit 3: sld_signaltap_lib-body" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 75 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_signaltap-rtl " "Info: Found design unit 4: sld_signaltap-rtl" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 229 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 sld_signaltap_impl-rtl " "Info: Found design unit 5: sld_signaltap_impl-rtl" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 522 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_signaltap " "Info: Found entity 1: sld_signaltap" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 131 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_signaltap_impl " "Info: Found entity 2: sld_signaltap_impl" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 433 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file e:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_ela_control-rtl " "Info: Found design unit 1: sld_ela_control-rtl" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" 129 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_ela_basic_multi_level_trigger-rtl " "Info: Found design unit 2: sld_ela_basic_multi_level_trigger-rtl" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" 702 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_ela_control " "Info: Found entity 1: sld_ela_control" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" 71 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_ela_basic_multi_level_trigger " "Info: Found entity 2: sld_ela_basic_multi_level_trigger" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" 669 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "LPM_SHIFTREG.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf" 39 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/sld_mbpmg.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file e:/altera/72/quartus/libraries/megafunctions/sld_mbpmg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_mbpmg-rtl " "Info: Found design unit 1: sld_mbpmg-rtl" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_mbpmg.vhd" 65 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_sbpmg-rtl " "Info: Found design unit 2: sld_sbpmg-rtl" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_mbpmg.vhd" 298 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_mbpmg " "Info: Found entity 1: sld_mbpmg" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_mbpmg.vhd" 44 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_sbpmg " "Info: Found entity 2: sld_sbpmg" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_mbpmg.vhd" 277 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_ela_trigger_flow_mgr-rtl " "Info: Found design unit 1: sld_ela_trigger_flow_mgr-rtl" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 43 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_ela_trigger_flow_mgr " "Info: Found entity 1: sld_ela_trigger_flow_mgr" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_buffer_manager-rtl " "Info: Found design unit 1: sld_buffer_manager-rtl" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 84 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_offload_buffer_mgr-rtl " "Info: Found design unit 2: sld_offload_buffer_mgr-rtl" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 354 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_buffer_manager " "Info: Found entity 1: sld_buffer_manager" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 47 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_offload_buffer_mgr " "Info: Found entity 2: sld_offload_buffer_mgr" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 310 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_m7p3.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_m7p3.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_m7p3 " "Info: Found entity 1: altsyncram_m7p3" {  } { { "db/altsyncram_m7p3.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/altsyncram_m7p3.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_2hq1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_2hq1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_2hq1 " "Info: Found entity 1: altsyncram_2hq1" {  } { { "db/altsyncram_2hq1.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/altsyncram_2hq1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/altdpram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/altdpram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altdpram " "Info: Found entity 1: altdpram" {  } { { "altdpram.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/altdpram.tdf" 180 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "lpm_mux.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_mux.tdf" 74 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_9oc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_9oc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_9oc " "Info: Found entity 1: mux_9oc" {  } { { "db/mux_9oc.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/mux_9oc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "lpm_decode.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/lpm_decode.tdf" 64 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_rqf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_rqf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_rqf " "Info: Found entity 1: decode_rqf" {  } { { "db/decode_rqf.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/decode_rqf.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_hbi.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_hbi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_hbi " "Info: Found entity 1: cntr_hbi" {  } { { "db/cntr_hbi.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cntr_hbi.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_c4j.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_c4j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_c4j " "Info: Found entity 1: cntr_c4j" {  } { { "db/cntr_c4j.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cntr_c4j.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_bbi.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_bbi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_bbi " "Info: Found entity 1: cntr_bbi" {  } { { "db/cntr_bbi.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cntr_bbi.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_uti.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_uti.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_uti " "Info: Found entity 1: cntr_uti" {  } { { "db/cntr_uti.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cntr_uti.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_AE_SUCCESSFUL" "auto_signaltap_0 " "Info: Analysis and Synthesis generated SignalTap II or debug node instance \"auto_signaltap_0\"" {  } {  } 0 0 "Analysis and Synthesis generated SignalTap II or debug node instance \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "p2s:inst28\|cnt p2s:inst13\|cnt " "Info: Duplicate register \"p2s:inst28\|cnt\" merged to single register \"p2s:inst13\|cnt\"" {  } { { "p2s.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/p2s.v" 9 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "s2p:inst6\|cnt s2p:inst7\|cnt " "Info: Duplicate register \"s2p:inst6\|cnt\" merged to single register \"s2p:inst7\|cnt\"" {  } { { "s2p.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/s2p.v" 9 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "butterfly:inst48\|real_a\[15\] butterfly:inst48\|real_a\[16\] " "Info: Duplicate register \"butterfly:inst48\|real_a\[15\]\" merged to single register \"butterfly:inst48\|real_a\[16\]\"" {  } { { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 64 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "butterfly:inst48\|imag_a\[15\] butterfly:inst48\|imag_a\[16\] " "Info: Duplicate register \"butterfly:inst48\|imag_a\[15\]\" merged to single register \"butterfly:inst48\|imag_a\[16\]\"" {  } { { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 64 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "butterfly:inst48\|real_b\[15\] butterfly:inst48\|real_b\[16\] " "Info: Duplicate register \"butterfly:inst48\|real_b\[15\]\" merged to single register \"butterfly:inst48\|real_b\[16\]\"" {  } { { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 64 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "butterfly:inst48\|imag_b\[15\] butterfly:inst48\|imag_b\[16\] " "Info: Duplicate register \"butterfly:inst48\|imag_b\[15\]\" merged to single register \"butterfly:inst48\|imag_b\[16\]\"" {  } { { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 64 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "butterfly:inst48\|real_WN_in\[15\] butterfly:inst48\|real_WN_in\[16\] " "Info: Duplicate register \"butterfly:inst48\|real_WN_in\[15\]\" merged to single register \"butterfly:inst48\|real_WN_in\[16\]\"" {  } { { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 64 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "butterfly:inst48\|imag_WN_in\[15\] butterfly:inst48\|imag_WN_in\[16\] " "Info: Duplicate register \"butterfly:inst48\|imag_WN_in\[15\]\" merged to single register \"butterfly:inst48\|imag_WN_in\[16\]\"" {  } { { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 64 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "s2p:inst6\|count\[6\] s2p:inst7\|count\[6\] " "Info: Duplicate register \"s2p:inst6\|count\[6\]\" merged to single register \"s2p:inst7\|count\[6\]\"" {  } { { "s2p.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/s2p.v" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "s2p:inst6\|count\[5\] s2p:inst7\|count\[5\] " "Info: Duplicate register \"s2p:inst6\|count\[5\]\" merged to single register \"s2p:inst7\|count\[5\]\"" {  } { { "s2p.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/s2p.v" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "s2p:inst6\|count\[4\] s2p:inst7\|count\[4\] " "Info: Duplicate register \"s2p:inst6\|count\[4\]\" merged to single register \"s2p:inst7\|count\[4\]\"" {  } { { "s2p.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/s2p.v" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "s2p:inst6\|count\[3\] s2p:inst7\|count\[3\] " "Info: Duplicate register \"s2p:inst6\|count\[3\]\" merged to single register \"s2p:inst7\|count\[3\]\"" {  } { { "s2p.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/s2p.v" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "s2p:inst6\|count\[2\] s2p:inst7\|count\[2\] " "Info: Duplicate register \"s2p:inst6\|count\[2\]\" merged to single register \"s2p:inst7\|count\[2\]\"" {  } { { "s2p.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/s2p.v" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "s2p:inst6\|count\[1\] s2p:inst7\|count\[1\] " "Info: Duplicate register \"s2p:inst6\|count\[1\]\" merged to single register \"s2p:inst7\|count\[1\]\"" {  } { { "s2p.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/s2p.v" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "s2p:inst6\|count\[0\] s2p:inst7\|count\[0\] " "Info: Duplicate register \"s2p:inst6\|count\[0\]\" merged to single register \"s2p:inst7\|count\[0\]\"" {  } { { "s2p.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/s2p.v" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "p2s:inst13\|data_temp\[0\]\[16\] p2s:inst13\|data_temp\[0\]\[17\] " "Info: Duplicate register \"p2s:inst13\|data_temp\[0\]\[16\]\" merged to single register \"p2s:inst13\|data_temp\[0\]\[17\]\"" {  } { { "p2s.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/p2s.v" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:adder1\|add_sub_5ii:auto_generated\|pipeline_dffe\[16\] butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:adder1\|add_sub_5ii:auto_generated\|pipeline_dffe\[17\] " "Info: Duplicate register \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:adder1\|add_sub_5ii:auto_generated\|pipeline_dffe\[16\]\" merged to single register \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:adder1\|add_sub_5ii:auto_generated\|pipeline_dffe\[17\]\"" {  } { { "db/add_sub_5ii.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_5ii.tdf" 32 15 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "p2s:inst28\|data_temp\[0\]\[16\] p2s:inst28\|data_temp\[0\]\[17\] " "Info: Duplicate register \"p2s:inst28\|data_temp\[0\]\[16\]\" merged to single register \"p2s:inst28\|data_temp\[0\]\[17\]\"" {  } { { "p2s.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/p2s.v" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|block\|block_new:inst45\|current_state 3 " "Info: State machine \"\|block\|block_new:inst45\|current_state\" contains 3 states" {  } { { "block_new.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/block_new.v" 16 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|block\|butterfly:inst48\|current_state 2 " "Info: State machine \"\|block\|butterfly:inst48\|current_state\" contains 2 states" {  } { { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 14 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|block\|ctrl_fft:inst3\|current_state 4 " "Info: State machine \"\|block\|ctrl_fft:inst3\|current_state\" contains 4 states" {  } { { "ctrl_fft.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd" 17 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|block\|T_control:inst46\|current_state 6 " "Info: State machine \"\|block\|T_control:inst46\|current_state\" contains 6 states" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 18 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|block\|block_new:inst45\|current_state " "Info: Selected Auto state machine encoding method for state machine \"\|block\|block_new:inst45\|current_state\"" {  } { { "block_new.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/block_new.v" 16 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|block\|block_new:inst45\|current_state " "Info: Encoding result for state machine \"\|block\|block_new:inst45\|current_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "block_new:inst45\|current_state.s0 " "Info: Encoded state bit \"block_new:inst45\|current_state.s0\"" {  } { { "block_new.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/block_new.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "block_new:inst45\|current_state.s2 " "Info: Encoded state bit \"block_new:inst45\|current_state.s2\"" {  } { { "block_new.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/block_new.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "block_new:inst45\|current_state.s1 " "Info: Encoded state bit \"block_new:inst45\|current_state.s1\"" {  } { { "block_new.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/block_new.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|block_new:inst45\|current_state.s0 000 " "Info: State \"\|block\|block_new:inst45\|current_state.s0\" uses code string \"000\"" {  } { { "block_new.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/block_new.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|block_new:inst45\|current_state.s1 101 " "Info: State \"\|block\|block_new:inst45\|current_state.s1\" uses code string \"101\"" {  } { { "block_new.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/block_new.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|block_new:inst45\|current_state.s2 110 " "Info: State \"\|block\|block_new:inst45\|current_state.s2\" uses code string \"110\"" {  } { { "block_new.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/block_new.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "block_new.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/block_new.v" 16 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|block\|butterfly:inst48\|current_state " "Info: Selected Auto state machine encoding method for state machine \"\|block\|butterfly:inst48\|current_state\"" {  } { { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 14 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|block\|butterfly:inst48\|current_state " "Info: Encoding result for state machine \"\|block\|butterfly:inst48\|current_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "1 " "Info: Completed encoding using 1 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "butterfly:inst48\|current_state.work " "Info: Encoded state bit \"butterfly:inst48\|current_state.work\"" {  } { { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 64 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|butterfly:inst48\|current_state.idle 0 " "Info: State \"\|block\|butterfly:inst48\|current_state.idle\" uses code string \"0\"" {  } { { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 14 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|butterfly:inst48\|current_state.work 1 " "Info: State \"\|block\|butterfly:inst48\|current_state.work\" uses code string \"1\"" {  } { { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 64 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 14 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|block\|ctrl_fft:inst3\|current_state " "Info: Selected Auto state machine encoding method for state machine \"\|block\|ctrl_fft:inst3\|current_state\"" {  } { { "ctrl_fft.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd" 17 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|block\|ctrl_fft:inst3\|current_state " "Info: Encoding result for state machine \"\|block\|ctrl_fft:inst3\|current_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ctrl_fft:inst3\|current_state.wait_state " "Info: Encoded state bit \"ctrl_fft:inst3\|current_state.wait_state\"" {  } { { "ctrl_fft.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ctrl_fft:inst3\|current_state.assert_eop " "Info: Encoded state bit \"ctrl_fft:inst3\|current_state.assert_eop\"" {  } { { "ctrl_fft.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ctrl_fft:inst3\|current_state.go " "Info: Encoded state bit \"ctrl_fft:inst3\|current_state.go\"" {  } { { "ctrl_fft.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ctrl_fft:inst3\|current_state.idle " "Info: Encoded state bit \"ctrl_fft:inst3\|current_state.idle\"" {  } { { "ctrl_fft.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd" 17 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|ctrl_fft:inst3\|current_state.idle 0000 " "Info: State \"\|block\|ctrl_fft:inst3\|current_state.idle\" uses code string \"0000\"" {  } { { "ctrl_fft.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|ctrl_fft:inst3\|current_state.go 0011 " "Info: State \"\|block\|ctrl_fft:inst3\|current_state.go\" uses code string \"0011\"" {  } { { "ctrl_fft.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|ctrl_fft:inst3\|current_state.assert_eop 0101 " "Info: State \"\|block\|ctrl_fft:inst3\|current_state.assert_eop\" uses code string \"0101\"" {  } { { "ctrl_fft.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|ctrl_fft:inst3\|current_state.wait_state 1001 " "Info: State \"\|block\|ctrl_fft:inst3\|current_state.wait_state\" uses code string \"1001\"" {  } { { "ctrl_fft.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd" 17 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "ctrl_fft.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd" 17 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|block\|T_control:inst46\|current_state " "Info: Selected Auto state machine encoding method for state machine \"\|block\|T_control:inst46\|current_state\"" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 18 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|block\|T_control:inst46\|current_state " "Info: Encoding result for state machine \"\|block\|T_control:inst46\|current_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "6 " "Info: Completed encoding using 6 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "T_control:inst46\|current_state.Pro_write " "Info: Encoded state bit \"T_control:inst46\|current_state.Pro_write\"" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 18 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "T_control:inst46\|current_state.source " "Info: Encoded state bit \"T_control:inst46\|current_state.source\"" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 18 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "T_control:inst46\|current_state.Wait " "Info: Encoded state bit \"T_control:inst46\|current_state.Wait\"" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 18 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "T_control:inst46\|current_state.Pro_read " "Info: Encoded state bit \"T_control:inst46\|current_state.Pro_read\"" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 18 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "T_control:inst46\|current_state.sink " "Info: Encoded state bit \"T_control:inst46\|current_state.sink\"" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 18 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "T_control:inst46\|current_state.idle " "Info: Encoded state bit \"T_control:inst46\|current_state.idle\"" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 18 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|T_control:inst46\|current_state.idle 000000 " "Info: State \"\|block\|T_control:inst46\|current_state.idle\" uses code string \"000000\"" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 18 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|T_control:inst46\|current_state.sink 000011 " "Info: State \"\|block\|T_control:inst46\|current_state.sink\" uses code string \"000011\"" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 18 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|T_control:inst46\|current_state.Pro_read 000101 " "Info: State \"\|block\|T_control:inst46\|current_state.Pro_read\" uses code string \"000101\"" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 18 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|T_control:inst46\|current_state.Wait 001001 " "Info: State \"\|block\|T_control:inst46\|current_state.Wait\" uses code string \"001001\"" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 18 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|T_control:inst46\|current_state.source 010001 " "Info: State \"\|block\|T_control:inst46\|current_state.source\" uses code string \"010001\"" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 18 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|T_control:inst46\|current_state.Pro_write 100001 " "Info: State \"\|block\|T_control:inst46\|current_state.Pro_write\" uses code string \"100001\"" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 18 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 18 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "ctrl_fft:inst3\|current_state.assert_eop ctrl_fft:inst3\|sink_eop " "Info: Duplicate register \"ctrl_fft:inst3\|current_state.assert_eop\" merged to single register \"ctrl_fft:inst3\|sink_eop\"" {  } { { "ctrl_fft.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd" 17 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSHIFT_TAPS_INFERRED" "butterfly:inst48\|ADD_17:add_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_vmg:auto_generated\|pipeline_dffe\[32\]~68 " "Info: Inferred altshift_taps megafunction from the following design logic: \"butterfly:inst48\|ADD_17:add_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_vmg:auto_generated\|pipeline_dffe\[32\]~68\"" { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMBER_OF_TAPS 1 " "Info: Parameter NUMBER_OF_TAPS set to 1" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "TAP_DISTANCE 3 " "Info: Parameter TAP_DISTANCE set to 3" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH 34 " "Info: Parameter WIDTH set to 34" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0}  } { { "db/add_sub_vmg.tdf" "pipeline_dffe\[32\]~68" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_vmg.tdf" 30 15 0 } }  } 0 0 "Inferred altshift_taps megafunction from the following design logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_counter:status_read_pointer_counter\|cntr_uti:auto_generated\|current_reg_q_w\[0\] data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_counter:status_read_pointer_counter\|cntr_uti:auto_generated\|current_reg_q_w\[0\]\" with stuck data_in port to stuck value GND" {  } { { "db/cntr_uti.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cntr_uti.tdf" 49 17 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|xraddr\[0\] data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|xraddr\[0\]\" with stuck data_in port to stuck value GND" {  } { { "altdpram.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/altdpram.tdf" 427 12 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[0\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[0\] " "Info: Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[0\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[0\]\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[1\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[1\] " "Info: Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[1\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[1\]\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[2\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[2\] " "Info: Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[2\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[2\]\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[3\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[3\] " "Info: Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[3\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[3\]\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[4\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[4\] " "Info: Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[4\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[4\]\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[5\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[5\] " "Info: Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[5\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[5\]\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[6\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[6\] " "Info: Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[6\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[6\]\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[7\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[7\] " "Info: Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[7\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[7\]\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[8\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[8\] " "Info: Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[8\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[8\]\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[9\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[9\] " "Info: Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[9\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[9\]\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[10\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[10\] " "Info: Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[10\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[10\]\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state 11 " "Info: State machine \"\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state\" contains 11 states" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state " "Info: Selected Auto state machine encoding method for state machine \"\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_OPT_REPORT_SAFE_STATE_MACHINE" "\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state " "Info: State machine \"\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state\" will be implemented as a safe state machine." {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state " "Info: Encoding result for state machine \"\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "11 " "Info: Completed encoding using 11 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s10 " "Info: Encoded state bit \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s10\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s9 " "Info: Encoded state bit \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s9\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s8 " "Info: Encoded state bit \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s8\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s7 " "Info: Encoded state bit \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s7\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s6 " "Info: Encoded state bit \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s6\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s5 " "Info: Encoded state bit \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s5\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s4 " "Info: Encoded state bit \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s4\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s3 " "Info: Encoded state bit \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s3\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s2 " "Info: Encoded state bit \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s2\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s1 " "Info: Encoded state bit \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s1\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s0 " "Info: Encoded state bit \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s0\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s0 00000000000 " "Info: State \"\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s0\" uses code string \"00000000000\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s1 00000000011 " "Info: State \"\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s1\" uses code string \"00000000011\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s2 00000000101 " "Info: State \"\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s2\" uses code string \"00000000101\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s3 00000001001 " "Info: State \"\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s3\" uses code string \"00000001001\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s4 00000010001 " "Info: State \"\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s4\" uses code string \"00000010001\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s5 00000100001 " "Info: State \"\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s5\" uses code string \"00000100001\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s6 00001000001 " "Info: State \"\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s6\" uses code string \"00001000001\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s7 00010000001 " "Info: State \"\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s7\" uses code string \"00010000001\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s8 00100000001 " "Info: State \"\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s8\" uses code string \"00100000001\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s9 01000000001 " "Info: State \"\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s9\" uses code string \"01000000001\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s10 10000000001 " "Info: State \"\|block\|sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s10\" uses code string \"10000000001\"" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s2 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s2\" with stuck data_in port to stuck value GND" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s3 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s3\" with stuck data_in port to stuck value GND" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s4 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s4\" with stuck data_in port to stuck value GND" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s5 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s5\" with stuck data_in port to stuck value GND" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s6 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s6\" with stuck data_in port to stuck value GND" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s7 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s7\" with stuck data_in port to stuck value GND" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s8 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s8\" with stuck data_in port to stuck value GND" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s9 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s9\" with stuck data_in port to stuck value GND" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s10 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s10\" with stuck data_in port to stuck value GND" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/72/quartus/libraries/megafunctions/altshift_taps.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/altshift_taps.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift_taps " "Info: Found entity 1: altshift_taps" {  } { { "altshift_taps.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/altshift_taps.tdf" 45 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "butterfly:inst48\|ADD_17:add_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_vmg:auto_generated\|altshift_taps:pipeline_dffe_rtl_0 " "Info: Elaborated megafunction instantiation \"butterfly:inst48\|ADD_17:add_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_vmg:auto_generated\|altshift_taps:pipeline_dffe_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/shift_taps_5hp.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/shift_taps_5hp.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 shift_taps_5hp " "Info: Found entity 1: shift_taps_5hp" {  } { { "db/shift_taps_5hp.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/shift_taps_5hp.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_hg31.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_hg31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_hg31 " "Info: Found entity 1: altsyncram_hg31" {  } { { "db/altsyncram_hg31.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/altsyncram_hg31.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_gvd.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_gvd.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_gvd " "Info: Found entity 1: add_sub_gvd" {  } { { "db/add_sub_gvd.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_gvd.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_kkf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_kkf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_kkf " "Info: Found entity 1: cntr_kkf" {  } { { "db/cntr_kkf.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cntr_kkf.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "13 13 " "Info: 13 registers lost all their fanouts during netlist optimizations. The first 13 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor3\|add_sub_i5j:auto_generated\|pipeline_dffe\[34\] " "Info: Register \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor3\|add_sub_i5j:auto_generated\|pipeline_dffe\[34\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add6\|mult_add_ie81:auto_generated\|dffe2a\[34\] " "Info: Register \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add6\|mult_add_ie81:auto_generated\|dffe2a\[34\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor3\|add_sub_i5j:auto_generated\|pipeline_dffe\[33\] " "Info: Register \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor3\|add_sub_i5j:auto_generated\|pipeline_dffe\[33\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add6\|mult_add_ie81:auto_generated\|dffe2a\[33\] " "Info: Register \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add6\|mult_add_ie81:auto_generated\|dffe2a\[33\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor2\|add_sub_5ji:auto_generated\|pipeline_dffe\[34\] " "Info: Register \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor2\|add_sub_5ji:auto_generated\|pipeline_dffe\[34\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor2\|add_sub_5ji:auto_generated\|pipeline_dffe\[33\] " "Info: Register \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor2\|add_sub_5ji:auto_generated\|pipeline_dffe\[33\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add6\|mult_add_ie81:auto_generated\|dffe2a\[35\] " "Info: Register \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add6\|mult_add_ie81:auto_generated\|dffe2a\[35\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add2\|mult_add_dqa1:auto_generated\|dffe2a\[33\] " "Info: Register \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add2\|mult_add_dqa1:auto_generated\|dffe2a\[33\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add1\|mult_add_dqa1:auto_generated\|dffe2a\[33\] " "Info: Register \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|altmult_add:mult_add1\|mult_add_dqa1:auto_generated\|dffe2a\[33\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "butterfly:inst48\|current_state~15 " "Info: Register \"butterfly:inst48\|current_state~15\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "T_control:inst46\|current_state~14 " "Info: Register \"T_control:inst46\|current_state~14\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "T_control:inst46\|current_state~15 " "Info: Register \"T_control:inst46\|current_state~15\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "T_control:inst46\|current_state~16 " "Info: Register \"T_control:inst46\|current_state~16\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Info: Found the following redundant logic cells in design" {  } {  } 0 0 "Found the following redundant logic cells in design" 0 0 "" 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Warning" "WOPT_OPT_NOT_GATE_PUSH_BACK_ENFORCED" "" "Warning: NOT_GATE_PUSH_BACK-forbidden assignments are ignored" { { "Warning" "WOPT_OPT_NOT_GATE_PUSH_BACK_ENFORCED_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[0\] " "Warning: NOT_GATE_PUSH_BACK performed on sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[0\]" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "NOT_GATE_PUSH_BACK performed on %1!s!" 0 0 "" 0}  } {  } 0 0 "NOT_GATE_PUSH_BACK-forbidden assignments are ignored" 0 0 "" 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0}
{ "Critical Warning" "WFTM_FTM_POWER_UP_HIGH_IGNORED_GROUP" "" "Critical Warning: Ignored Power-Up Level option on the following registers" { { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[0\] High " "Critical Warning: Register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[0\] will power up to High" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[5\] High " "Critical Warning: Register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[5\] will power up to High" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[6\] High " "Critical Warning: Register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[6\] will power up to High" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[2\] High " "Critical Warning: Register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[2\] will power up to High" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[10\] High " "Critical Warning: Register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[10\] will power up to High" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[4\] High " "Critical Warning: Register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[4\] will power up to High" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[7\] High " "Critical Warning: Register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[7\] will power up to High" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[8\] High " "Critical Warning: Register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[8\] will power up to High" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[1\] High " "Critical Warning: Register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[1\] will power up to High" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[11\] High " "Critical Warning: Register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[11\] will power up to High" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[9\] High " "Critical Warning: Register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[9\] will power up to High" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[3\] High " "Critical Warning: Register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|modified_post_count\[3\] will power up to High" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0}  } {  } 1 0 "Ignored Power-Up Level option on the following registers" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "23 23 " "Info: 23 registers lost all their fanouts during netlist optimizations. The first 23 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[22\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[22\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[21\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[21\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[20\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[20\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[19\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[19\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[18\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[18\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[17\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[17\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[16\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[16\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[15\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[15\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[14\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[14\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[13\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[13\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[12\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[12\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[11\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[11\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[10\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[10\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[9\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[8\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[8\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[7\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[7\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[6\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[6\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[5\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[5\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[4\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[4\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[3\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[3\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[2\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[2\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[1\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[1\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[0\] " "Info: Register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|altdpram:\\stp_non_zero_ram_gen:attribute_mem\|cells\[1\]\[0\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Documents and Settings/wangwei/桌面/FFT last edition/FFT.map.smsg " "Info: Generated suppressed messages file C:/Documents and Settings/wangwei/桌面/FFT last edition/FFT.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Critical Warning" "WAMERGE_TAP_SOURCE_DOES_NOT_EXIST" "sld_signaltap:auto_signaltap_0 sin\[16\] " "Critical Warning: Can't connect signal \"sin\[16\]\" to SignalTap II instance \"sld_signaltap:auto_signaltap_0\" because the signal does not exist" {  } {  } 1 0 "Can't connect signal \"%2!s!\" to SignalTap II instance \"%1!s!\" because the signal does not exist" 0 0 "" 0}
{ "Critical Warning" "WAMERGE_TAP_SOURCE_DOES_NOT_EXIST" "sld_signaltap:auto_signaltap_0 sin\[16\] " "Critical Warning: Can't connect signal \"sin\[16\]\" to SignalTap II instance \"sld_signaltap:auto_signaltap_0\" because the signal does not exist" {  } {  } 1 0 "Can't connect signal \"%2!s!\" to SignalTap II instance \"%1!s!\" because the signal does not exist" 0 0 "" 0}
{ "Critical Warning" "WAMERGE_TAP_SOURCE_DOES_NOT_EXIST" "sld_signaltap:auto_signaltap_0 sin\[17\] " "Critical Warning: Can't connect signal \"sin\[17\]\" to SignalTap II instance \"sld_signaltap:auto_signaltap_0\" because the signal does not exist" {  } {  } 1 0 "Can't connect signal \"%2!s!\" to SignalTap II instance \"%1!s!\" because the signal does not exist" 0 0 "" 0}
{ "Critical Warning" "WAMERGE_TAP_SOURCE_DOES_NOT_EXIST" "sld_signaltap:auto_signaltap_0 sin\[17\] " "Critical Warning: Can't connect signal \"sin\[17\]\" to SignalTap II instance \"sld_signaltap:auto_signaltap_0\" because the signal does not exist" {  } {  } 1 0 "Can't connect signal \"%2!s!\" to SignalTap II instance \"%1!s!\" because the signal does not exist" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "2666 " "Info: Implemented 2666 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "54 " "Info: Implemented 54 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "2390 " "Info: Implemented 2390 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_RAMS" "210 " "Info: Implemented 210 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0} { "Info" "ICUT_CUT_TM_DSP_ELEM" "6 " "Info: Implemented 6 DSP elements" {  } {  } 0 0 "Implemented %1!d! DSP elements" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 54 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 54 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "199 " "Info: Allocated 199 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 06 17:02:03 2010 " "Info: Processing ended: Sun Jun 06 17:02:03 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:03:21 " "Info: Elapsed time: 00:03:21" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 06 17:02:55 2010 " "Info: Processing started: Sun Jun 06 17:02:55 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off FFT -c FFT " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off FFT -c FFT" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "FFT EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"FFT\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "high junction temperature 85 " "Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "low junction temperature 0 " "Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "3 0 " "Info: The Fitter has identified 3 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "1756 Top " "Info: Previous placement does not exist for 1756 of 1756 atoms in partition Top" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0} { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "1362 sld_signaltap:auto_signaltap_0 " "Info: Previous placement does not exist for 1362 of 1362 atoms in partition sld_signaltap:auto_signaltap_0" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0} { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "176 sld_hub:sld_hub_inst " "Info: Previous placement does not exist for 176 of 176 atoms in partition sld_hub:sld_hub_inst" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0}  } {  } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" {  } { { "e:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/altera/72/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" {  } { { "e:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/altera/72/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" {  } { { "e:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/altera/72/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN 23 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node clk (placed in PIN 23 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "altera_auto_signaltap_0_clk_signaltap_lcell " "Info: Destination node altera_auto_signaltap_0_clk_signaltap_lcell" {  } { { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "altera_auto_signaltap_0_clk_signaltap_lcell" } } } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_auto_signaltap_0_clk_signaltap_lcell } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_auto_signaltap_0_clk_signaltap_lcell } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/altera/72/quartus/bin/pin_planner.ppl" { clk } } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 328 80 248 344 "clk" "" } { 304 864 936 320 "clk" "" } { 256 1448 1488 272 "clk" "" } { 80 1752 1808 96 "clk" "" } { 88 1280 1352 104 "clk" "" } { -80 1272 1344 -64 "clk" "" } { 624 992 1040 640 "clk" "" } { 736 992 1040 752 "clk" "" } { 448 880 936 464 "clk" "" } { 320 248 368 336 "clk" "" } { 608 1472 1496 624 "clk" "" } { 720 1472 1504 736 "clk" "" } { 720 1224 1256 736 "clk" "" } { 608 1216 1248 624 "clk" "" } { 448 1784 1840 464 "clk" "" } { 224 1808 1848 240 "clk" "" } { 368 -184 -120 384 "clk" "" } { 656 -312 -232 672 "clk" "" } { 352 -408 -344 368 "clk" "" } { 720 0 96 736 "clk" "" } } } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Info: Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset_ctrl:inst5\|clk_c  " "Info: Automatically promoted node reset_ctrl:inst5\|clk_c " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "T_control:inst46\|sink_ready~22 " "Info: Destination node T_control:inst46\|sink_ready~22" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 8 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { T_control:inst46|sink_ready~22 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { T_control:inst46|sink_ready~22 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ctrl_fft:inst3\|Selector0~42 " "Info: Destination node ctrl_fft:inst3\|Selector0~42" {  } { { "ctrl_fft.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd" 23 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ctrl_fft:inst3|Selector0~42 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ctrl_fft:inst3|Selector0~42 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ctrl_fft:inst3\|current_state.idle~77 " "Info: Destination node ctrl_fft:inst3\|current_state.idle~77" {  } { { "ctrl_fft.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd" 17 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ctrl_fft:inst3|current_state.idle~77 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ctrl_fft:inst3|current_state.idle~77 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|valid_wreq~35 " "Info: Destination node lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|valid_wreq~35" {  } { { "db/a_dpfifo_e141.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/a_dpfifo_e141.tdf" 48 2 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|valid_wreq~35 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|valid_wreq~35 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|valid_rreq " "Info: Destination node lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|valid_rreq" {  } { { "db/a_dpfifo_e141.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/a_dpfifo_e141.tdf" 47 2 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|valid_rreq } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|valid_rreq } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "s2p:inst6\|source_valid " "Info: Destination node s2p:inst6\|source_valid" {  } { { "s2p.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/s2p.v" 5 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { s2p:inst6|source_valid } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { s2p:inst6|source_valid } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|valid_wreq~33 " "Info: Destination node lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|valid_wreq~33" {  } { { "db/a_dpfifo_e141.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/a_dpfifo_e141.tdf" 48 2 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|valid_wreq~33 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|valid_wreq~33 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|valid_rreq " "Info: Destination node lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|valid_rreq" {  } { { "db/a_dpfifo_e141.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/a_dpfifo_e141.tdf" 47 2 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|valid_rreq } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|valid_rreq } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|a_fefifo_b6f:fifo_state\|b_full~132 " "Info: Destination node lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|a_fefifo_b6f:fifo_state\|b_full~132" {  } { { "db/a_fefifo_b6f.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/a_fefifo_b6f.tdf" 36 2 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|a_fefifo_b6f:fifo_state|b_full~132 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|a_fefifo_b6f:fifo_state|b_full~132 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "T_control:inst46\|rdreq_fifo~58 " "Info: Destination node T_control:inst46\|rdreq_fifo~58" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 8 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { T_control:inst46|rdreq_fifo~58 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { T_control:inst46|rdreq_fifo~58 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" {  } {  } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "reset_ctrl.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/reset_ctrl.vhd" 8 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset_ctrl:inst5|clk_c } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset_ctrl:inst5|clk_c } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|reset_all  " "Info: Automatically promoted node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|reset_all " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset " "Info: Destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 385 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 737 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|reset_all } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|reset_all } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|CLR_SIGNAL  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|CLR_SIGNAL " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|CLR_SIGNAL~_wirecell " "Info: Destination node sld_hub:sld_hub_inst\|CLR_SIGNAL~_wirecell" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL~_wirecell } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL~_wirecell } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|CLR_SIGNAL" } } } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~442 " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~442" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 1148 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~442 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~442 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5 " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 1148 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]~_wirecell " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]~_wirecell" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 1163 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]~_wirecell } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]~_wirecell } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 1163 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset  " "Info: Automatically promoted node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 385 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|offload_shift_ena  " "Info: Automatically promoted node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|offload_shift_ena " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|ram_shift_load " "Info: Destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|ram_shift_load" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 370 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|ram_shift_load } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|ram_shift_load } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 364 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|offload_shift_ena } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|offload_shift_ena } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:01 " "Info: Finished register packing: elapsed time is 00:00:01" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "36 Embedded multiplier block " "Extra Info: Packed 36 registers into blocks of type Embedded multiplier block" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "99 Embedded multiplier output " "Extra Info: Packed 99 registers into blocks of type Embedded multiplier output" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "1 " "Extra Info: Created 1 register duplicates" {  } {  } 1 0 "Created %1!d! register duplicates" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Warning: Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "sin\[16\] " "Warning: Ignored I/O standard assignment to node \"sin\[16\]\"" {  } { { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sin\[16\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "sin\[17\] " "Warning: Ignored I/O standard assignment to node \"sin\[17\]\"" {  } { { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sin\[17\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Ignored I/O standard assignments to the following nodes" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "sin\[16\] " "Warning: Node \"sin\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sin\[16\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "sin\[17\] " "Warning: Node \"sin\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sin\[17\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0}  } {  } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:04 " "Info: Fitter placement operations ending: elapsed time is 00:00:04" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.208 ns register register " "Info: Estimated most critical path is register to register delay of 8.208 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns butterfly:inst48\|cnt\[4\] 1 REG LAB_X30_Y6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X30_Y6; Fanout = 3; REG Node = 'butterfly:inst48\|cnt\[4\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { butterfly:inst48|cnt[4] } "NODE_NAME" } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.817 ns) + CELL(0.370 ns) 1.187 ns butterfly:inst48\|LessThan1~176 2 COMB LAB_X31_Y6 3 " "Info: 2: + IC(0.817 ns) + CELL(0.370 ns) = 1.187 ns; Loc. = LAB_X31_Y6; Fanout = 3; COMB Node = 'butterfly:inst48\|LessThan1~176'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.187 ns" { butterfly:inst48|cnt[4] butterfly:inst48|LessThan1~176 } "NODE_NAME" } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.206 ns) 1.998 ns butterfly:inst48\|LessThan1~179 3 COMB LAB_X31_Y6 2 " "Info: 3: + IC(0.605 ns) + CELL(0.206 ns) = 1.998 ns; Loc. = LAB_X31_Y6; Fanout = 2; COMB Node = 'butterfly:inst48\|LessThan1~179'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { butterfly:inst48|LessThan1~176 butterfly:inst48|LessThan1~179 } "NODE_NAME" } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.997 ns) + CELL(0.651 ns) 4.646 ns block_new:inst45\|Head\[1\]~124 4 COMB LAB_X19_Y4 3 " "Info: 4: + IC(1.997 ns) + CELL(0.651 ns) = 4.646 ns; Loc. = LAB_X19_Y4; Fanout = 3; COMB Node = 'block_new:inst45\|Head\[1\]~124'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.648 ns" { butterfly:inst48|LessThan1~179 block_new:inst45|Head[1]~124 } "NODE_NAME" } } { "block_new.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/block_new.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.442 ns) + CELL(0.202 ns) 7.290 ns block_new:inst45\|Selector1~72 5 COMB LAB_X31_Y6 1 " "Info: 5: + IC(2.442 ns) + CELL(0.202 ns) = 7.290 ns; Loc. = LAB_X31_Y6; Fanout = 1; COMB Node = 'block_new:inst45\|Selector1~72'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.644 ns" { block_new:inst45|Head[1]~124 block_new:inst45|Selector1~72 } "NODE_NAME" } } { "block_new.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/block_new.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.650 ns) 8.100 ns block_new:inst45\|Selector1~73 6 COMB LAB_X31_Y6 1 " "Info: 6: + IC(0.160 ns) + CELL(0.650 ns) = 8.100 ns; Loc. = LAB_X31_Y6; Fanout = 1; COMB Node = 'block_new:inst45\|Selector1~73'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.810 ns" { block_new:inst45|Selector1~72 block_new:inst45|Selector1~73 } "NODE_NAME" } } { "block_new.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/block_new.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.208 ns block_new:inst45\|current_state.s1 7 REG LAB_X31_Y6 6 " "Info: 7: + IC(0.000 ns) + CELL(0.108 ns) = 8.208 ns; Loc. = LAB_X31_Y6; Fanout = 6; REG Node = 'block_new:inst45\|current_state.s1'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { block_new:inst45|Selector1~73 block_new:inst45|current_state.s1 } "NODE_NAME" } } { "block_new.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/block_new.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.187 ns ( 26.64 % ) " "Info: Total cell delay = 2.187 ns ( 26.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.021 ns ( 73.36 % ) " "Info: Total interconnect delay = 6.021 ns ( 73.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.208 ns" { butterfly:inst48|cnt[4] butterfly:inst48|LessThan1~176 butterfly:inst48|LessThan1~179 block_new:inst45|Head[1]~124 block_new:inst45|Selector1~72 block_new:inst45|Selector1~73 block_new:inst45|current_state.s1 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "9 " "Info: Average interconnect usage is 9% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "15 X11_Y0 X22_Y9 " "Info: Peak interconnect usage is 15% of the available device resources in the region that extends from location X11_Y0 to location X22_Y9" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:09 " "Info: Fitter routing operations ending: elapsed time is 00:00:09" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_MAIN_TITLE" "1 " "Info: Fitter merged 1 physical RAM blocks that contain multiple logical RAM slices into a single location" { { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_TITLE" "" "Info: Following physical RAM blocks contain multiple logical RAM slices" { { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_PHYSICAL_LOCATION" "M4K_X27_Y13 " "Info: Physical RAM block M4K_X27_Y13 contains the following logical RAM slices" { { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a0 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a0" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a1 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a1" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a2 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a2" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a3 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a3" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a4 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a4" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a5 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a5" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a6 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a6" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a7 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a7" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a8 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a8" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a9 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a9" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a10 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a10" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a11 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a11" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a12 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a12" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a13 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a13" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a14 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a14" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a15 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a15" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a0 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a0" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a1 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a1" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a2 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a2" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a3 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a3" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a4 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a4" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a5 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a5" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a6 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a6" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a7 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a7" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a8 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a8" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a9 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a9" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a10 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a10" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a11 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a11" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a12 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a12" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a13 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a13" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a14 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a14" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a15 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a15" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0}  } {  } 2 0 "Physical RAM block %1!s! contains the following logical RAM slices" 0 0 "" 0}  } {  } 2 0 "Following physical RAM blocks contain multiple logical RAM slices" 0 0 "" 0}  } {  } 2 0 "Fitter merged %1!llu! physical RAM blocks that contain multiple logical RAM slices into a single location" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "53 " "Warning: Found 53 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "source_eop 0 " "Info: Pin \"source_eop\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "source_sop 0 " "Info: Pin \"source_sop\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "source_valid18 0 " "Info: Pin \"source_valid18\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[15\] 0 " "Info: Pin \"Imagdata_out\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[14\] 0 " "Info: Pin \"Imagdata_out\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[13\] 0 " "Info: Pin \"Imagdata_out\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[12\] 0 " "Info: Pin \"Imagdata_out\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[11\] 0 " "Info: Pin \"Imagdata_out\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[10\] 0 " "Info: Pin \"Imagdata_out\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[9\] 0 " "Info: Pin \"Imagdata_out\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[8\] 0 " "Info: Pin \"Imagdata_out\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[7\] 0 " "Info: Pin \"Imagdata_out\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[6\] 0 " "Info: Pin \"Imagdata_out\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[5\] 0 " "Info: Pin \"Imagdata_out\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[4\] 0 " "Info: Pin \"Imagdata_out\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[3\] 0 " "Info: Pin \"Imagdata_out\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[2\] 0 " "Info: Pin \"Imagdata_out\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[1\] 0 " "Info: Pin \"Imagdata_out\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[0\] 0 " "Info: Pin \"Imagdata_out\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[15\] 0 " "Info: Pin \"Realdata_out\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[14\] 0 " "Info: Pin \"Realdata_out\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[13\] 0 " "Info: Pin \"Realdata_out\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[12\] 0 " "Info: Pin \"Realdata_out\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[11\] 0 " "Info: Pin \"Realdata_out\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[10\] 0 " "Info: Pin \"Realdata_out\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[9\] 0 " "Info: Pin \"Realdata_out\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[8\] 0 " "Info: Pin \"Realdata_out\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[7\] 0 " "Info: Pin \"Realdata_out\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[6\] 0 " "Info: Pin \"Realdata_out\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[5\] 0 " "Info: Pin \"Realdata_out\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[4\] 0 " "Info: Pin \"Realdata_out\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[3\] 0 " "Info: Pin \"Realdata_out\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[2\] 0 " "Info: Pin \"Realdata_out\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[1\] 0 " "Info: Pin \"Realdata_out\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[0\] 0 " "Info: Pin \"Realdata_out\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[15\] 0 " "Info: Pin \"sin\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[14\] 0 " "Info: Pin \"sin\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[13\] 0 " "Info: Pin \"sin\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[12\] 0 " "Info: Pin \"sin\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[11\] 0 " "Info: Pin \"sin\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[10\] 0 " "Info: Pin \"sin\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[9\] 0 " "Info: Pin \"sin\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[8\] 0 " "Info: Pin \"sin\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[7\] 0 " "Info: Pin \"sin\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[6\] 0 " "Info: Pin \"sin\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[5\] 0 " "Info: Pin \"sin\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[4\] 0 " "Info: Pin \"sin\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[3\] 0 " "Info: Pin \"sin\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[2\] 0 " "Info: Pin \"sin\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[1\] 0 " "Info: Pin \"sin\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[0\] 0 " "Info: Pin \"sin\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "state\[1\] 0 " "Info: Pin \"state\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "state\[0\] 0 " "Info: Pin \"state\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|reset_all~clkctrl " "Info: Node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|reset_all~clkctrl uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[19\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[19\] -- routed using non-global resources" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[19] } "NODE_NAME" } } { "LPM_SHIFTREG.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf" 56 7 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[19] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[38\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[38\] -- routed using non-global resources" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[38] } "NODE_NAME" } } { "LPM_SHIFTREG.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf" 56 7 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[38] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[39\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[39\] -- routed using non-global resources" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[39] } "NODE_NAME" } } { "LPM_SHIFTREG.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf" 56 7 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[39] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[21\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[21\] -- routed using non-global resources" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[21] } "NODE_NAME" } } { "LPM_SHIFTREG.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf" 56 7 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[21] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[20\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[20\] -- routed using non-global resources" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[20] } "NODE_NAME" } } { "LPM_SHIFTREG.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf" 56 7 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[20] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|reset_all~clkctrl } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 737 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|reset_all~clkctrl } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|CLR_SIGNAL~clkctrl " "Info: Node sld_hub:sld_hub_inst\|CLR_SIGNAL~clkctrl uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] -- routed using non-global resources" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\] -- routed using non-global resources" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL~clkctrl } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL~clkctrl } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Documents and Settings/wangwei/桌面/FFT last edition/FFT.fit.smsg " "Info: Generated suppressed messages file C:/Documents and Settings/wangwei/桌面/FFT last edition/FFT.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 10 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "196 " "Info: Allocated 196 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 06 17:04:38 2010 " "Info: Processing ended: Sun Jun 06 17:04:38 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:01:43 " "Info: Elapsed time: 00:01:43" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 06 17:05:34 2010 " "Info: Processing started: Sun Jun 06 17:05:34 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off FFT -c FFT " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off FFT -c FFT" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "151 " "Info: Allocated 151 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 06 17:06:04 2010 " "Info: Processing ended: Sun Jun 06 17:06:04 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Info: Elapsed time: 00:00:30" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 06 17:06:16 2010 " "Info: Processing started: Sun Jun 06 17:06:16 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off FFT -c FFT --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off FFT -c FFT --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 328 80 248 344 "clk" "" } { 304 864 936 320 "clk" "" } { 256 1448 1488 272 "clk" "" } { 80 1752 1808 96 "clk" "" } { 88 1280 1352 104 "clk" "" } { -80 1272 1344 -64 "clk" "" } { 624 992 1040 640 "clk" "" } { 736 992 1040 752 "clk" "" } { 448 880 936 464 "clk" "" } { 320 248 368 336 "clk" "" } { 608 1472 1496 624 "clk" "" } { 720 1472 1504 736 "clk" "" } { 720 1224 1256 736 "clk" "" } { 608 1216 1248 624 "clk" "" } { 448 1784 1840 464 "clk" "" } { 224 1808 1848 240 "clk" "" } { 368 -184 -120 384 "clk" "" } { 656 -312 -232 672 "clk" "" } { 352 -408 -344 368 "clk" "" } { 720 0 96 736 "clk" "" } } } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register butterfly:inst48\|real_a\[0\] register butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[15\] 117.7 MHz 8.496 ns Internal " "Info: Clock \"clk\" has Internal fmax of 117.7 MHz between source register \"butterfly:inst48\|real_a\[0\]\" and destination register \"butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[15\]\" (period= 8.496 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.501 ns + Longest register register " "Info: + Longest register to register delay is 8.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns butterfly:inst48\|real_a\[0\] 1 REG LCFF_X16_Y11_N17 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y11_N17; Fanout = 4; REG Node = 'butterfly:inst48\|real_a\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { butterfly:inst48|real_a[0] } "NODE_NAME" } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(0.651 ns) 1.123 ns butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[0\]~34 2 COMB LCCOMB_X16_Y11_N16 3 " "Info: 2: + IC(0.472 ns) + CELL(0.651 ns) = 1.123 ns; Loc. = LCCOMB_X16_Y11_N16; Fanout = 3; COMB Node = 'butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[0\]~34'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.123 ns" { butterfly:inst48|real_a[0] butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[0]~34 } "NODE_NAME" } } { "db/add_sub_4qe.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_4qe.tdf" 26 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.309 ns) + CELL(0.735 ns) 4.167 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[0\]~113 3 COMB LCCOMB_X19_Y11_N14 2 " "Info: 3: + IC(2.309 ns) + CELL(0.735 ns) = 4.167 ns; Loc. = LCCOMB_X19_Y11_N14; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[0\]~113'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.044 ns" { butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[0]~34 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[0]~113 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 4.253 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[1\]~115 4 COMB LCCOMB_X19_Y11_N16 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 4.253 ns; Loc. = LCCOMB_X19_Y11_N16; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[1\]~115'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[0]~113 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[1]~115 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 4.339 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[2\]~117 5 COMB LCCOMB_X19_Y11_N18 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 4.339 ns; Loc. = LCCOMB_X19_Y11_N18; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[2\]~117'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[1]~115 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[2]~117 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 4.425 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[3\]~119 6 COMB LCCOMB_X19_Y11_N20 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 4.425 ns; Loc. = LCCOMB_X19_Y11_N20; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[3\]~119'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[2]~117 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[3]~119 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 4.511 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[4\]~121 7 COMB LCCOMB_X19_Y11_N22 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 4.511 ns; Loc. = LCCOMB_X19_Y11_N22; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[4\]~121'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[3]~119 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[4]~121 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 4.597 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[5\]~123 8 COMB LCCOMB_X19_Y11_N24 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 4.597 ns; Loc. = LCCOMB_X19_Y11_N24; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[5\]~123'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[4]~121 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[5]~123 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 4.683 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[6\]~125 9 COMB LCCOMB_X19_Y11_N26 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 4.683 ns; Loc. = LCCOMB_X19_Y11_N26; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[6\]~125'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[5]~123 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[6]~125 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 4.769 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[7\]~127 10 COMB LCCOMB_X19_Y11_N28 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 4.769 ns; Loc. = LCCOMB_X19_Y11_N28; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[7\]~127'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[6]~125 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[7]~127 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.175 ns) 4.944 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[8\]~129 11 COMB LCCOMB_X19_Y11_N30 2 " "Info: 11: + IC(0.000 ns) + CELL(0.175 ns) = 4.944 ns; Loc. = LCCOMB_X19_Y11_N30; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[8\]~129'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.175 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[7]~127 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[8]~129 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.030 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[9\]~131 12 COMB LCCOMB_X19_Y10_N0 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 5.030 ns; Loc. = LCCOMB_X19_Y10_N0; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[9\]~131'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[8]~129 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[9]~131 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.116 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[10\]~133 13 COMB LCCOMB_X19_Y10_N2 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 5.116 ns; Loc. = LCCOMB_X19_Y10_N2; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[10\]~133'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[9]~131 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[10]~133 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.202 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[11\]~135 14 COMB LCCOMB_X19_Y10_N4 2 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 5.202 ns; Loc. = LCCOMB_X19_Y10_N4; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[11\]~135'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[10]~133 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[11]~135 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.288 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[12\]~137 15 COMB LCCOMB_X19_Y10_N6 2 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 5.288 ns; Loc. = LCCOMB_X19_Y10_N6; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[12\]~137'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[11]~135 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[12]~137 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.374 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[13\]~139 16 COMB LCCOMB_X19_Y10_N8 2 " "Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 5.374 ns; Loc. = LCCOMB_X19_Y10_N8; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[13\]~139'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[12]~137 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[13]~139 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.460 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[14\]~141 17 COMB LCCOMB_X19_Y10_N10 2 " "Info: 17: + IC(0.000 ns) + CELL(0.086 ns) = 5.460 ns; Loc. = LCCOMB_X19_Y10_N10; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[14\]~141'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[13]~139 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[14]~141 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 5.966 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[15\]~142 18 COMB LCCOMB_X19_Y10_N12 1 " "Info: 18: + IC(0.000 ns) + CELL(0.506 ns) = 5.966 ns; Loc. = LCCOMB_X19_Y10_N12; Fanout = 1; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[15\]~142'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[14]~141 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15]~142 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(1.545 ns) 8.501 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[15\] 19 REG DSPMULT_X20_Y10_N0 21 " "Info: 19: + IC(0.990 ns) + CELL(1.545 ns) = 8.501 ns; Loc. = DSPMULT_X20_Y10_N0; Fanout = 21; REG Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[15\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15]~142 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15] } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.730 ns ( 55.64 % ) " "Info: Total cell delay = 4.730 ns ( 55.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.771 ns ( 44.36 % ) " "Info: Total interconnect delay = 3.771 ns ( 44.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.501 ns" { butterfly:inst48|real_a[0] butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[0]~34 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[0]~113 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[1]~115 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[2]~117 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[3]~119 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[4]~121 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[5]~123 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[6]~125 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[7]~127 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[8]~129 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[9]~131 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[10]~133 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[11]~135 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[12]~137 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[13]~139 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[14]~141 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15]~142 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.501 ns" { butterfly:inst48|real_a[0] {} butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[0]~34 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[0]~113 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[1]~115 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[2]~117 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[3]~119 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[4]~121 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[5]~123 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[6]~125 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[7]~127 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[8]~129 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[9]~131 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[10]~133 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[11]~135 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[12]~137 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[13]~139 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[14]~141 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15]~142 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15] {} } { 0.000ns 0.472ns 2.309ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.990ns } { 0.000ns 0.651ns 0.735ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 1.545ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.371 ns - Smallest " "Info: - Smallest clock skew is 0.371 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.214 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.214 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 328 80 248 344 "clk" "" } { 304 864 936 320 "clk" "" } { 256 1448 1488 272 "clk" "" } { 80 1752 1808 96 "clk" "" } { 88 1280 1352 104 "clk" "" } { -80 1272 1344 -64 "clk" "" } { 624 992 1040 640 "clk" "" } { 736 992 1040 752 "clk" "" } { 448 880 936 464 "clk" "" } { 320 248 368 336 "clk" "" } { 608 1472 1496 624 "clk" "" } { 720 1472 1504 736 "clk" "" } { 720 1224 1256 736 "clk" "" } { 608 1216 1248 624 "clk" "" } { 448 1784 1840 464 "clk" "" } { 224 1808 1848 240 "clk" "" } { 368 -184 -120 384 "clk" "" } { 656 -312 -232 672 "clk" "" } { 352 -408 -344 368 "clk" "" } { 720 0 96 736 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 2133 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 2133; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 328 80 248 344 "clk" "" } { 304 864 936 320 "clk" "" } { 256 1448 1488 272 "clk" "" } { 80 1752 1808 96 "clk" "" } { 88 1280 1352 104 "clk" "" } { -80 1272 1344 -64 "clk" "" } { 624 992 1040 640 "clk" "" } { 736 992 1040 752 "clk" "" } { 448 880 936 464 "clk" "" } { 320 248 368 336 "clk" "" } { 608 1472 1496 624 "clk" "" } { 720 1472 1504 736 "clk" "" } { 720 1224 1256 736 "clk" "" } { 608 1216 1248 624 "clk" "" } { 448 1784 1840 464 "clk" "" } { 224 1808 1848 240 "clk" "" } { 368 -184 -120 384 "clk" "" } { 656 -312 -232 672 "clk" "" } { 352 -408 -344 368 "clk" "" } { 720 0 96 736 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.798 ns) + CELL(1.137 ns) 3.214 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[15\] 3 REG DSPMULT_X20_Y10_N0 21 " "Info: 3: + IC(0.798 ns) + CELL(1.137 ns) = 3.214 ns; Loc. = DSPMULT_X20_Y10_N0; Fanout = 21; REG Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[15\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.935 ns" { clk~clkctrl butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15] } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.277 ns ( 70.85 % ) " "Info: Total cell delay = 2.277 ns ( 70.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.937 ns ( 29.15 % ) " "Info: Total interconnect delay = 0.937 ns ( 29.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.214 ns" { clk clk~clkctrl butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.214 ns" { clk {} clk~combout {} clk~clkctrl {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15] {} } { 0.000ns 0.000ns 0.139ns 0.798ns } { 0.000ns 1.140ns 0.000ns 1.137ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.843 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.843 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 328 80 248 344 "clk" "" } { 304 864 936 320 "clk" "" } { 256 1448 1488 272 "clk" "" } { 80 1752 1808 96 "clk" "" } { 88 1280 1352 104 "clk" "" } { -80 1272 1344 -64 "clk" "" } { 624 992 1040 640 "clk" "" } { 736 992 1040 752 "clk" "" } { 448 880 936 464 "clk" "" } { 320 248 368 336 "clk" "" } { 608 1472 1496 624 "clk" "" } { 720 1472 1504 736 "clk" "" } { 720 1224 1256 736 "clk" "" } { 608 1216 1248 624 "clk" "" } { 448 1784 1840 464 "clk" "" } { 224 1808 1848 240 "clk" "" } { 368 -184 -120 384 "clk" "" } { 656 -312 -232 672 "clk" "" } { 352 -408 -344 368 "clk" "" } { 720 0 96 736 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 2133 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 2133; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 328 80 248 344 "clk" "" } { 304 864 936 320 "clk" "" } { 256 1448 1488 272 "clk" "" } { 80 1752 1808 96 "clk" "" } { 88 1280 1352 104 "clk" "" } { -80 1272 1344 -64 "clk" "" } { 624 992 1040 640 "clk" "" } { 736 992 1040 752 "clk" "" } { 448 880 936 464 "clk" "" } { 320 248 368 336 "clk" "" } { 608 1472 1496 624 "clk" "" } { 720 1472 1504 736 "clk" "" } { 720 1224 1256 736 "clk" "" } { 608 1216 1248 624 "clk" "" } { 448 1784 1840 464 "clk" "" } { 224 1808 1848 240 "clk" "" } { 368 -184 -120 384 "clk" "" } { 656 -312 -232 672 "clk" "" } { 352 -408 -344 368 "clk" "" } { 720 0 96 736 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.666 ns) 2.843 ns butterfly:inst48\|real_a\[0\] 3 REG LCFF_X16_Y11_N17 4 " "Info: 3: + IC(0.898 ns) + CELL(0.666 ns) = 2.843 ns; Loc. = LCFF_X16_Y11_N17; Fanout = 4; REG Node = 'butterfly:inst48\|real_a\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { clk~clkctrl butterfly:inst48|real_a[0] } "NODE_NAME" } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.52 % ) " "Info: Total cell delay = 1.806 ns ( 63.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.037 ns ( 36.48 % ) " "Info: Total interconnect delay = 1.037 ns ( 36.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.843 ns" { clk clk~clkctrl butterfly:inst48|real_a[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.843 ns" { clk {} clk~combout {} clk~clkctrl {} butterfly:inst48|real_a[0] {} } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.214 ns" { clk clk~clkctrl butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.214 ns" { clk {} clk~combout {} clk~clkctrl {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15] {} } { 0.000ns 0.000ns 0.139ns 0.798ns } { 0.000ns 1.140ns 0.000ns 1.137ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.843 ns" { clk clk~clkctrl butterfly:inst48|real_a[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.843 ns" { clk {} clk~combout {} clk~clkctrl {} butterfly:inst48|real_a[0] {} } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 64 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.062 ns + " "Info: + Micro setup delay of destination is 0.062 ns" {  } { { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.501 ns" { butterfly:inst48|real_a[0] butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[0]~34 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[0]~113 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[1]~115 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[2]~117 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[3]~119 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[4]~121 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[5]~123 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[6]~125 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[7]~127 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[8]~129 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[9]~131 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[10]~133 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[11]~135 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[12]~137 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[13]~139 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[14]~141 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15]~142 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.501 ns" { butterfly:inst48|real_a[0] {} butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[0]~34 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[0]~113 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[1]~115 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[2]~117 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[3]~119 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[4]~121 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[5]~123 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[6]~125 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[7]~127 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[8]~129 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[9]~131 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[10]~133 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[11]~135 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[12]~137 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[13]~139 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[14]~141 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15]~142 {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15] {} } { 0.000ns 0.472ns 2.309ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.990ns } { 0.000ns 0.651ns 0.735ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 1.545ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.214 ns" { clk clk~clkctrl butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.214 ns" { clk {} clk~combout {} clk~clkctrl {} butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15] {} } { 0.000ns 0.000ns 0.139ns 0.798ns } { 0.000ns 1.140ns 0.000ns 1.137ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.843 ns" { clk clk~clkctrl butterfly:inst48|real_a[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.843 ns" { clk {} clk~combout {} clk~clkctrl {} butterfly:inst48|real_a[0] {} } { 0.000ns 0.000ns 0.139ns 0.898ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|jtag_debug_mode register sld_hub:sld_hub_inst\|hub_tdo_reg 97.33 MHz 10.274 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 97.33 MHz between source register \"sld_hub:sld_hub_inst\|jtag_debug_mode\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo_reg\" (period= 10.274 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.872 ns + Longest register register " "Info: + Longest register to register delay is 4.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode 1 REG LCFF_X9_Y9_N29 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X9_Y9_N29; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 394 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.624 ns) 1.074 ns sld_hub:sld_hub_inst\|node_ena~10 2 COMB LCCOMB_X9_Y9_N30 6 " "Info: 2: + IC(0.450 ns) + CELL(0.624 ns) = 1.074 ns; Loc. = LCCOMB_X9_Y9_N30; Fanout = 6; COMB Node = 'sld_hub:sld_hub_inst\|node_ena~10'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.074 ns" { sld_hub:sld_hub_inst|jtag_debug_mode sld_hub:sld_hub_inst|node_ena~10 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 136 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.613 ns) + CELL(0.206 ns) 1.893 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|crc_rom_sr_ena~31 3 COMB LCCOMB_X8_Y9_N2 4 " "Info: 3: + IC(0.613 ns) + CELL(0.206 ns) = 1.893 ns; Loc. = LCCOMB_X8_Y9_N2; Fanout = 4; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|crc_rom_sr_ena~31'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.819 ns" { sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 803 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.206 ns) 2.460 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|status_shift_enable~55 4 COMB LCCOMB_X8_Y9_N10 18 " "Info: 4: + IC(0.361 ns) + CELL(0.206 ns) = 2.460 ns; Loc. = LCCOMB_X8_Y9_N10; Fanout = 18; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|status_shift_enable~55'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.567 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~55 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 831 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.383 ns) + CELL(0.206 ns) 3.049 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~425 5 COMB LCCOMB_X8_Y9_N26 1 " "Info: 5: + IC(0.383 ns) + CELL(0.206 ns) = 3.049 ns; Loc. = LCCOMB_X8_Y9_N26; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~425'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.589 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~55 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 512 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.366 ns) + CELL(0.206 ns) 3.621 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~428 6 COMB LCCOMB_X8_Y9_N6 1 " "Info: 6: + IC(0.366 ns) + CELL(0.206 ns) = 3.621 ns; Loc. = LCCOMB_X8_Y9_N6; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~428'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.572 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 512 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.206 ns) 4.192 ns sld_hub:sld_hub_inst\|hub_tdo_reg~294 7 COMB LCCOMB_X8_Y9_N12 1 " "Info: 7: + IC(0.365 ns) + CELL(0.206 ns) = 4.192 ns; Loc. = LCCOMB_X8_Y9_N12; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~294'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.571 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|hub_tdo_reg~294 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.366 ns) + CELL(0.206 ns) 4.764 ns sld_hub:sld_hub_inst\|hub_tdo_reg~295 8 COMB LCCOMB_X8_Y9_N24 1 " "Info: 8: + IC(0.366 ns) + CELL(0.206 ns) = 4.764 ns; Loc. = LCCOMB_X8_Y9_N24; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~295'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.572 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg~295 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.872 ns sld_hub:sld_hub_inst\|hub_tdo_reg 9 REG LCFF_X8_Y9_N25 2 " "Info: 9: + IC(0.000 ns) + CELL(0.108 ns) = 4.872 ns; Loc. = LCFF_X8_Y9_N25; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.968 ns ( 40.39 % ) " "Info: Total cell delay = 1.968 ns ( 40.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.904 ns ( 59.61 % ) " "Info: Total interconnect delay = 2.904 ns ( 59.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.872 ns" { sld_hub:sld_hub_inst|jtag_debug_mode sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~55 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.872 ns" { sld_hub:sld_hub_inst|jtag_debug_mode {} sld_hub:sld_hub_inst|node_ena~10 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~55 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 {} sld_hub:sld_hub_inst|hub_tdo_reg~294 {} sld_hub:sld_hub_inst|hub_tdo_reg~295 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 0.450ns 0.613ns 0.361ns 0.383ns 0.366ns 0.365ns 0.366ns 0.000ns } { 0.000ns 0.624ns 0.206ns 0.206ns 0.206ns 0.206ns 0.206ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.001 ns - Smallest " "Info: - Smallest clock skew is -0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.378 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.378 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.835 ns) + CELL(0.000 ns) 3.835 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 753 " "Info: 2: + IC(3.835 ns) + CELL(0.000 ns) = 3.835 ns; Loc. = CLKCTRL_G0; Fanout = 753; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.835 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.877 ns) + CELL(0.666 ns) 5.378 ns sld_hub:sld_hub_inst\|hub_tdo_reg 3 REG LCFF_X8_Y9_N25 2 " "Info: 3: + IC(0.877 ns) + CELL(0.666 ns) = 5.378 ns; Loc. = LCFF_X8_Y9_N25; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.543 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 12.38 % ) " "Info: Total cell delay = 0.666 ns ( 12.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.712 ns ( 87.62 % ) " "Info: Total interconnect delay = 4.712 ns ( 87.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.378 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.378 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 3.835ns 0.877ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.379 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.835 ns) + CELL(0.000 ns) 3.835 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 753 " "Info: 2: + IC(3.835 ns) + CELL(0.000 ns) = 3.835 ns; Loc. = CLKCTRL_G0; Fanout = 753; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.835 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.878 ns) + CELL(0.666 ns) 5.379 ns sld_hub:sld_hub_inst\|jtag_debug_mode 3 REG LCFF_X9_Y9_N29 2 " "Info: 3: + IC(0.878 ns) + CELL(0.666 ns) = 5.379 ns; Loc. = LCFF_X9_Y9_N29; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.544 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 394 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 12.38 % ) " "Info: Total cell delay = 0.666 ns ( 12.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.713 ns ( 87.62 % ) " "Info: Total interconnect delay = 4.713 ns ( 87.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.379 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.379 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|jtag_debug_mode {} } { 0.000ns 3.835ns 0.878ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.378 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.378 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 3.835ns 0.877ns } { 0.000ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.379 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.379 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|jtag_debug_mode {} } { 0.000ns 3.835ns 0.878ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 394 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 394 -1 0 } } { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.872 ns" { sld_hub:sld_hub_inst|jtag_debug_mode sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~55 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.872 ns" { sld_hub:sld_hub_inst|jtag_debug_mode {} sld_hub:sld_hub_inst|node_ena~10 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~55 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~425 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~428 {} sld_hub:sld_hub_inst|hub_tdo_reg~294 {} sld_hub:sld_hub_inst|hub_tdo_reg~295 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 0.450ns 0.613ns 0.361ns 0.383ns 0.366ns 0.365ns 0.366ns 0.000ns } { 0.000ns 0.624ns 0.206ns 0.206ns 0.206ns 0.206ns 0.206ns 0.206ns 0.108ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.378 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.378 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 3.835ns 0.877ns } { 0.000ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.379 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.379 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|jtag_debug_mode {} } { 0.000ns 3.835ns 0.878ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[32\] aclr clk 5.849 ns register " "Info: tsu for register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[32\]\" (data pin = \"aclr\", clock pin = \"clk\") is 5.849 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.726 ns + Longest pin register " "Info: + Longest pin to register delay is 8.726 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.004 ns) 1.004 ns aclr 1 PIN PIN_206 20 " "Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_206; Fanout = 20; PIN Node = 'aclr'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { aclr } "NODE_NAME" } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 744 -72 96 760 "aclr" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.262 ns) + CELL(0.460 ns) 8.726 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[32\] 2 REG LCFF_X12_Y11_N9 3 " "Info: 2: + IC(7.262 ns) + CELL(0.460 ns) = 8.726 ns; Loc. = LCFF_X12_Y11_N9; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[32\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.722 ns" { aclr sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[32] } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 939 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.464 ns ( 16.78 % ) " "Info: Total cell delay = 1.464 ns ( 16.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.262 ns ( 83.22 % ) " "Info: Total interconnect delay = 7.262 ns ( 83.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.726 ns" { aclr sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[32] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.726 ns" { aclr {} aclr~combout {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[32] {} } { 0.000ns 0.000ns 7.262ns } { 0.000ns 1.004ns 0.460ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 939 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.837 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.837 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 328 80 248 344 "clk" "" } { 304 864 936 320 "clk" "" } { 256 1448 1488 272 "clk" "" } { 80 1752 1808 96 "clk" "" } { 88 1280 1352 104 "clk" "" } { -80 1272 1344 -64 "clk" "" } { 624 992 1040 640 "clk" "" } { 736 992 1040 752 "clk" "" } { 448 880 936 464 "clk" "" } { 320 248 368 336 "clk" "" } { 608 1472 1496 624 "clk" "" } { 720 1472 1504 736 "clk" "" } { 720 1224 1256 736 "clk" "" } { 608 1216 1248 624 "clk" "" } { 448 1784 1840 464 "clk" "" } { 224 1808 1848 240 "clk" "" } { 368 -184 -120 384 "clk" "" } { 656 -312 -232 672 "clk" "" } { 352 -408 -344 368 "clk" "" } { 720 0 96 736 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 2133 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 2133; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 328 80 248 344 "clk" "" } { 304 864 936 320 "clk" "" } { 256 1448 1488 272 "clk" "" } { 80 1752 1808 96 "clk" "" } { 88 1280 1352 104 "clk" "" } { -80 1272 1344 -64 "clk" "" } { 624 992 1040 640 "clk" "" } { 736 992 1040 752 "clk" "" } { 448 880 936 464 "clk" "" } { 320 248 368 336 "clk" "" } { 608 1472 1496 624 "clk" "" } { 720 1472 1504 736 "clk" "" } { 720 1224 1256 736 "clk" "" } { 608 1216 1248 624 "clk" "" } { 448 1784 1840 464 "clk" "" } { 224 1808 1848 240 "clk" "" } { 368 -184 -120 384 "clk" "" } { 656 -312 -232 672 "clk" "" } { 352 -408 -344 368 "clk" "" } { 720 0 96 736 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.892 ns) + CELL(0.666 ns) 2.837 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[32\] 3 REG LCFF_X12_Y11_N9 3 " "Info: 3: + IC(0.892 ns) + CELL(0.666 ns) = 2.837 ns; Loc. = LCFF_X12_Y11_N9; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[32\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.558 ns" { clk~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[32] } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 939 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.66 % ) " "Info: Total cell delay = 1.806 ns ( 63.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.031 ns ( 36.34 % ) " "Info: Total interconnect delay = 1.031 ns ( 36.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.837 ns" { clk clk~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[32] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.837 ns" { clk {} clk~combout {} clk~clkctrl {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[32] {} } { 0.000ns 0.000ns 0.139ns 0.892ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.726 ns" { aclr sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[32] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.726 ns" { aclr {} aclr~combout {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[32] {} } { 0.000ns 0.000ns 7.262ns } { 0.000ns 1.004ns 0.460ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.837 ns" { clk clk~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[32] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.837 ns" { clk {} clk~combout {} clk~clkctrl {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[32] {} } { 0.000ns 0.000ns 0.139ns 0.892ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Imagdata_out\[5\] T_control:inst46\|cnt\[3\] 15.628 ns register " "Info: tco from clock \"clk\" to destination pin \"Imagdata_out\[5\]\" through register \"T_control:inst46\|cnt\[3\]\" is 15.628 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.841 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.841 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 328 80 248 344 "clk" "" } { 304 864 936 320 "clk" "" } { 256 1448 1488 272 "clk" "" } { 80 1752 1808 96 "clk" "" } { 88 1280 1352 104 "clk" "" } { -80 1272 1344 -64 "clk" "" } { 624 992 1040 640 "clk" "" } { 736 992 1040 752 "clk" "" } { 448 880 936 464 "clk" "" } { 320 248 368 336 "clk" "" } { 608 1472 1496 624 "clk" "" } { 720 1472 1504 736 "clk" "" } { 720 1224 1256 736 "clk" "" } { 608 1216 1248 624 "clk" "" } { 448 1784 1840 464 "clk" "" } { 224 1808 1848 240 "clk" "" } { 368 -184 -120 384 "clk" "" } { 656 -312 -232 672 "clk" "" } { 352 -408 -344 368 "clk" "" } { 720 0 96 736 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 2133 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 2133; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 328 80 248 344 "clk" "" } { 304 864 936 320 "clk" "" } { 256 1448 1488 272 "clk" "" } { 80 1752 1808 96 "clk" "" } { 88 1280 1352 104 "clk" "" } { -80 1272 1344 -64 "clk" "" } { 624 992 1040 640 "clk" "" } { 736 992 1040 752 "clk" "" } { 448 880 936 464 "clk" "" } { 320 248 368 336 "clk" "" } { 608 1472 1496 624 "clk" "" } { 720 1472 1504 736 "clk" "" } { 720 1224 1256 736 "clk" "" } { 608 1216 1248 624 "clk" "" } { 448 1784 1840 464 "clk" "" } { 224 1808 1848 240 "clk" "" } { 368 -184 -120 384 "clk" "" } { 656 -312 -232 672 "clk" "" } { 352 -408 -344 368 "clk" "" } { 720 0 96 736 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.896 ns) + CELL(0.666 ns) 2.841 ns T_control:inst46\|cnt\[3\] 3 REG LCFF_X23_Y12_N27 17 " "Info: 3: + IC(0.896 ns) + CELL(0.666 ns) = 2.841 ns; Loc. = LCFF_X23_Y12_N27; Fanout = 17; REG Node = 'T_control:inst46\|cnt\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.562 ns" { clk~clkctrl T_control:inst46|cnt[3] } "NODE_NAME" } } { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 119 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.57 % ) " "Info: Total cell delay = 1.806 ns ( 63.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.035 ns ( 36.43 % ) " "Info: Total interconnect delay = 1.035 ns ( 36.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.841 ns" { clk clk~clkctrl T_control:inst46|cnt[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.841 ns" { clk {} clk~combout {} clk~clkctrl {} T_control:inst46|cnt[3] {} } { 0.000ns 0.000ns 0.139ns 0.896ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 119 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.483 ns + Longest register pin " "Info: + Longest register to pin delay is 12.483 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns T_control:inst46\|cnt\[3\] 1 REG LCFF_X23_Y12_N27 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X23_Y12_N27; Fanout = 17; REG Node = 'T_control:inst46\|cnt\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { T_control:inst46|cnt[3] } "NODE_NAME" } } { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 119 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.370 ns) 1.146 ns T_control:inst46\|source_sop~50 2 COMB LCCOMB_X22_Y12_N28 4 " "Info: 2: + IC(0.776 ns) + CELL(0.370 ns) = 1.146 ns; Loc. = LCCOMB_X22_Y12_N28; Fanout = 4; COMB Node = 'T_control:inst46\|source_sop~50'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.146 ns" { T_control:inst46|cnt[3] T_control:inst46|source_sop~50 } "NODE_NAME" } } { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.060 ns) + CELL(0.589 ns) 2.795 ns altera_auto_signaltap_0_source_valid18_signaltap_lcell 3 COMB LCCOMB_X18_Y12_N30 36 " "Info: 3: + IC(1.060 ns) + CELL(0.589 ns) = 2.795 ns; Loc. = LCCOMB_X18_Y12_N30; Fanout = 36; COMB Node = 'altera_auto_signaltap_0_source_valid18_signaltap_lcell'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.649 ns" { T_control:inst46|source_sop~50 altera_auto_signaltap_0_source_valid18_signaltap_lcell } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.528 ns) + CELL(0.650 ns) 4.973 ns altera_auto_signaltap_0_Imagdata_out\[5\]_signaltap_lcell 4 COMB LCCOMB_X13_Y12_N4 4 " "Info: 4: + IC(1.528 ns) + CELL(0.650 ns) = 4.973 ns; Loc. = LCCOMB_X13_Y12_N4; Fanout = 4; COMB Node = 'altera_auto_signaltap_0_Imagdata_out\[5\]_signaltap_lcell'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.178 ns" { altera_auto_signaltap_0_source_valid18_signaltap_lcell altera_auto_signaltap_0_Imagdata_out[5]_signaltap_lcell } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.240 ns) + CELL(3.270 ns) 12.483 ns Imagdata_out\[5\] 5 PIN PIN_48 0 " "Info: 5: + IC(4.240 ns) + CELL(3.270 ns) = 12.483 ns; Loc. = PIN_48; Fanout = 0; PIN Node = 'Imagdata_out\[5\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.510 ns" { altera_auto_signaltap_0_Imagdata_out[5]_signaltap_lcell Imagdata_out[5] } "NODE_NAME" } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 248 728 922 264 "Imagdata_out\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.879 ns ( 39.09 % ) " "Info: Total cell delay = 4.879 ns ( 39.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.604 ns ( 60.91 % ) " "Info: Total interconnect delay = 7.604 ns ( 60.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.483 ns" { T_control:inst46|cnt[3] T_control:inst46|source_sop~50 altera_auto_signaltap_0_source_valid18_signaltap_lcell altera_auto_signaltap_0_Imagdata_out[5]_signaltap_lcell Imagdata_out[5] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.483 ns" { T_control:inst46|cnt[3] {} T_control:inst46|source_sop~50 {} altera_auto_signaltap_0_source_valid18_signaltap_lcell {} altera_auto_signaltap_0_Imagdata_out[5]_signaltap_lcell {} Imagdata_out[5] {} } { 0.000ns 0.776ns 1.060ns 1.528ns 4.240ns } { 0.000ns 0.370ns 0.589ns 0.650ns 3.270ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.841 ns" { clk clk~clkctrl T_control:inst46|cnt[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.841 ns" { clk {} clk~combout {} clk~clkctrl {} T_control:inst46|cnt[3] {} } { 0.000ns 0.000ns 0.139ns 0.896ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.483 ns" { T_control:inst46|cnt[3] T_control:inst46|source_sop~50 altera_auto_signaltap_0_source_valid18_signaltap_lcell altera_auto_signaltap_0_Imagdata_out[5]_signaltap_lcell Imagdata_out[5] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.483 ns" { T_control:inst46|cnt[3] {} T_control:inst46|source_sop~50 {} altera_auto_signaltap_0_source_valid18_signaltap_lcell {} altera_auto_signaltap_0_Imagdata_out[5]_signaltap_lcell {} Imagdata_out[5] {} } { 0.000ns 0.776ns 1.060ns 1.528ns 4.240ns } { 0.000ns 0.370ns 0.589ns 0.650ns 3.270ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "aclr altera_auto_signaltap_0_aclr_ae 9.648 ns Longest " "Info: Longest tpd from source pin \"aclr\" to destination pin \"altera_auto_signaltap_0_aclr_ae\" is 9.648 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.004 ns) 1.004 ns aclr 1 PIN PIN_206 20 " "Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_206; Fanout = 20; PIN Node = 'aclr'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { aclr } "NODE_NAME" } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 744 -72 96 760 "aclr" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.205 ns) + CELL(0.319 ns) 8.528 ns altera_auto_signaltap_0_aclr_signaltap_lcell 2 COMB LCCOMB_X18_Y8_N18 1 " "Info: 2: + IC(7.205 ns) + CELL(0.319 ns) = 8.528 ns; Loc. = LCCOMB_X18_Y8_N18; Fanout = 1; COMB Node = 'altera_auto_signaltap_0_aclr_signaltap_lcell'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.524 ns" { aclr altera_auto_signaltap_0_aclr_signaltap_lcell } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.120 ns) + CELL(0.000 ns) 9.648 ns altera_auto_signaltap_0_aclr_ae 3 PIN LCCOMB_X18_Y4_N0 0 " "Info: 3: + IC(1.120 ns) + CELL(0.000 ns) = 9.648 ns; Loc. = LCCOMB_X18_Y4_N0; Fanout = 0; PIN Node = 'altera_auto_signaltap_0_aclr_ae'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.120 ns" { altera_auto_signaltap_0_aclr_signaltap_lcell altera_auto_signaltap_0_aclr_ae } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.323 ns ( 13.71 % ) " "Info: Total cell delay = 1.323 ns ( 13.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.325 ns ( 86.29 % ) " "Info: Total interconnect delay = 8.325 ns ( 86.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.648 ns" { aclr altera_auto_signaltap_0_aclr_signaltap_lcell altera_auto_signaltap_0_aclr_ae } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.648 ns" { aclr {} aclr~combout {} altera_auto_signaltap_0_aclr_signaltap_lcell {} altera_auto_signaltap_0_aclr_ae {} } { 0.000ns 0.000ns 7.205ns 1.120ns } { 0.000ns 1.004ns 0.319ns 0.000ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\] altera_internal_jtag~TDIUTAP altera_internal_jtag~TCKUTAP 3.575 ns register " "Info: th for register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\]\" (data pin = \"altera_internal_jtag~TDIUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 3.575 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.396 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.396 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.835 ns) + CELL(0.000 ns) 3.835 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 753 " "Info: 2: + IC(3.835 ns) + CELL(0.000 ns) = 3.835 ns; Loc. = CLKCTRL_G0; Fanout = 753; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.835 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.895 ns) + CELL(0.666 ns) 5.396 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\] 3 REG LCFF_X7_Y8_N19 1 " "Info: 3: + IC(0.895 ns) + CELL(0.666 ns) = 5.396 ns; Loc. = LCFF_X7_Y8_N19; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.561 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 12.34 % ) " "Info: Total cell delay = 0.666 ns ( 12.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.730 ns ( 87.66 % ) " "Info: Total interconnect delay = 4.730 ns ( 87.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.396 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.396 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[3] {} } { 0.000ns 3.835ns 0.895ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.127 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.127 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDIUTAP 1 PIN JTAG_X1_Y10_N0 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N0; Fanout = 11; PIN Node = 'altera_internal_jtag~TDIUTAP'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDIUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.813 ns) + CELL(0.206 ns) 2.019 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_rom_sr:crc_rom_sr\|WORD_SR~1039 2 COMB LCCOMB_X7_Y8_N18 1 " "Info: 2: + IC(1.813 ns) + CELL(0.206 ns) = 2.019 ns; Loc. = LCCOMB_X7_Y8_N18; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_rom_sr:crc_rom_sr\|WORD_SR~1039'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.019 ns" { altera_internal_jtag~TDIUTAP sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR~1039 } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.127 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\] 3 REG LCFF_X7_Y8_N19 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.127 ns; Loc. = LCFF_X7_Y8_N19; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR~1039 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 14.76 % ) " "Info: Total cell delay = 0.314 ns ( 14.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.813 ns ( 85.24 % ) " "Info: Total interconnect delay = 1.813 ns ( 85.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.127 ns" { altera_internal_jtag~TDIUTAP sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR~1039 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.127 ns" { altera_internal_jtag~TDIUTAP {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR~1039 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[3] {} } { 0.000ns 1.813ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.396 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.396 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[3] {} } { 0.000ns 3.835ns 0.895ns } { 0.000ns 0.000ns 0.666ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.127 ns" { altera_internal_jtag~TDIUTAP sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR~1039 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.127 ns" { altera_internal_jtag~TDIUTAP {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR~1039 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[3] {} } { 0.000ns 1.813ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "133 " "Info: Allocated 133 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 06 17:06:41 2010 " "Info: Processing ended: Sun Jun 06 17:06:41 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:25 " "Info: Elapsed time: 00:00:25" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 65 s " "Info: Quartus II Full Compilation was successful. 0 errors, 65 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
