library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
entity ctrl_fft is port( 
	reset_n : in std_logic; 
	clk : in std_logic; 
	sink_ready : in std_logic;
	sink_valid : out std_logic; 
	sink_sop : out std_logic; 
	sink_eop : out std_logic; 
	clk_en	 :out std_logic
	); 
end ctrl_fft; 
architecture one of ctrl_fft is 
constant frame : integer := 512; --fftµãÊý 
type state is (idle,go,assert_eop,wait_state); 
signal current_state,next_state : state; 
signal count,next_count : integer range 0 to frame - 1; 
signal sink_sop_d,sink_eop_d,sink_valid_d ,clk_en_d: std_logic; 
begin 
process(current_state,sink_ready,count) 
	begin 
	case current_state is 
		when idle => 
			next_count <= 0; 
			if (sink_ready = '1') then 
				next_state <= go; 
			else 
				next_state <= idle;     
			end if;   
		when go => 
			if (count < frame - 2) then 
				next_state <= go; 
				next_count <= count + 1; 
			else 
				next_state <= assert_eop; 
				next_count <= count + 1; 
			end if; 
		when assert_eop => 
				next_count <= 0; 
				next_state <= wait_state; 
		when wait_state => 
			if (sink_ready = '1') then 
				next_count <= 0; 
				next_state <= go; 
			else 
				next_count <= count ; 
				next_state <= wait_state; 
			end if;     
   end case; 
end process; 
sink_sop_d<='1' when ((next_state=go) and (next_count=0)) else '0'; 
sink_eop_d<='1' when (next_state=assert_eop) else '0'; 
sink_valid_d<='1' when ((next_state=go) or (next_state=assert_eop)) else '0';
clk_en_d<='1'  when  (next_state=go) else '0'; 
process(reset_n,clk) 
begin 
    if (reset_n = '0') then 
		current_state <= idle; 
		count <= 0; 
		sink_sop <= '0'; 
		sink_eop <= '0'; 
		sink_valid <= '0'; 
		clk_en <= '0'; 
	elsif rising_edge(clk) then 
		current_state <=next_state; 
		count <= next_count; 
		sink_sop <= sink_sop_d;--¼Ä´æÆ÷Êä³ö£¬±ÜÃâÃ«´Ì 
		sink_eop <= sink_eop_d; 
		sink_valid <= sink_valid_d; 
		clk_en <=clk_en_d;
   end if; 
end process; 
end one; 
