// megafunction wizard: %ALTMULT_COMPLEX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altmult_complex 

// ============================================================
// File Name: complex_mult.v
// Megafunction Name(s):
// 			altmult_complex
//
// Simulation Library Files(s):
// 			altera_mf;lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 151 09/26/2007 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


//altmult_complex CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" IMPLEMENTATION_STYLE="AUTO" PIPELINE=4 REPRESENTATION_A="SIGNED" REPRESENTATION_B="SIGNED" WIDTH_A=17 WIDTH_B=17 WIDTH_RESULT=34 clock dataa_imag dataa_real datab_imag datab_real result_imag result_real CARRY_CHAIN="MANUAL"
//VERSION_BEGIN 7.2 cbx_alt_ded_mult_y 2007:03:05:16:04:08:SJ cbx_altmult_add 2007:08:27:13:54:20:SJ cbx_altmult_complex 2007:07:27:03:10:06:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_mult 2007:07:20:16:47:26:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_padd 2007:07:12:14:48:24:SJ cbx_parallel_add 2007:01:30:03:53:08:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463


//synthesis_resources = altmult_add 3 lpm_add_sub 6 lpm_compare 1 reg 3 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  complex_mult_altmult_complex_q5p
	( 
	clock,
	dataa_imag,
	dataa_real,
	datab_imag,
	datab_real,
	result_imag,
	result_real) /* synthesis synthesis_clearbox=1 */;
	input   clock;
	input   [16:0]  dataa_imag;
	input   [16:0]  dataa_real;
	input   [16:0]  datab_imag;
	input   [16:0]  datab_real;
	output   [33:0]  result_imag;
	output   [33:0]  result_real;

	wire  [33:0]   wire_mult_add1_result;
	wire  [33:0]   wire_mult_add2_result;
	wire  [35:0]   wire_mult_add6_result;
	reg	[0:0]	dffe3a;
	reg	[0:0]	dffe4a;
	reg	[0:0]	dffe5a;
	wire  [34:0]   wire_add_sub7_result;
	wire  [17:0]   wire_adder1_result;
	wire  [34:0]   wire_adder2_result;
	wire  [17:0]   wire_subtractor1_result;
	wire  [34:0]   wire_subtractor2_result;
	wire  [35:0]   wire_subtractor3_result;
	wire  wire_comparator1_alb;
	wire aclr;
	wire  [17:0]  add1_res;
	wire ena;
	wire  [0:0]  gnd_value;
	wire  [35:0]  inputa_imag;
	wire  [35:0]  inputa_real;
	wire  [35:0]  inputb_imag;
	wire  [35:0]  inputb_real;
	wire  [33:0]  product1_res;
	wire  [33:0]  product2_res;
	wire  [34:0]  product3_res;
	wire  [17:0]  sub1_res;
	wire  [34:0]  sub2_res;

	altmult_add   mult_add1
	( 
	.aclr0(aclr),
	.chainout_sat_overflow(),
	.clock0(clock),
	.dataa(inputa_real[16:0]),
	.datab(inputb_imag[16:0]),
	.ena0(ena),
	.mult0_is_saturated(),
	.mult1_is_saturated(),
	.mult2_is_saturated(),
	.mult3_is_saturated(),
	.overflow(),
	.result(wire_mult_add1_result),
	.scanouta(),
	.scanoutb()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.accum_sload(1'b0),
	.aclr1(1'b0),
	.aclr2(1'b0),
	.aclr3(1'b0),
	.addnsub1(1'b1),
	.addnsub1_round(1'b0),
	.addnsub3(1'b1),
	.addnsub3_round(1'b0),
	.chainin({1{1'b0}}),
	.chainout_round(1'b0),
	.chainout_saturate(1'b0),
	.clock1(1'b1),
	.clock2(1'b1),
	.clock3(1'b1),
	.ena1(1'b1),
	.ena2(1'b1),
	.ena3(1'b1),
	.mult01_round(1'b0),
	.mult01_saturation(1'b0),
	.mult23_round(1'b0),
	.mult23_saturation(1'b0),
	.output_round(1'b0),
	.output_saturate(1'b0),
	.rotate(1'b0),
	.scanina({17{1'b0}}),
	.scaninb({17{1'b0}}),
	.shift_right(1'b0),
	.signa(1'b0),
	.signb(1'b0),
	.sourcea({1{1'b0}}),
	.sourceb({1{1'b0}}),
	.zero_chainout(1'b0),
	.zero_loopback(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	);
	defparam
		mult_add1.input_aclr_a0 = "ACLR0",
		mult_add1.input_aclr_b0 = "ACLR0",
		mult_add1.input_register_a0 = "CLOCK0",
		mult_add1.input_register_b0 = "CLOCK0",
		mult_add1.multiplier_register0 = "UNREGISTERED",
		mult_add1.number_of_multipliers = 1,
		mult_add1.output_aclr = "ACLR0",
		mult_add1.output_register = "CLOCK0",
		mult_add1.representation_a = "SIGNED",
		mult_add1.representation_b = "SIGNED",
		mult_add1.width_a = 17,
		mult_add1.width_b = 17,
		mult_add1.width_result = 34,
		mult_add1.lpm_type = "altmult_add";
	altmult_add   mult_add2
	( 
	.aclr0(aclr),
	.chainout_sat_overflow(),
	.clock0(clock),
	.dataa(inputa_imag[16:0]),
	.datab(inputb_real[16:0]),
	.ena0(ena),
	.mult0_is_saturated(),
	.mult1_is_saturated(),
	.mult2_is_saturated(),
	.mult3_is_saturated(),
	.overflow(),
	.result(wire_mult_add2_result),
	.scanouta(),
	.scanoutb()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.accum_sload(1'b0),
	.aclr1(1'b0),
	.aclr2(1'b0),
	.aclr3(1'b0),
	.addnsub1(1'b1),
	.addnsub1_round(1'b0),
	.addnsub3(1'b1),
	.addnsub3_round(1'b0),
	.chainin({1{1'b0}}),
	.chainout_round(1'b0),
	.chainout_saturate(1'b0),
	.clock1(1'b1),
	.clock2(1'b1),
	.clock3(1'b1),
	.ena1(1'b1),
	.ena2(1'b1),
	.ena3(1'b1),
	.mult01_round(1'b0),
	.mult01_saturation(1'b0),
	.mult23_round(1'b0),
	.mult23_saturation(1'b0),
	.output_round(1'b0),
	.output_saturate(1'b0),
	.rotate(1'b0),
	.scanina({17{1'b0}}),
	.scaninb({17{1'b0}}),
	.shift_right(1'b0),
	.signa(1'b0),
	.signb(1'b0),
	.sourcea({1{1'b0}}),
	.sourceb({1{1'b0}}),
	.zero_chainout(1'b0),
	.zero_loopback(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	);
	defparam
		mult_add2.input_aclr_a0 = "ACLR0",
		mult_add2.input_aclr_b0 = "ACLR0",
		mult_add2.input_register_a0 = "CLOCK0",
		mult_add2.input_register_b0 = "CLOCK0",
		mult_add2.multiplier_register0 = "UNREGISTERED",
		mult_add2.number_of_multipliers = 1,
		mult_add2.output_aclr = "ACLR0",
		mult_add2.output_register = "CLOCK0",
		mult_add2.representation_a = "SIGNED",
		mult_add2.representation_b = "SIGNED",
		mult_add2.width_a = 17,
		mult_add2.width_b = 17,
		mult_add2.width_result = 34,
		mult_add2.lpm_type = "altmult_add";
	altmult_add   mult_add6
	( 
	.aclr0(aclr),
	.chainout_sat_overflow(),
	.clock0(clock),
	.dataa(add1_res[17:0]),
	.datab(sub1_res),
	.ena0(ena),
	.mult0_is_saturated(),
	.mult1_is_saturated(),
	.mult2_is_saturated(),
	.mult3_is_saturated(),
	.overflow(),
	.result(wire_mult_add6_result),
	.scanouta(),
	.scanoutb()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.accum_sload(1'b0),
	.aclr1(1'b0),
	.aclr2(1'b0),
	.aclr3(1'b0),
	.addnsub1(1'b1),
	.addnsub1_round(1'b0),
	.addnsub3(1'b1),
	.addnsub3_round(1'b0),
	.chainin({1{1'b0}}),
	.chainout_round(1'b0),
	.chainout_saturate(1'b0),
	.clock1(1'b1),
	.clock2(1'b1),
	.clock3(1'b1),
	.ena1(1'b1),
	.ena2(1'b1),
	.ena3(1'b1),
	.mult01_round(1'b0),
	.mult01_saturation(1'b0),
	.mult23_round(1'b0),
	.mult23_saturation(1'b0),
	.output_round(1'b0),
	.output_saturate(1'b0),
	.rotate(1'b0),
	.scanina({18{1'b0}}),
	.scaninb({18{1'b0}}),
	.shift_right(1'b0),
	.signa(1'b0),
	.signb(1'b0),
	.sourcea({1{1'b0}}),
	.sourceb({1{1'b0}}),
	.zero_chainout(1'b0),
	.zero_loopback(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	);
	defparam
		mult_add6.input_register_a0 = "UNREGISTERED",
		mult_add6.input_register_b0 = "UNREGISTERED",
		mult_add6.multiplier_register0 = "UNREGISTERED",
		mult_add6.number_of_multipliers = 1,
		mult_add6.output_aclr = "ACLR0",
		mult_add6.output_register = "CLOCK0",
		mult_add6.representation_a = "SIGNED",
		mult_add6.representation_b = "SIGNED",
		mult_add6.width_a = 18,
		mult_add6.width_b = 18,
		mult_add6.width_result = 36,
		mult_add6.lpm_type = "altmult_add";
	// synopsys translate_off
	initial
		dffe3a = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) dffe3a <= 1'b0;
		else if  (ena == 1'b1)   dffe3a <= wire_comparator1_alb;
	// synopsys translate_off
	initial
		dffe4a = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) dffe4a <= 1'b0;
		else if  (ena == 1'b1)   dffe4a <= dffe3a;
	// synopsys translate_off
	initial
		dffe5a = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) dffe5a <= 1'b0;
		else if  (ena == 1'b1)   dffe5a <= dffe4a;
	lpm_add_sub   add_sub7
	( 
	.aclr(aclr),
	.clken(ena),
	.clock(clock),
	.cout(),
	.dataa({sub2_res[34:0]}),
	.datab({product3_res[34:0]}),
	.overflow(),
	.result(wire_add_sub7_result)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.add_sub(1'b1),
	.cin()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub7.lpm_direction = "ADD",
		add_sub7.lpm_pipeline = 1,
		add_sub7.lpm_width = 35,
		add_sub7.lpm_type = "lpm_add_sub",
		add_sub7.lpm_hint = "CARRY_CHAIN=MANUAL";
	lpm_add_sub   adder1
	( 
	.aclr(aclr),
	.clken(ena),
	.clock(clock),
	.cout(),
	.dataa({inputa_real[16], inputa_real[16:0]}),
	.datab({inputa_imag[16], inputa_imag[16:0]}),
	.overflow(),
	.result(wire_adder1_result)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.add_sub(1'b1),
	.cin()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	);
	defparam
		adder1.lpm_direction = "ADD",
		adder1.lpm_pipeline = 1,
		adder1.lpm_representation = "SIGNED",
		adder1.lpm_width = 18,
		adder1.lpm_type = "lpm_add_sub",
		adder1.lpm_hint = "CARRY_CHAIN=MANUAL";
	lpm_add_sub   adder2
	( 
	.aclr(aclr),
	.clken(ena),
	.clock(clock),
	.cout(),
	.dataa({product1_res[33], product1_res}),
	.datab({product2_res[33], product2_res}),
	.overflow(),
	.result(wire_adder2_result)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.add_sub(1'b1),
	.cin()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	);
	defparam
		adder2.lpm_direction = "ADD",
		adder2.lpm_pipeline = 2,
		adder2.lpm_representation = "SIGNED",
		adder2.lpm_width = 35,
		adder2.lpm_type = "lpm_add_sub",
		adder2.lpm_hint = "CARRY_CHAIN=MANUAL";
	lpm_add_sub   subtractor1
	( 
	.aclr(aclr),
	.clken(ena),
	.clock(clock),
	.cout(),
	.dataa({inputb_real[16], inputb_real[16:0]}),
	.datab({inputb_imag[16], inputb_imag[16:0]}),
	.overflow(),
	.result(wire_subtractor1_result)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.add_sub(1'b1),
	.cin()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	);
	defparam
		subtractor1.lpm_direction = "SUB",
		subtractor1.lpm_pipeline = 1,
		subtractor1.lpm_representation = "SIGNED",
		subtractor1.lpm_width = 18,
		subtractor1.lpm_type = "lpm_add_sub",
		subtractor1.lpm_hint = "CARRY_CHAIN=MANUAL";
	lpm_add_sub   subtractor2
	( 
	.aclr(aclr),
	.clken(ena),
	.clock(clock),
	.cout(),
	.dataa({product1_res[33], product1_res}),
	.datab({product2_res[33], product2_res}),
	.overflow(),
	.result(wire_subtractor2_result)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.add_sub(1'b1),
	.cin()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	);
	defparam
		subtractor2.lpm_direction = "SUB",
		subtractor2.lpm_pipeline = 1,
		subtractor2.lpm_representation = "SIGNED",
		subtractor2.lpm_width = 35,
		subtractor2.lpm_type = "lpm_add_sub",
		subtractor2.lpm_hint = "CARRY_CHAIN=MANUAL";
	lpm_add_sub   subtractor3
	( 
	.aclr(aclr),
	.clken(ena),
	.clock(clock),
	.cout(),
	.dataa({36{gnd_value}}),
	.datab({wire_mult_add6_result[35:0]}),
	.overflow(),
	.result(wire_subtractor3_result)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.add_sub(1'b1),
	.cin()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	);
	defparam
		subtractor3.lpm_direction = "ADD",
		subtractor3.lpm_pipeline = 1,
		subtractor3.lpm_representation = "UNSIGNED",
		subtractor3.lpm_width = 36,
		subtractor3.lpm_type = "lpm_add_sub",
		subtractor3.lpm_hint = "CARRY_CHAIN=MANUAL";
	lpm_compare   comparator1
	( 
	.aeb(),
	.agb(),
	.ageb(),
	.alb(wire_comparator1_alb),
	.aleb(),
	.aneb(),
	.dataa(datab_real),
	.datab(datab_imag)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.clken(1'b1),
	.clock(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	);
	defparam
		comparator1.lpm_representation = "SIGNED",
		comparator1.lpm_width = 17,
		comparator1.lpm_type = "lpm_compare";
	assign
		aclr = 1'b0,
		add1_res = wire_adder1_result,
		ena = 1'b1,
		gnd_value = 1'b0,
		inputa_imag = {{19{inputa_imag[16]}}, dataa_imag[16:0]},
		inputa_real = {{19{inputa_real[16]}}, dataa_real[16:0]},
		inputb_imag = {{19{inputb_imag[16]}}, datab_imag[16:0]},
		inputb_real = {{19{inputb_real[16]}}, datab_real[16:0]},
		product1_res = wire_mult_add1_result,
		product2_res = wire_mult_add2_result,
		product3_res = {wire_subtractor3_result[34:0]},
		result_imag = wire_adder2_result[33:0],
		result_real = wire_add_sub7_result[33:0],
		sub1_res = wire_subtractor1_result,
		sub2_res = wire_subtractor2_result;
endmodule //complex_mult_altmult_complex_q5p
//VALID FILE


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module complex_mult (
	clock,
	dataa_imag,
	dataa_real,
	datab_imag,
	datab_real,
	result_imag,
	result_real)/* synthesis synthesis_clearbox = 1 */;

	input	  clock;
	input	[16:0]  dataa_imag;
	input	[16:0]  dataa_real;
	input	[16:0]  datab_imag;
	input	[16:0]  datab_real;
	output	[33:0]  result_imag;
	output	[33:0]  result_real;

	wire [33:0] sub_wire0;
	wire [33:0] sub_wire1;
	wire [33:0] result_real = sub_wire0[33:0];
	wire [33:0] result_imag = sub_wire1[33:0];

	complex_mult_altmult_complex_q5p	complex_mult_altmult_complex_q5p_component (
				.datab_imag (datab_imag),
				.clock (clock),
				.dataa_imag (dataa_imag),
				.datab_real (datab_real),
				.dataa_real (dataa_real),
				.result_real (sub_wire0),
				.result_imag (sub_wire1));

endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: IMPLEMENTATION_STYLE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "4"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "SIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "17"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "17"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "34"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa_imag 0 0 17 0 INPUT NODEFVAL "dataa_imag[16..0]"
// Retrieval info: USED_PORT: dataa_real 0 0 17 0 INPUT NODEFVAL "dataa_real[16..0]"
// Retrieval info: USED_PORT: datab_imag 0 0 17 0 INPUT NODEFVAL "datab_imag[16..0]"
// Retrieval info: USED_PORT: datab_real 0 0 17 0 INPUT NODEFVAL "datab_real[16..0]"
// Retrieval info: USED_PORT: result_imag 0 0 34 0 OUTPUT NODEFVAL "result_imag[33..0]"
// Retrieval info: USED_PORT: result_real 0 0 34 0 OUTPUT NODEFVAL "result_real[33..0]"
// Retrieval info: CONNECT: @datab_real 0 0 17 0 datab_real 0 0 17 0
// Retrieval info: CONNECT: result_imag 0 0 34 0 @result_imag 0 0 34 0
// Retrieval info: CONNECT: result_real 0 0 34 0 @result_real 0 0 34 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa_imag 0 0 17 0 dataa_imag 0 0 17 0
// Retrieval info: CONNECT: @datab_imag 0 0 17 0 datab_imag 0 0 17 0
// Retrieval info: CONNECT: @dataa_real 0 0 17 0 dataa_real 0 0 17 0
// Retrieval info: GEN_FILE: TYPE_NORMAL complex_mult.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL complex_mult.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL complex_mult.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL complex_mult.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL complex_mult_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL complex_mult_bb.v TRUE FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: LIB_FILE: lpm

