|block
source_eop <= T_control:inst46.source_eop
clk => T_control:inst46.clk
clk => reset_ctrl:inst5.clk
clk => ctrl_fft:inst3.clk
clk => p2s:inst28.clk
clk => butterfly:inst48.clk
clk => s2p:inst6.clk
clk => s2p:inst7.clk
clk => D:inst16.clk
clk => D:inst15.clk
clk => lpm_rom1:inst2.clock
clk => D:inst14.clk
clk => D:inst11.clk
clk => lpm_rom0:inst1.clock
clk => lpm_fifo0:inst24.clock
clk => lpm_fifo0:inst.clock
clk => p2s:inst13.clk
clk => lpm_rom2:inst19.clock
clk => lpm_counter0:inst4.clock
clk => block_new:inst45.clk
aclr => lpm_rom2:inst19.aclr
source_sop <= T_control:inst46.source_sop
source_valid18 <= T_control:inst46.source_valid
Imagdata_out[0] <= T_control:inst46.Imagdata_out[0]
Imagdata_out[1] <= T_control:inst46.Imagdata_out[1]
Imagdata_out[2] <= T_control:inst46.Imagdata_out[2]
Imagdata_out[3] <= T_control:inst46.Imagdata_out[3]
Imagdata_out[4] <= T_control:inst46.Imagdata_out[4]
Imagdata_out[5] <= T_control:inst46.Imagdata_out[5]
Imagdata_out[6] <= T_control:inst46.Imagdata_out[6]
Imagdata_out[7] <= T_control:inst46.Imagdata_out[7]
Imagdata_out[8] <= T_control:inst46.Imagdata_out[8]
Imagdata_out[9] <= T_control:inst46.Imagdata_out[9]
Imagdata_out[10] <= T_control:inst46.Imagdata_out[10]
Imagdata_out[11] <= T_control:inst46.Imagdata_out[11]
Imagdata_out[12] <= T_control:inst46.Imagdata_out[12]
Imagdata_out[13] <= T_control:inst46.Imagdata_out[13]
Imagdata_out[14] <= T_control:inst46.Imagdata_out[14]
Imagdata_out[15] <= T_control:inst46.Imagdata_out[15]
Realdata_out[0] <= T_control:inst46.Realdata_out[0]
Realdata_out[1] <= T_control:inst46.Realdata_out[1]
Realdata_out[2] <= T_control:inst46.Realdata_out[2]
Realdata_out[3] <= T_control:inst46.Realdata_out[3]
Realdata_out[4] <= T_control:inst46.Realdata_out[4]
Realdata_out[5] <= T_control:inst46.Realdata_out[5]
Realdata_out[6] <= T_control:inst46.Realdata_out[6]
Realdata_out[7] <= T_control:inst46.Realdata_out[7]
Realdata_out[8] <= T_control:inst46.Realdata_out[8]
Realdata_out[9] <= T_control:inst46.Realdata_out[9]
Realdata_out[10] <= T_control:inst46.Realdata_out[10]
Realdata_out[11] <= T_control:inst46.Realdata_out[11]
Realdata_out[12] <= T_control:inst46.Realdata_out[12]
Realdata_out[13] <= T_control:inst46.Realdata_out[13]
Realdata_out[14] <= T_control:inst46.Realdata_out[14]
Realdata_out[15] <= T_control:inst46.Realdata_out[15]
sin[0] <= lpm_rom2:inst19.q[0]
sin[1] <= lpm_rom2:inst19.q[1]
sin[2] <= lpm_rom2:inst19.q[2]
sin[3] <= lpm_rom2:inst19.q[3]
sin[4] <= lpm_rom2:inst19.q[4]
sin[5] <= lpm_rom2:inst19.q[5]
sin[6] <= lpm_rom2:inst19.q[6]
sin[7] <= lpm_rom2:inst19.q[7]
sin[8] <= lpm_rom2:inst19.q[8]
sin[9] <= lpm_rom2:inst19.q[9]
sin[10] <= lpm_rom2:inst19.q[10]
sin[11] <= lpm_rom2:inst19.q[11]
sin[12] <= lpm_rom2:inst19.q[12]
sin[13] <= lpm_rom2:inst19.q[13]
sin[14] <= lpm_rom2:inst19.q[14]
sin[15] <= lpm_rom2:inst19.q[15]
state[0] <= block_new:inst45.state[0]
state[1] <= block_new:inst45.state[1]


|block|T_control:inst46
clk => clk~0.IN2
reset => cnt[0]~reg0.ACLR
reset => cnt[1]~reg0.ACLR
reset => cnt[2]~reg0.ACLR
reset => cnt[3]~reg0.ACLR
reset => cnt[4]~reg0.ACLR
reset => cnt[5]~reg0.ACLR
reset => cnt[6]~reg0.ACLR
reset => level[0].ACLR
reset => level[1].ACLR
reset => level[2].ACLR
reset => rdreq_fifo~0.OUTPUTSELECT
reset => source_valid_Tcontrol~0.OUTPUTSELECT
reset => sink_ready~1.OUTPUTSELECT
reset => idata_out~16.OUTPUTSELECT
reset => idata_out~17.OUTPUTSELECT
reset => idata_out~18.OUTPUTSELECT
reset => idata_out~19.OUTPUTSELECT
reset => idata_out~20.OUTPUTSELECT
reset => idata_out~21.OUTPUTSELECT
reset => idata_out~22.OUTPUTSELECT
reset => idata_out~23.OUTPUTSELECT
reset => idata_out~24.OUTPUTSELECT
reset => idata_out~25.OUTPUTSELECT
reset => idata_out~26.OUTPUTSELECT
reset => idata_out~27.OUTPUTSELECT
reset => idata_out~28.OUTPUTSELECT
reset => idata_out~29.OUTPUTSELECT
reset => idata_out~30.OUTPUTSELECT
reset => idata_out~31.OUTPUTSELECT
reset => rdata_out~32.OUTPUTSELECT
reset => rdata_out~31.OUTPUTSELECT
reset => rdata_out~30.OUTPUTSELECT
reset => rdata_out~29.OUTPUTSELECT
reset => rdata_out~28.OUTPUTSELECT
reset => rdata_out~27.OUTPUTSELECT
reset => rdata_out~26.OUTPUTSELECT
reset => rdata_out~25.OUTPUTSELECT
reset => rdata_out~24.OUTPUTSELECT
reset => rdata_out~23.OUTPUTSELECT
reset => rdata_out~22.OUTPUTSELECT
reset => rdata_out~21.OUTPUTSELECT
reset => rdata_out~20.OUTPUTSELECT
reset => rdata_out~19.OUTPUTSELECT
reset => rdata_out~18.OUTPUTSELECT
reset => rdata_out~17.OUTPUTSELECT
reset => current_state~1.IN1
sink_valid => always0~1.IN0
sink_valid => always0~0.IN0
sink_sop => always0~0.IN1
sink_eop => always0~1.IN1
fifo_full => Selector5.IN3
fifo_full => Selector3.IN2
Realdata_in[0] => Rdata_in~36.DATAB
Realdata_in[1] => Rdata_in~35.DATAB
Realdata_in[2] => Rdata_in~34.DATAB
Realdata_in[3] => Rdata_in~33.DATAB
Realdata_in[4] => Rdata_in~32.DATAB
Realdata_in[5] => Rdata_in~31.DATAB
Realdata_in[6] => Rdata_in~30.DATAB
Realdata_in[7] => Rdata_in~29.DATAB
Realdata_in[8] => Rdata_in~28.DATAB
Realdata_in[9] => Rdata_in~27.DATAB
Realdata_in[10] => Rdata_in~26.DATAB
Realdata_in[11] => Rdata_in~25.DATAB
Realdata_in[12] => Rdata_in~24.DATAB
Realdata_in[13] => Rdata_in~23.DATAB
Realdata_in[14] => Rdata_in~22.DATAB
Realdata_in[15] => Rdata_in~21.DATAB
Realdata_in[16] => Rdata_in~20.DATAB
Realdata_in[17] => Rdata_in~19.DATAB
Imagdata_in[0] => Idata_in~36.DATAB
Imagdata_in[1] => Idata_in~35.DATAB
Imagdata_in[2] => Idata_in~34.DATAB
Imagdata_in[3] => Idata_in~33.DATAB
Imagdata_in[4] => Idata_in~32.DATAB
Imagdata_in[5] => Idata_in~31.DATAB
Imagdata_in[6] => Idata_in~30.DATAB
Imagdata_in[7] => Idata_in~29.DATAB
Imagdata_in[8] => Idata_in~28.DATAB
Imagdata_in[9] => Idata_in~27.DATAB
Imagdata_in[10] => Idata_in~26.DATAB
Imagdata_in[11] => Idata_in~25.DATAB
Imagdata_in[12] => Idata_in~24.DATAB
Imagdata_in[13] => Idata_in~23.DATAB
Imagdata_in[14] => Idata_in~22.DATAB
Imagdata_in[15] => Idata_in~21.DATAB
Imagdata_in[16] => Idata_in~20.DATAB
Imagdata_in[17] => Idata_in~19.DATAB
Rfifodata_in[0] => Rdata_in~18.DATAB
Rfifodata_in[1] => Rdata_in~17.DATAB
Rfifodata_in[2] => Rdata_in~16.DATAB
Rfifodata_in[3] => Rdata_in~15.DATAB
Rfifodata_in[4] => Rdata_in~14.DATAB
Rfifodata_in[5] => Rdata_in~13.DATAB
Rfifodata_in[6] => Rdata_in~12.DATAB
Rfifodata_in[7] => Rdata_in~11.DATAB
Rfifodata_in[8] => Rdata_in~10.DATAB
Rfifodata_in[9] => Rdata_in~9.DATAB
Rfifodata_in[10] => Rdata_in~8.DATAB
Rfifodata_in[11] => Rdata_in~7.DATAB
Rfifodata_in[12] => Rdata_in~6.DATAB
Rfifodata_in[13] => Rdata_in~5.DATAB
Rfifodata_in[14] => Rdata_in~4.DATAB
Rfifodata_in[15] => Rdata_in~3.DATAB
Rfifodata_in[16] => Rdata_in~2.DATAB
Rfifodata_in[17] => Rdata_in~1.DATAB
Ififodata_in[0] => Idata_in~18.DATAB
Ififodata_in[1] => Idata_in~17.DATAB
Ififodata_in[2] => Idata_in~16.DATAB
Ififodata_in[3] => Idata_in~15.DATAB
Ififodata_in[4] => Idata_in~14.DATAB
Ififodata_in[5] => Idata_in~13.DATAB
Ififodata_in[6] => Idata_in~12.DATAB
Ififodata_in[7] => Idata_in~11.DATAB
Ififodata_in[8] => Idata_in~10.DATAB
Ififodata_in[9] => Idata_in~9.DATAB
Ififodata_in[10] => Idata_in~8.DATAB
Ififodata_in[11] => Idata_in~7.DATAB
Ififodata_in[12] => Idata_in~6.DATAB
Ififodata_in[13] => Idata_in~5.DATAB
Ififodata_in[14] => Idata_in~4.DATAB
Ififodata_in[15] => Idata_in~3.DATAB
Ififodata_in[16] => Idata_in~2.DATAB
Ififodata_in[17] => Idata_in~1.DATAB
state[0] => Equal2.IN1
state[0] => Equal3.IN0
state[0] => Equal4.IN1
state[1] => Equal2.IN0
state[1] => Equal3.IN1
state[1] => Equal4.IN0
ADD[0] <= ADD[0]~5.DB_MAX_OUTPUT_PORT_TYPE
ADD[1] <= ADD[1]~4.DB_MAX_OUTPUT_PORT_TYPE
ADD[2] <= ADD[2]~3.DB_MAX_OUTPUT_PORT_TYPE
ADD[3] <= ADD[3]~2.DB_MAX_OUTPUT_PORT_TYPE
ADD[4] <= ADD[4]~1.DB_MAX_OUTPUT_PORT_TYPE
ADD[5] <= ADD[5]~0.DB_MAX_OUTPUT_PORT_TYPE
ADD_WN[0] <= ADD_WN~5.DB_MAX_OUTPUT_PORT_TYPE
ADD_WN[1] <= ADD_WN~4.DB_MAX_OUTPUT_PORT_TYPE
ADD_WN[2] <= ADD_WN~3.DB_MAX_OUTPUT_PORT_TYPE
ADD_WN[3] <= ADD_WN~2.DB_MAX_OUTPUT_PORT_TYPE
ADD_WN[4] <= ADD_WN~1.DB_MAX_OUTPUT_PORT_TYPE
Realdata_out[0] <= Realdata_out~64.DB_MAX_OUTPUT_PORT_TYPE
Realdata_out[1] <= Realdata_out~63.DB_MAX_OUTPUT_PORT_TYPE
Realdata_out[2] <= Realdata_out~62.DB_MAX_OUTPUT_PORT_TYPE
Realdata_out[3] <= Realdata_out~61.DB_MAX_OUTPUT_PORT_TYPE
Realdata_out[4] <= Realdata_out~60.DB_MAX_OUTPUT_PORT_TYPE
Realdata_out[5] <= Realdata_out~59.DB_MAX_OUTPUT_PORT_TYPE
Realdata_out[6] <= Realdata_out~58.DB_MAX_OUTPUT_PORT_TYPE
Realdata_out[7] <= Realdata_out~57.DB_MAX_OUTPUT_PORT_TYPE
Realdata_out[8] <= Realdata_out~56.DB_MAX_OUTPUT_PORT_TYPE
Realdata_out[9] <= Realdata_out~55.DB_MAX_OUTPUT_PORT_TYPE
Realdata_out[10] <= Realdata_out~54.DB_MAX_OUTPUT_PORT_TYPE
Realdata_out[11] <= Realdata_out~53.DB_MAX_OUTPUT_PORT_TYPE
Realdata_out[12] <= Realdata_out~52.DB_MAX_OUTPUT_PORT_TYPE
Realdata_out[13] <= Realdata_out~51.DB_MAX_OUTPUT_PORT_TYPE
Realdata_out[14] <= Realdata_out~50.DB_MAX_OUTPUT_PORT_TYPE
Realdata_out[15] <= Realdata_out~49.DB_MAX_OUTPUT_PORT_TYPE
Imagdata_out[0] <= Imagdata_out~63.DB_MAX_OUTPUT_PORT_TYPE
Imagdata_out[1] <= Imagdata_out~62.DB_MAX_OUTPUT_PORT_TYPE
Imagdata_out[2] <= Imagdata_out~61.DB_MAX_OUTPUT_PORT_TYPE
Imagdata_out[3] <= Imagdata_out~60.DB_MAX_OUTPUT_PORT_TYPE
Imagdata_out[4] <= Imagdata_out~59.DB_MAX_OUTPUT_PORT_TYPE
Imagdata_out[5] <= Imagdata_out~58.DB_MAX_OUTPUT_PORT_TYPE
Imagdata_out[6] <= Imagdata_out~57.DB_MAX_OUTPUT_PORT_TYPE
Imagdata_out[7] <= Imagdata_out~56.DB_MAX_OUTPUT_PORT_TYPE
Imagdata_out[8] <= Imagdata_out~55.DB_MAX_OUTPUT_PORT_TYPE
Imagdata_out[9] <= Imagdata_out~54.DB_MAX_OUTPUT_PORT_TYPE
Imagdata_out[10] <= Imagdata_out~53.DB_MAX_OUTPUT_PORT_TYPE
Imagdata_out[11] <= Imagdata_out~52.DB_MAX_OUTPUT_PORT_TYPE
Imagdata_out[12] <= Imagdata_out~51.DB_MAX_OUTPUT_PORT_TYPE
Imagdata_out[13] <= Imagdata_out~50.DB_MAX_OUTPUT_PORT_TYPE
Imagdata_out[14] <= Imagdata_out~49.DB_MAX_OUTPUT_PORT_TYPE
Imagdata_out[15] <= Imagdata_out~48.DB_MAX_OUTPUT_PORT_TYPE
rdata_out[0] <= rdata_out~32.DB_MAX_OUTPUT_PORT_TYPE
rdata_out[1] <= rdata_out~31.DB_MAX_OUTPUT_PORT_TYPE
rdata_out[2] <= rdata_out~30.DB_MAX_OUTPUT_PORT_TYPE
rdata_out[3] <= rdata_out~29.DB_MAX_OUTPUT_PORT_TYPE
rdata_out[4] <= rdata_out~28.DB_MAX_OUTPUT_PORT_TYPE
rdata_out[5] <= rdata_out~27.DB_MAX_OUTPUT_PORT_TYPE
rdata_out[6] <= rdata_out~26.DB_MAX_OUTPUT_PORT_TYPE
rdata_out[7] <= rdata_out~25.DB_MAX_OUTPUT_PORT_TYPE
rdata_out[8] <= rdata_out~24.DB_MAX_OUTPUT_PORT_TYPE
rdata_out[9] <= rdata_out~23.DB_MAX_OUTPUT_PORT_TYPE
rdata_out[10] <= rdata_out~22.DB_MAX_OUTPUT_PORT_TYPE
rdata_out[11] <= rdata_out~21.DB_MAX_OUTPUT_PORT_TYPE
rdata_out[12] <= rdata_out~20.DB_MAX_OUTPUT_PORT_TYPE
rdata_out[13] <= rdata_out~19.DB_MAX_OUTPUT_PORT_TYPE
rdata_out[14] <= rdata_out~18.DB_MAX_OUTPUT_PORT_TYPE
rdata_out[15] <= rdata_out~17.DB_MAX_OUTPUT_PORT_TYPE
idata_out[0] <= idata_out~31.DB_MAX_OUTPUT_PORT_TYPE
idata_out[1] <= idata_out~30.DB_MAX_OUTPUT_PORT_TYPE
idata_out[2] <= idata_out~29.DB_MAX_OUTPUT_PORT_TYPE
idata_out[3] <= idata_out~28.DB_MAX_OUTPUT_PORT_TYPE
idata_out[4] <= idata_out~27.DB_MAX_OUTPUT_PORT_TYPE
idata_out[5] <= idata_out~26.DB_MAX_OUTPUT_PORT_TYPE
idata_out[6] <= idata_out~25.DB_MAX_OUTPUT_PORT_TYPE
idata_out[7] <= idata_out~24.DB_MAX_OUTPUT_PORT_TYPE
idata_out[8] <= idata_out~23.DB_MAX_OUTPUT_PORT_TYPE
idata_out[9] <= idata_out~22.DB_MAX_OUTPUT_PORT_TYPE
idata_out[10] <= idata_out~21.DB_MAX_OUTPUT_PORT_TYPE
idata_out[11] <= idata_out~20.DB_MAX_OUTPUT_PORT_TYPE
idata_out[12] <= idata_out~19.DB_MAX_OUTPUT_PORT_TYPE
idata_out[13] <= idata_out~18.DB_MAX_OUTPUT_PORT_TYPE
idata_out[14] <= idata_out~17.DB_MAX_OUTPUT_PORT_TYPE
idata_out[15] <= idata_out~16.DB_MAX_OUTPUT_PORT_TYPE
source_valid <= Realdata_out~0.DB_MAX_OUTPUT_PORT_TYPE
source_eop <= source_eop~0.DB_MAX_OUTPUT_PORT_TYPE
source_sop <= source_sop~0.DB_MAX_OUTPUT_PORT_TYPE
sink_ready <= sink_ready~1.DB_MAX_OUTPUT_PORT_TYPE
source_valid_Tcontrol <= source_valid_Tcontrol~0.DB_MAX_OUTPUT_PORT_TYPE
rdreq_fifo <= rdreq_fifo~0.DB_MAX_OUTPUT_PORT_TYPE
aclr_rom <= aclr_rom~0.DB_MAX_OUTPUT_PORT_TYPE
cnt[0] <= cnt[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[1] <= cnt[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[2] <= cnt[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[3] <= cnt[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[4] <= cnt[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[5] <= cnt[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[6] <= cnt[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|block|T_control:inst46|lpm_ram_dq0:ram1
address[0] => address[0]~5.IN1
address[1] => address[1]~4.IN1
address[2] => address[2]~3.IN1
address[3] => address[3]~2.IN1
address[4] => address[4]~1.IN1
address[5] => address[5]~0.IN1
clock => clock~0.IN1
data[0] => data[0]~17.IN1
data[1] => data[1]~16.IN1
data[2] => data[2]~15.IN1
data[3] => data[3]~14.IN1
data[4] => data[4]~13.IN1
data[5] => data[5]~12.IN1
data[6] => data[6]~11.IN1
data[7] => data[7]~10.IN1
data[8] => data[8]~9.IN1
data[9] => data[9]~8.IN1
data[10] => data[10]~7.IN1
data[11] => data[11]~6.IN1
data[12] => data[12]~5.IN1
data[13] => data[13]~4.IN1
data[14] => data[14]~3.IN1
data[15] => data[15]~2.IN1
data[16] => data[16]~1.IN1
data[17] => data[17]~0.IN1
wren => wren~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
q[8] <= altsyncram:altsyncram_component.q_a
q[9] <= altsyncram:altsyncram_component.q_a
q[10] <= altsyncram:altsyncram_component.q_a
q[11] <= altsyncram:altsyncram_component.q_a
q[12] <= altsyncram:altsyncram_component.q_a
q[13] <= altsyncram:altsyncram_component.q_a
q[14] <= altsyncram:altsyncram_component.q_a
q[15] <= altsyncram:altsyncram_component.q_a
q[16] <= altsyncram:altsyncram_component.q_a
q[17] <= altsyncram:altsyncram_component.q_a


|block|T_control:inst46|lpm_ram_dq0:ram1|altsyncram:altsyncram_component
wren_a => altsyncram_n4a1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_n4a1:auto_generated.data_a[0]
data_a[1] => altsyncram_n4a1:auto_generated.data_a[1]
data_a[2] => altsyncram_n4a1:auto_generated.data_a[2]
data_a[3] => altsyncram_n4a1:auto_generated.data_a[3]
data_a[4] => altsyncram_n4a1:auto_generated.data_a[4]
data_a[5] => altsyncram_n4a1:auto_generated.data_a[5]
data_a[6] => altsyncram_n4a1:auto_generated.data_a[6]
data_a[7] => altsyncram_n4a1:auto_generated.data_a[7]
data_a[8] => altsyncram_n4a1:auto_generated.data_a[8]
data_a[9] => altsyncram_n4a1:auto_generated.data_a[9]
data_a[10] => altsyncram_n4a1:auto_generated.data_a[10]
data_a[11] => altsyncram_n4a1:auto_generated.data_a[11]
data_a[12] => altsyncram_n4a1:auto_generated.data_a[12]
data_a[13] => altsyncram_n4a1:auto_generated.data_a[13]
data_a[14] => altsyncram_n4a1:auto_generated.data_a[14]
data_a[15] => altsyncram_n4a1:auto_generated.data_a[15]
data_a[16] => altsyncram_n4a1:auto_generated.data_a[16]
data_a[17] => altsyncram_n4a1:auto_generated.data_a[17]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_n4a1:auto_generated.address_a[0]
address_a[1] => altsyncram_n4a1:auto_generated.address_a[1]
address_a[2] => altsyncram_n4a1:auto_generated.address_a[2]
address_a[3] => altsyncram_n4a1:auto_generated.address_a[3]
address_a[4] => altsyncram_n4a1:auto_generated.address_a[4]
address_a[5] => altsyncram_n4a1:auto_generated.address_a[5]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_n4a1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_n4a1:auto_generated.q_a[0]
q_a[1] <= altsyncram_n4a1:auto_generated.q_a[1]
q_a[2] <= altsyncram_n4a1:auto_generated.q_a[2]
q_a[3] <= altsyncram_n4a1:auto_generated.q_a[3]
q_a[4] <= altsyncram_n4a1:auto_generated.q_a[4]
q_a[5] <= altsyncram_n4a1:auto_generated.q_a[5]
q_a[6] <= altsyncram_n4a1:auto_generated.q_a[6]
q_a[7] <= altsyncram_n4a1:auto_generated.q_a[7]
q_a[8] <= altsyncram_n4a1:auto_generated.q_a[8]
q_a[9] <= altsyncram_n4a1:auto_generated.q_a[9]
q_a[10] <= altsyncram_n4a1:auto_generated.q_a[10]
q_a[11] <= altsyncram_n4a1:auto_generated.q_a[11]
q_a[12] <= altsyncram_n4a1:auto_generated.q_a[12]
q_a[13] <= altsyncram_n4a1:auto_generated.q_a[13]
q_a[14] <= altsyncram_n4a1:auto_generated.q_a[14]
q_a[15] <= altsyncram_n4a1:auto_generated.q_a[15]
q_a[16] <= altsyncram_n4a1:auto_generated.q_a[16]
q_a[17] <= altsyncram_n4a1:auto_generated.q_a[17]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|block|T_control:inst46|lpm_ram_dq0:ram1|altsyncram:altsyncram_component|altsyncram_n4a1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[5] => ram_block1a16.PORTAADDR5
address_a[5] => ram_block1a17.PORTAADDR5
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
data_a[16] => ram_block1a16.PORTADATAIN
data_a[17] => ram_block1a17.PORTADATAIN
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT
q_a[10] <= ram_block1a10.PORTADATAOUT
q_a[11] <= ram_block1a11.PORTADATAOUT
q_a[12] <= ram_block1a12.PORTADATAOUT
q_a[13] <= ram_block1a13.PORTADATAOUT
q_a[14] <= ram_block1a14.PORTADATAOUT
q_a[15] <= ram_block1a15.PORTADATAOUT
q_a[16] <= ram_block1a16.PORTADATAOUT
q_a[17] <= ram_block1a17.PORTADATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a8.PORTAWE
wren_a => ram_block1a9.PORTAWE
wren_a => ram_block1a10.PORTAWE
wren_a => ram_block1a11.PORTAWE
wren_a => ram_block1a12.PORTAWE
wren_a => ram_block1a13.PORTAWE
wren_a => ram_block1a14.PORTAWE
wren_a => ram_block1a15.PORTAWE
wren_a => ram_block1a16.PORTAWE
wren_a => ram_block1a17.PORTAWE


|block|T_control:inst46|lpm_ram_dq0:ram2
address[0] => address[0]~5.IN1
address[1] => address[1]~4.IN1
address[2] => address[2]~3.IN1
address[3] => address[3]~2.IN1
address[4] => address[4]~1.IN1
address[5] => address[5]~0.IN1
clock => clock~0.IN1
data[0] => data[0]~17.IN1
data[1] => data[1]~16.IN1
data[2] => data[2]~15.IN1
data[3] => data[3]~14.IN1
data[4] => data[4]~13.IN1
data[5] => data[5]~12.IN1
data[6] => data[6]~11.IN1
data[7] => data[7]~10.IN1
data[8] => data[8]~9.IN1
data[9] => data[9]~8.IN1
data[10] => data[10]~7.IN1
data[11] => data[11]~6.IN1
data[12] => data[12]~5.IN1
data[13] => data[13]~4.IN1
data[14] => data[14]~3.IN1
data[15] => data[15]~2.IN1
data[16] => data[16]~1.IN1
data[17] => data[17]~0.IN1
wren => wren~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
q[8] <= altsyncram:altsyncram_component.q_a
q[9] <= altsyncram:altsyncram_component.q_a
q[10] <= altsyncram:altsyncram_component.q_a
q[11] <= altsyncram:altsyncram_component.q_a
q[12] <= altsyncram:altsyncram_component.q_a
q[13] <= altsyncram:altsyncram_component.q_a
q[14] <= altsyncram:altsyncram_component.q_a
q[15] <= altsyncram:altsyncram_component.q_a
q[16] <= altsyncram:altsyncram_component.q_a
q[17] <= altsyncram:altsyncram_component.q_a


|block|T_control:inst46|lpm_ram_dq0:ram2|altsyncram:altsyncram_component
wren_a => altsyncram_n4a1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_n4a1:auto_generated.data_a[0]
data_a[1] => altsyncram_n4a1:auto_generated.data_a[1]
data_a[2] => altsyncram_n4a1:auto_generated.data_a[2]
data_a[3] => altsyncram_n4a1:auto_generated.data_a[3]
data_a[4] => altsyncram_n4a1:auto_generated.data_a[4]
data_a[5] => altsyncram_n4a1:auto_generated.data_a[5]
data_a[6] => altsyncram_n4a1:auto_generated.data_a[6]
data_a[7] => altsyncram_n4a1:auto_generated.data_a[7]
data_a[8] => altsyncram_n4a1:auto_generated.data_a[8]
data_a[9] => altsyncram_n4a1:auto_generated.data_a[9]
data_a[10] => altsyncram_n4a1:auto_generated.data_a[10]
data_a[11] => altsyncram_n4a1:auto_generated.data_a[11]
data_a[12] => altsyncram_n4a1:auto_generated.data_a[12]
data_a[13] => altsyncram_n4a1:auto_generated.data_a[13]
data_a[14] => altsyncram_n4a1:auto_generated.data_a[14]
data_a[15] => altsyncram_n4a1:auto_generated.data_a[15]
data_a[16] => altsyncram_n4a1:auto_generated.data_a[16]
data_a[17] => altsyncram_n4a1:auto_generated.data_a[17]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_n4a1:auto_generated.address_a[0]
address_a[1] => altsyncram_n4a1:auto_generated.address_a[1]
address_a[2] => altsyncram_n4a1:auto_generated.address_a[2]
address_a[3] => altsyncram_n4a1:auto_generated.address_a[3]
address_a[4] => altsyncram_n4a1:auto_generated.address_a[4]
address_a[5] => altsyncram_n4a1:auto_generated.address_a[5]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_n4a1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_n4a1:auto_generated.q_a[0]
q_a[1] <= altsyncram_n4a1:auto_generated.q_a[1]
q_a[2] <= altsyncram_n4a1:auto_generated.q_a[2]
q_a[3] <= altsyncram_n4a1:auto_generated.q_a[3]
q_a[4] <= altsyncram_n4a1:auto_generated.q_a[4]
q_a[5] <= altsyncram_n4a1:auto_generated.q_a[5]
q_a[6] <= altsyncram_n4a1:auto_generated.q_a[6]
q_a[7] <= altsyncram_n4a1:auto_generated.q_a[7]
q_a[8] <= altsyncram_n4a1:auto_generated.q_a[8]
q_a[9] <= altsyncram_n4a1:auto_generated.q_a[9]
q_a[10] <= altsyncram_n4a1:auto_generated.q_a[10]
q_a[11] <= altsyncram_n4a1:auto_generated.q_a[11]
q_a[12] <= altsyncram_n4a1:auto_generated.q_a[12]
q_a[13] <= altsyncram_n4a1:auto_generated.q_a[13]
q_a[14] <= altsyncram_n4a1:auto_generated.q_a[14]
q_a[15] <= altsyncram_n4a1:auto_generated.q_a[15]
q_a[16] <= altsyncram_n4a1:auto_generated.q_a[16]
q_a[17] <= altsyncram_n4a1:auto_generated.q_a[17]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|block|T_control:inst46|lpm_ram_dq0:ram2|altsyncram:altsyncram_component|altsyncram_n4a1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[5] => ram_block1a16.PORTAADDR5
address_a[5] => ram_block1a17.PORTAADDR5
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
data_a[16] => ram_block1a16.PORTADATAIN
data_a[17] => ram_block1a17.PORTADATAIN
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT
q_a[10] <= ram_block1a10.PORTADATAOUT
q_a[11] <= ram_block1a11.PORTADATAOUT
q_a[12] <= ram_block1a12.PORTADATAOUT
q_a[13] <= ram_block1a13.PORTADATAOUT
q_a[14] <= ram_block1a14.PORTADATAOUT
q_a[15] <= ram_block1a15.PORTADATAOUT
q_a[16] <= ram_block1a16.PORTADATAOUT
q_a[17] <= ram_block1a17.PORTADATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a8.PORTAWE
wren_a => ram_block1a9.PORTAWE
wren_a => ram_block1a10.PORTAWE
wren_a => ram_block1a11.PORTAWE
wren_a => ram_block1a12.PORTAWE
wren_a => ram_block1a13.PORTAWE
wren_a => ram_block1a14.PORTAWE
wren_a => ram_block1a15.PORTAWE
wren_a => ram_block1a16.PORTAWE
wren_a => ram_block1a17.PORTAWE


|block|reset_ctrl:inst5
clk => num[6].CLK
clk => num[5].CLK
clk => num[4].CLK
clk => num[3].CLK
clk => num[2].CLK
clk => num[1].CLK
clk => num[0].CLK
clk => clk_c~reg0.CLK
clk_c <= clk_c~reg0.DB_MAX_OUTPUT_PORT_TYPE


|block|ctrl_fft:inst3
reset_n => count[8].ACLR
reset_n => count[7].ACLR
reset_n => count[6].ACLR
reset_n => count[5].ACLR
reset_n => count[4].ACLR
reset_n => count[3].ACLR
reset_n => count[2].ACLR
reset_n => count[1].ACLR
reset_n => count[0].ACLR
reset_n => sink_sop~reg0.ACLR
reset_n => sink_eop~reg0.ACLR
reset_n => sink_valid~reg0.ACLR
reset_n => clk_en~reg0.ACLR
reset_n => current_state~1.IN1
clk => count[8].CLK
clk => count[7].CLK
clk => count[6].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => sink_sop~reg0.CLK
clk => sink_eop~reg0.CLK
clk => sink_valid~reg0.CLK
clk => clk_en~reg0.CLK
clk => current_state~0.IN1
sink_ready => Selector9.IN2
sink_ready => Selector9.IN3
sink_ready => next_count~8.OUTPUTSELECT
sink_ready => next_count~7.OUTPUTSELECT
sink_ready => next_count~6.OUTPUTSELECT
sink_ready => next_count~5.OUTPUTSELECT
sink_ready => next_count~4.OUTPUTSELECT
sink_ready => next_count~3.OUTPUTSELECT
sink_ready => next_count~2.OUTPUTSELECT
sink_ready => next_count~1.OUTPUTSELECT
sink_ready => next_count~0.OUTPUTSELECT
sink_ready => Selector10.IN2
sink_ready => next_state.idle.DATAB
sink_valid <= sink_valid~reg0.DB_MAX_OUTPUT_PORT_TYPE
sink_sop <= sink_sop~reg0.DB_MAX_OUTPUT_PORT_TYPE
sink_eop <= sink_eop~reg0.DB_MAX_OUTPUT_PORT_TYPE
clk_en <= clk_en~reg0.DB_MAX_OUTPUT_PORT_TYPE


|block|lpm_fifo0:inst24
aclr => aclr~0.IN1
clock => clock~0.IN1
data[0] => data[0]~17.IN1
data[1] => data[1]~16.IN1
data[2] => data[2]~15.IN1
data[3] => data[3]~14.IN1
data[4] => data[4]~13.IN1
data[5] => data[5]~12.IN1
data[6] => data[6]~11.IN1
data[7] => data[7]~10.IN1
data[8] => data[8]~9.IN1
data[9] => data[9]~8.IN1
data[10] => data[10]~7.IN1
data[11] => data[11]~6.IN1
data[12] => data[12]~5.IN1
data[13] => data[13]~4.IN1
data[14] => data[14]~3.IN1
data[15] => data[15]~2.IN1
data[16] => data[16]~1.IN1
data[17] => data[17]~0.IN1
rdreq => rdreq~0.IN1
wrreq => wrreq~0.IN1
empty <= scfifo:scfifo_component.empty
full <= scfifo:scfifo_component.full
q[0] <= scfifo:scfifo_component.q
q[1] <= scfifo:scfifo_component.q
q[2] <= scfifo:scfifo_component.q
q[3] <= scfifo:scfifo_component.q
q[4] <= scfifo:scfifo_component.q
q[5] <= scfifo:scfifo_component.q
q[6] <= scfifo:scfifo_component.q
q[7] <= scfifo:scfifo_component.q
q[8] <= scfifo:scfifo_component.q
q[9] <= scfifo:scfifo_component.q
q[10] <= scfifo:scfifo_component.q
q[11] <= scfifo:scfifo_component.q
q[12] <= scfifo:scfifo_component.q
q[13] <= scfifo:scfifo_component.q
q[14] <= scfifo:scfifo_component.q
q[15] <= scfifo:scfifo_component.q
q[16] <= scfifo:scfifo_component.q
q[17] <= scfifo:scfifo_component.q
usedw[0] <= scfifo:scfifo_component.usedw
usedw[1] <= scfifo:scfifo_component.usedw
usedw[2] <= scfifo:scfifo_component.usedw
usedw[3] <= scfifo:scfifo_component.usedw
usedw[4] <= scfifo:scfifo_component.usedw
usedw[5] <= scfifo:scfifo_component.usedw


|block|lpm_fifo0:inst24|scfifo:scfifo_component
data[0] => scfifo_7r31:auto_generated.data[0]
data[1] => scfifo_7r31:auto_generated.data[1]
data[2] => scfifo_7r31:auto_generated.data[2]
data[3] => scfifo_7r31:auto_generated.data[3]
data[4] => scfifo_7r31:auto_generated.data[4]
data[5] => scfifo_7r31:auto_generated.data[5]
data[6] => scfifo_7r31:auto_generated.data[6]
data[7] => scfifo_7r31:auto_generated.data[7]
data[8] => scfifo_7r31:auto_generated.data[8]
data[9] => scfifo_7r31:auto_generated.data[9]
data[10] => scfifo_7r31:auto_generated.data[10]
data[11] => scfifo_7r31:auto_generated.data[11]
data[12] => scfifo_7r31:auto_generated.data[12]
data[13] => scfifo_7r31:auto_generated.data[13]
data[14] => scfifo_7r31:auto_generated.data[14]
data[15] => scfifo_7r31:auto_generated.data[15]
data[16] => scfifo_7r31:auto_generated.data[16]
data[17] => scfifo_7r31:auto_generated.data[17]
q[0] <= scfifo_7r31:auto_generated.q[0]
q[1] <= scfifo_7r31:auto_generated.q[1]
q[2] <= scfifo_7r31:auto_generated.q[2]
q[3] <= scfifo_7r31:auto_generated.q[3]
q[4] <= scfifo_7r31:auto_generated.q[4]
q[5] <= scfifo_7r31:auto_generated.q[5]
q[6] <= scfifo_7r31:auto_generated.q[6]
q[7] <= scfifo_7r31:auto_generated.q[7]
q[8] <= scfifo_7r31:auto_generated.q[8]
q[9] <= scfifo_7r31:auto_generated.q[9]
q[10] <= scfifo_7r31:auto_generated.q[10]
q[11] <= scfifo_7r31:auto_generated.q[11]
q[12] <= scfifo_7r31:auto_generated.q[12]
q[13] <= scfifo_7r31:auto_generated.q[13]
q[14] <= scfifo_7r31:auto_generated.q[14]
q[15] <= scfifo_7r31:auto_generated.q[15]
q[16] <= scfifo_7r31:auto_generated.q[16]
q[17] <= scfifo_7r31:auto_generated.q[17]
wrreq => scfifo_7r31:auto_generated.wrreq
rdreq => scfifo_7r31:auto_generated.rdreq
clock => scfifo_7r31:auto_generated.clock
aclr => scfifo_7r31:auto_generated.aclr
sclr => ~NO_FANOUT~
empty <= scfifo_7r31:auto_generated.empty
full <= scfifo_7r31:auto_generated.full
almost_full <= <GND>
almost_empty <= <GND>
usedw[0] <= scfifo_7r31:auto_generated.usedw[0]
usedw[1] <= scfifo_7r31:auto_generated.usedw[1]
usedw[2] <= scfifo_7r31:auto_generated.usedw[2]
usedw[3] <= scfifo_7r31:auto_generated.usedw[3]
usedw[4] <= scfifo_7r31:auto_generated.usedw[4]
usedw[5] <= scfifo_7r31:auto_generated.usedw[5]


|block|lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated
aclr => a_dpfifo_e141:dpfifo.aclr
clock => a_dpfifo_e141:dpfifo.clock
data[0] => a_dpfifo_e141:dpfifo.data[0]
data[1] => a_dpfifo_e141:dpfifo.data[1]
data[2] => a_dpfifo_e141:dpfifo.data[2]
data[3] => a_dpfifo_e141:dpfifo.data[3]
data[4] => a_dpfifo_e141:dpfifo.data[4]
data[5] => a_dpfifo_e141:dpfifo.data[5]
data[6] => a_dpfifo_e141:dpfifo.data[6]
data[7] => a_dpfifo_e141:dpfifo.data[7]
data[8] => a_dpfifo_e141:dpfifo.data[8]
data[9] => a_dpfifo_e141:dpfifo.data[9]
data[10] => a_dpfifo_e141:dpfifo.data[10]
data[11] => a_dpfifo_e141:dpfifo.data[11]
data[12] => a_dpfifo_e141:dpfifo.data[12]
data[13] => a_dpfifo_e141:dpfifo.data[13]
data[14] => a_dpfifo_e141:dpfifo.data[14]
data[15] => a_dpfifo_e141:dpfifo.data[15]
data[16] => a_dpfifo_e141:dpfifo.data[16]
data[17] => a_dpfifo_e141:dpfifo.data[17]
empty <= a_dpfifo_e141:dpfifo.empty
full <= a_dpfifo_e141:dpfifo.full
q[0] <= a_dpfifo_e141:dpfifo.q[0]
q[1] <= a_dpfifo_e141:dpfifo.q[1]
q[2] <= a_dpfifo_e141:dpfifo.q[2]
q[3] <= a_dpfifo_e141:dpfifo.q[3]
q[4] <= a_dpfifo_e141:dpfifo.q[4]
q[5] <= a_dpfifo_e141:dpfifo.q[5]
q[6] <= a_dpfifo_e141:dpfifo.q[6]
q[7] <= a_dpfifo_e141:dpfifo.q[7]
q[8] <= a_dpfifo_e141:dpfifo.q[8]
q[9] <= a_dpfifo_e141:dpfifo.q[9]
q[10] <= a_dpfifo_e141:dpfifo.q[10]
q[11] <= a_dpfifo_e141:dpfifo.q[11]
q[12] <= a_dpfifo_e141:dpfifo.q[12]
q[13] <= a_dpfifo_e141:dpfifo.q[13]
q[14] <= a_dpfifo_e141:dpfifo.q[14]
q[15] <= a_dpfifo_e141:dpfifo.q[15]
q[16] <= a_dpfifo_e141:dpfifo.q[16]
q[17] <= a_dpfifo_e141:dpfifo.q[17]
rdreq => a_dpfifo_e141:dpfifo.rreq
usedw[0] <= a_dpfifo_e141:dpfifo.usedw[0]
usedw[1] <= a_dpfifo_e141:dpfifo.usedw[1]
usedw[2] <= a_dpfifo_e141:dpfifo.usedw[2]
usedw[3] <= a_dpfifo_e141:dpfifo.usedw[3]
usedw[4] <= a_dpfifo_e141:dpfifo.usedw[4]
usedw[5] <= a_dpfifo_e141:dpfifo.usedw[5]
wrreq => a_dpfifo_e141:dpfifo.wreq


|block|lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo
aclr => a_fefifo_b6f:fifo_state.aclr
aclr => cntr_fjb:rd_ptr_count.aclr
aclr => cntr_fjb:wr_ptr.aclr
clock => a_fefifo_b6f:fifo_state.clock
clock => dpram_fv01:FIFOram.inclock
clock => dpram_fv01:FIFOram.outclock
clock => cntr_fjb:rd_ptr_count.clock
clock => cntr_fjb:wr_ptr.clock
data[0] => dpram_fv01:FIFOram.data[0]
data[1] => dpram_fv01:FIFOram.data[1]
data[2] => dpram_fv01:FIFOram.data[2]
data[3] => dpram_fv01:FIFOram.data[3]
data[4] => dpram_fv01:FIFOram.data[4]
data[5] => dpram_fv01:FIFOram.data[5]
data[6] => dpram_fv01:FIFOram.data[6]
data[7] => dpram_fv01:FIFOram.data[7]
data[8] => dpram_fv01:FIFOram.data[8]
data[9] => dpram_fv01:FIFOram.data[9]
data[10] => dpram_fv01:FIFOram.data[10]
data[11] => dpram_fv01:FIFOram.data[11]
data[12] => dpram_fv01:FIFOram.data[12]
data[13] => dpram_fv01:FIFOram.data[13]
data[14] => dpram_fv01:FIFOram.data[14]
data[15] => dpram_fv01:FIFOram.data[15]
data[16] => dpram_fv01:FIFOram.data[16]
data[17] => dpram_fv01:FIFOram.data[17]
empty <= a_fefifo_b6f:fifo_state.empty
full <= a_fefifo_b6f:fifo_state.full
q[0] <= dpram_fv01:FIFOram.q[0]
q[1] <= dpram_fv01:FIFOram.q[1]
q[2] <= dpram_fv01:FIFOram.q[2]
q[3] <= dpram_fv01:FIFOram.q[3]
q[4] <= dpram_fv01:FIFOram.q[4]
q[5] <= dpram_fv01:FIFOram.q[5]
q[6] <= dpram_fv01:FIFOram.q[6]
q[7] <= dpram_fv01:FIFOram.q[7]
q[8] <= dpram_fv01:FIFOram.q[8]
q[9] <= dpram_fv01:FIFOram.q[9]
q[10] <= dpram_fv01:FIFOram.q[10]
q[11] <= dpram_fv01:FIFOram.q[11]
q[12] <= dpram_fv01:FIFOram.q[12]
q[13] <= dpram_fv01:FIFOram.q[13]
q[14] <= dpram_fv01:FIFOram.q[14]
q[15] <= dpram_fv01:FIFOram.q[15]
q[16] <= dpram_fv01:FIFOram.q[16]
q[17] <= dpram_fv01:FIFOram.q[17]
rreq => a_fefifo_b6f:fifo_state.rreq
rreq => valid_rreq.IN0
sclr => a_fefifo_b6f:fifo_state.sclr
sclr => cntr_fjb:rd_ptr_count.sclr
sclr => cntr_fjb:wr_ptr.sclr
usedw[0] <= a_fefifo_b6f:fifo_state.usedw_out[0]
usedw[1] <= a_fefifo_b6f:fifo_state.usedw_out[1]
usedw[2] <= a_fefifo_b6f:fifo_state.usedw_out[2]
usedw[3] <= a_fefifo_b6f:fifo_state.usedw_out[3]
usedw[4] <= a_fefifo_b6f:fifo_state.usedw_out[4]
usedw[5] <= a_fefifo_b6f:fifo_state.usedw_out[5]
wreq => a_fefifo_b6f:fifo_state.wreq
wreq => valid_wreq.IN0


|block|lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|a_fefifo_b6f:fifo_state
aclr => cntr_tk7:count_usedw.aclr
clock => cntr_tk7:count_usedw.clock
clock => b_full.CLK
clock => b_non_empty.CLK
full <= b_full.DB_MAX_OUTPUT_PORT_TYPE
rreq => valid_rreq.IN0
sclr => cntr_tk7:count_usedw.sclr
usedw_out[0] <= usedw[0].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[1] <= usedw[1].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[2] <= usedw[2].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[3] <= usedw[3].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[4] <= usedw[4].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[5] <= usedw[5].DB_MAX_OUTPUT_PORT_TYPE
wreq => valid_wreq.IN0


|block|lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|a_fefifo_b6f:fifo_state|cntr_tk7:count_usedw
aclr => counter_reg_bit1a[5].ACLR
aclr => counter_reg_bit1a[4].ACLR
aclr => counter_reg_bit1a[3].ACLR
aclr => counter_reg_bit1a[2].ACLR
aclr => counter_reg_bit1a[1].ACLR
aclr => counter_reg_bit1a[0].ACLR
clock => counter_reg_bit1a[5].CLK
clock => counter_reg_bit1a[4].CLK
clock => counter_reg_bit1a[3].CLK
clock => counter_reg_bit1a[2].CLK
clock => counter_reg_bit1a[1].CLK
clock => counter_reg_bit1a[0].CLK
q[0] <= counter_reg_bit1a[0].REGOUT
q[1] <= counter_reg_bit1a[1].REGOUT
q[2] <= counter_reg_bit1a[2].REGOUT
q[3] <= counter_reg_bit1a[3].REGOUT
q[4] <= counter_reg_bit1a[4].REGOUT
q[5] <= counter_reg_bit1a[5].REGOUT
updown => counter_comb_bita0.DATAB
updown => counter_comb_bita1.DATAB
updown => counter_comb_bita2.DATAB
updown => counter_comb_bita3.DATAB
updown => counter_comb_bita4.DATAB
updown => counter_comb_bita5.DATAB


|block|lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|dpram_fv01:FIFOram
data[0] => altsyncram_avj1:altsyncram1.data_a[0]
data[1] => altsyncram_avj1:altsyncram1.data_a[1]
data[2] => altsyncram_avj1:altsyncram1.data_a[2]
data[3] => altsyncram_avj1:altsyncram1.data_a[3]
data[4] => altsyncram_avj1:altsyncram1.data_a[4]
data[5] => altsyncram_avj1:altsyncram1.data_a[5]
data[6] => altsyncram_avj1:altsyncram1.data_a[6]
data[7] => altsyncram_avj1:altsyncram1.data_a[7]
data[8] => altsyncram_avj1:altsyncram1.data_a[8]
data[9] => altsyncram_avj1:altsyncram1.data_a[9]
data[10] => altsyncram_avj1:altsyncram1.data_a[10]
data[11] => altsyncram_avj1:altsyncram1.data_a[11]
data[12] => altsyncram_avj1:altsyncram1.data_a[12]
data[13] => altsyncram_avj1:altsyncram1.data_a[13]
data[14] => altsyncram_avj1:altsyncram1.data_a[14]
data[15] => altsyncram_avj1:altsyncram1.data_a[15]
data[16] => altsyncram_avj1:altsyncram1.data_a[16]
data[17] => altsyncram_avj1:altsyncram1.data_a[17]
inclock => altsyncram_avj1:altsyncram1.clock0
outclock => altsyncram_avj1:altsyncram1.clock1
outclocken => altsyncram_avj1:altsyncram1.clocken1
q[0] <= altsyncram_avj1:altsyncram1.q_b[0]
q[1] <= altsyncram_avj1:altsyncram1.q_b[1]
q[2] <= altsyncram_avj1:altsyncram1.q_b[2]
q[3] <= altsyncram_avj1:altsyncram1.q_b[3]
q[4] <= altsyncram_avj1:altsyncram1.q_b[4]
q[5] <= altsyncram_avj1:altsyncram1.q_b[5]
q[6] <= altsyncram_avj1:altsyncram1.q_b[6]
q[7] <= altsyncram_avj1:altsyncram1.q_b[7]
q[8] <= altsyncram_avj1:altsyncram1.q_b[8]
q[9] <= altsyncram_avj1:altsyncram1.q_b[9]
q[10] <= altsyncram_avj1:altsyncram1.q_b[10]
q[11] <= altsyncram_avj1:altsyncram1.q_b[11]
q[12] <= altsyncram_avj1:altsyncram1.q_b[12]
q[13] <= altsyncram_avj1:altsyncram1.q_b[13]
q[14] <= altsyncram_avj1:altsyncram1.q_b[14]
q[15] <= altsyncram_avj1:altsyncram1.q_b[15]
q[16] <= altsyncram_avj1:altsyncram1.q_b[16]
q[17] <= altsyncram_avj1:altsyncram1.q_b[17]
rdaddress[0] => altsyncram_avj1:altsyncram1.address_b[0]
rdaddress[1] => altsyncram_avj1:altsyncram1.address_b[1]
rdaddress[2] => altsyncram_avj1:altsyncram1.address_b[2]
rdaddress[3] => altsyncram_avj1:altsyncram1.address_b[3]
rdaddress[4] => altsyncram_avj1:altsyncram1.address_b[4]
rdaddress[5] => altsyncram_avj1:altsyncram1.address_b[5]
wraddress[0] => altsyncram_avj1:altsyncram1.address_a[0]
wraddress[1] => altsyncram_avj1:altsyncram1.address_a[1]
wraddress[2] => altsyncram_avj1:altsyncram1.address_a[2]
wraddress[3] => altsyncram_avj1:altsyncram1.address_a[3]
wraddress[4] => altsyncram_avj1:altsyncram1.address_a[4]
wraddress[5] => altsyncram_avj1:altsyncram1.address_a[5]
wren => altsyncram_avj1:altsyncram1.wren_a


|block|lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|dpram_fv01:FIFOram|altsyncram_avj1:altsyncram1
address_a[0] => ram_block2a0.PORTAADDR
address_a[0] => ram_block2a1.PORTAADDR
address_a[0] => ram_block2a2.PORTAADDR
address_a[0] => ram_block2a3.PORTAADDR
address_a[0] => ram_block2a4.PORTAADDR
address_a[0] => ram_block2a5.PORTAADDR
address_a[0] => ram_block2a6.PORTAADDR
address_a[0] => ram_block2a7.PORTAADDR
address_a[0] => ram_block2a8.PORTAADDR
address_a[0] => ram_block2a9.PORTAADDR
address_a[0] => ram_block2a10.PORTAADDR
address_a[0] => ram_block2a11.PORTAADDR
address_a[0] => ram_block2a12.PORTAADDR
address_a[0] => ram_block2a13.PORTAADDR
address_a[0] => ram_block2a14.PORTAADDR
address_a[0] => ram_block2a15.PORTAADDR
address_a[0] => ram_block2a16.PORTAADDR
address_a[0] => ram_block2a17.PORTAADDR
address_a[1] => ram_block2a0.PORTAADDR1
address_a[1] => ram_block2a1.PORTAADDR1
address_a[1] => ram_block2a2.PORTAADDR1
address_a[1] => ram_block2a3.PORTAADDR1
address_a[1] => ram_block2a4.PORTAADDR1
address_a[1] => ram_block2a5.PORTAADDR1
address_a[1] => ram_block2a6.PORTAADDR1
address_a[1] => ram_block2a7.PORTAADDR1
address_a[1] => ram_block2a8.PORTAADDR1
address_a[1] => ram_block2a9.PORTAADDR1
address_a[1] => ram_block2a10.PORTAADDR1
address_a[1] => ram_block2a11.PORTAADDR1
address_a[1] => ram_block2a12.PORTAADDR1
address_a[1] => ram_block2a13.PORTAADDR1
address_a[1] => ram_block2a14.PORTAADDR1
address_a[1] => ram_block2a15.PORTAADDR1
address_a[1] => ram_block2a16.PORTAADDR1
address_a[1] => ram_block2a17.PORTAADDR1
address_a[2] => ram_block2a0.PORTAADDR2
address_a[2] => ram_block2a1.PORTAADDR2
address_a[2] => ram_block2a2.PORTAADDR2
address_a[2] => ram_block2a3.PORTAADDR2
address_a[2] => ram_block2a4.PORTAADDR2
address_a[2] => ram_block2a5.PORTAADDR2
address_a[2] => ram_block2a6.PORTAADDR2
address_a[2] => ram_block2a7.PORTAADDR2
address_a[2] => ram_block2a8.PORTAADDR2
address_a[2] => ram_block2a9.PORTAADDR2
address_a[2] => ram_block2a10.PORTAADDR2
address_a[2] => ram_block2a11.PORTAADDR2
address_a[2] => ram_block2a12.PORTAADDR2
address_a[2] => ram_block2a13.PORTAADDR2
address_a[2] => ram_block2a14.PORTAADDR2
address_a[2] => ram_block2a15.PORTAADDR2
address_a[2] => ram_block2a16.PORTAADDR2
address_a[2] => ram_block2a17.PORTAADDR2
address_a[3] => ram_block2a0.PORTAADDR3
address_a[3] => ram_block2a1.PORTAADDR3
address_a[3] => ram_block2a2.PORTAADDR3
address_a[3] => ram_block2a3.PORTAADDR3
address_a[3] => ram_block2a4.PORTAADDR3
address_a[3] => ram_block2a5.PORTAADDR3
address_a[3] => ram_block2a6.PORTAADDR3
address_a[3] => ram_block2a7.PORTAADDR3
address_a[3] => ram_block2a8.PORTAADDR3
address_a[3] => ram_block2a9.PORTAADDR3
address_a[3] => ram_block2a10.PORTAADDR3
address_a[3] => ram_block2a11.PORTAADDR3
address_a[3] => ram_block2a12.PORTAADDR3
address_a[3] => ram_block2a13.PORTAADDR3
address_a[3] => ram_block2a14.PORTAADDR3
address_a[3] => ram_block2a15.PORTAADDR3
address_a[3] => ram_block2a16.PORTAADDR3
address_a[3] => ram_block2a17.PORTAADDR3
address_a[4] => ram_block2a0.PORTAADDR4
address_a[4] => ram_block2a1.PORTAADDR4
address_a[4] => ram_block2a2.PORTAADDR4
address_a[4] => ram_block2a3.PORTAADDR4
address_a[4] => ram_block2a4.PORTAADDR4
address_a[4] => ram_block2a5.PORTAADDR4
address_a[4] => ram_block2a6.PORTAADDR4
address_a[4] => ram_block2a7.PORTAADDR4
address_a[4] => ram_block2a8.PORTAADDR4
address_a[4] => ram_block2a9.PORTAADDR4
address_a[4] => ram_block2a10.PORTAADDR4
address_a[4] => ram_block2a11.PORTAADDR4
address_a[4] => ram_block2a12.PORTAADDR4
address_a[4] => ram_block2a13.PORTAADDR4
address_a[4] => ram_block2a14.PORTAADDR4
address_a[4] => ram_block2a15.PORTAADDR4
address_a[4] => ram_block2a16.PORTAADDR4
address_a[4] => ram_block2a17.PORTAADDR4
address_a[5] => ram_block2a0.PORTAADDR5
address_a[5] => ram_block2a1.PORTAADDR5
address_a[5] => ram_block2a2.PORTAADDR5
address_a[5] => ram_block2a3.PORTAADDR5
address_a[5] => ram_block2a4.PORTAADDR5
address_a[5] => ram_block2a5.PORTAADDR5
address_a[5] => ram_block2a6.PORTAADDR5
address_a[5] => ram_block2a7.PORTAADDR5
address_a[5] => ram_block2a8.PORTAADDR5
address_a[5] => ram_block2a9.PORTAADDR5
address_a[5] => ram_block2a10.PORTAADDR5
address_a[5] => ram_block2a11.PORTAADDR5
address_a[5] => ram_block2a12.PORTAADDR5
address_a[5] => ram_block2a13.PORTAADDR5
address_a[5] => ram_block2a14.PORTAADDR5
address_a[5] => ram_block2a15.PORTAADDR5
address_a[5] => ram_block2a16.PORTAADDR5
address_a[5] => ram_block2a17.PORTAADDR5
address_b[0] => ram_block2a0.PORTBADDR
address_b[0] => ram_block2a1.PORTBADDR
address_b[0] => ram_block2a2.PORTBADDR
address_b[0] => ram_block2a3.PORTBADDR
address_b[0] => ram_block2a4.PORTBADDR
address_b[0] => ram_block2a5.PORTBADDR
address_b[0] => ram_block2a6.PORTBADDR
address_b[0] => ram_block2a7.PORTBADDR
address_b[0] => ram_block2a8.PORTBADDR
address_b[0] => ram_block2a9.PORTBADDR
address_b[0] => ram_block2a10.PORTBADDR
address_b[0] => ram_block2a11.PORTBADDR
address_b[0] => ram_block2a12.PORTBADDR
address_b[0] => ram_block2a13.PORTBADDR
address_b[0] => ram_block2a14.PORTBADDR
address_b[0] => ram_block2a15.PORTBADDR
address_b[0] => ram_block2a16.PORTBADDR
address_b[0] => ram_block2a17.PORTBADDR
address_b[1] => ram_block2a0.PORTBADDR1
address_b[1] => ram_block2a1.PORTBADDR1
address_b[1] => ram_block2a2.PORTBADDR1
address_b[1] => ram_block2a3.PORTBADDR1
address_b[1] => ram_block2a4.PORTBADDR1
address_b[1] => ram_block2a5.PORTBADDR1
address_b[1] => ram_block2a6.PORTBADDR1
address_b[1] => ram_block2a7.PORTBADDR1
address_b[1] => ram_block2a8.PORTBADDR1
address_b[1] => ram_block2a9.PORTBADDR1
address_b[1] => ram_block2a10.PORTBADDR1
address_b[1] => ram_block2a11.PORTBADDR1
address_b[1] => ram_block2a12.PORTBADDR1
address_b[1] => ram_block2a13.PORTBADDR1
address_b[1] => ram_block2a14.PORTBADDR1
address_b[1] => ram_block2a15.PORTBADDR1
address_b[1] => ram_block2a16.PORTBADDR1
address_b[1] => ram_block2a17.PORTBADDR1
address_b[2] => ram_block2a0.PORTBADDR2
address_b[2] => ram_block2a1.PORTBADDR2
address_b[2] => ram_block2a2.PORTBADDR2
address_b[2] => ram_block2a3.PORTBADDR2
address_b[2] => ram_block2a4.PORTBADDR2
address_b[2] => ram_block2a5.PORTBADDR2
address_b[2] => ram_block2a6.PORTBADDR2
address_b[2] => ram_block2a7.PORTBADDR2
address_b[2] => ram_block2a8.PORTBADDR2
address_b[2] => ram_block2a9.PORTBADDR2
address_b[2] => ram_block2a10.PORTBADDR2
address_b[2] => ram_block2a11.PORTBADDR2
address_b[2] => ram_block2a12.PORTBADDR2
address_b[2] => ram_block2a13.PORTBADDR2
address_b[2] => ram_block2a14.PORTBADDR2
address_b[2] => ram_block2a15.PORTBADDR2
address_b[2] => ram_block2a16.PORTBADDR2
address_b[2] => ram_block2a17.PORTBADDR2
address_b[3] => ram_block2a0.PORTBADDR3
address_b[3] => ram_block2a1.PORTBADDR3
address_b[3] => ram_block2a2.PORTBADDR3
address_b[3] => ram_block2a3.PORTBADDR3
address_b[3] => ram_block2a4.PORTBADDR3
address_b[3] => ram_block2a5.PORTBADDR3
address_b[3] => ram_block2a6.PORTBADDR3
address_b[3] => ram_block2a7.PORTBADDR3
address_b[3] => ram_block2a8.PORTBADDR3
address_b[3] => ram_block2a9.PORTBADDR3
address_b[3] => ram_block2a10.PORTBADDR3
address_b[3] => ram_block2a11.PORTBADDR3
address_b[3] => ram_block2a12.PORTBADDR3
address_b[3] => ram_block2a13.PORTBADDR3
address_b[3] => ram_block2a14.PORTBADDR3
address_b[3] => ram_block2a15.PORTBADDR3
address_b[3] => ram_block2a16.PORTBADDR3
address_b[3] => ram_block2a17.PORTBADDR3
address_b[4] => ram_block2a0.PORTBADDR4
address_b[4] => ram_block2a1.PORTBADDR4
address_b[4] => ram_block2a2.PORTBADDR4
address_b[4] => ram_block2a3.PORTBADDR4
address_b[4] => ram_block2a4.PORTBADDR4
address_b[4] => ram_block2a5.PORTBADDR4
address_b[4] => ram_block2a6.PORTBADDR4
address_b[4] => ram_block2a7.PORTBADDR4
address_b[4] => ram_block2a8.PORTBADDR4
address_b[4] => ram_block2a9.PORTBADDR4
address_b[4] => ram_block2a10.PORTBADDR4
address_b[4] => ram_block2a11.PORTBADDR4
address_b[4] => ram_block2a12.PORTBADDR4
address_b[4] => ram_block2a13.PORTBADDR4
address_b[4] => ram_block2a14.PORTBADDR4
address_b[4] => ram_block2a15.PORTBADDR4
address_b[4] => ram_block2a16.PORTBADDR4
address_b[4] => ram_block2a17.PORTBADDR4
address_b[5] => ram_block2a0.PORTBADDR5
address_b[5] => ram_block2a1.PORTBADDR5
address_b[5] => ram_block2a2.PORTBADDR5
address_b[5] => ram_block2a3.PORTBADDR5
address_b[5] => ram_block2a4.PORTBADDR5
address_b[5] => ram_block2a5.PORTBADDR5
address_b[5] => ram_block2a6.PORTBADDR5
address_b[5] => ram_block2a7.PORTBADDR5
address_b[5] => ram_block2a8.PORTBADDR5
address_b[5] => ram_block2a9.PORTBADDR5
address_b[5] => ram_block2a10.PORTBADDR5
address_b[5] => ram_block2a11.PORTBADDR5
address_b[5] => ram_block2a12.PORTBADDR5
address_b[5] => ram_block2a13.PORTBADDR5
address_b[5] => ram_block2a14.PORTBADDR5
address_b[5] => ram_block2a15.PORTBADDR5
address_b[5] => ram_block2a16.PORTBADDR5
address_b[5] => ram_block2a17.PORTBADDR5
clock0 => ram_block2a0.CLK0
clock0 => ram_block2a1.CLK0
clock0 => ram_block2a2.CLK0
clock0 => ram_block2a3.CLK0
clock0 => ram_block2a4.CLK0
clock0 => ram_block2a5.CLK0
clock0 => ram_block2a6.CLK0
clock0 => ram_block2a7.CLK0
clock0 => ram_block2a8.CLK0
clock0 => ram_block2a9.CLK0
clock0 => ram_block2a10.CLK0
clock0 => ram_block2a11.CLK0
clock0 => ram_block2a12.CLK0
clock0 => ram_block2a13.CLK0
clock0 => ram_block2a14.CLK0
clock0 => ram_block2a15.CLK0
clock0 => ram_block2a16.CLK0
clock0 => ram_block2a17.CLK0
clock1 => ram_block2a0.CLK1
clock1 => ram_block2a1.CLK1
clock1 => ram_block2a2.CLK1
clock1 => ram_block2a3.CLK1
clock1 => ram_block2a4.CLK1
clock1 => ram_block2a5.CLK1
clock1 => ram_block2a6.CLK1
clock1 => ram_block2a7.CLK1
clock1 => ram_block2a8.CLK1
clock1 => ram_block2a9.CLK1
clock1 => ram_block2a10.CLK1
clock1 => ram_block2a11.CLK1
clock1 => ram_block2a12.CLK1
clock1 => ram_block2a13.CLK1
clock1 => ram_block2a14.CLK1
clock1 => ram_block2a15.CLK1
clock1 => ram_block2a16.CLK1
clock1 => ram_block2a17.CLK1
clocken1 => ram_block2a0.ENA1
clocken1 => ram_block2a1.ENA1
clocken1 => ram_block2a2.ENA1
clocken1 => ram_block2a3.ENA1
clocken1 => ram_block2a4.ENA1
clocken1 => ram_block2a5.ENA1
clocken1 => ram_block2a6.ENA1
clocken1 => ram_block2a7.ENA1
clocken1 => ram_block2a8.ENA1
clocken1 => ram_block2a9.ENA1
clocken1 => ram_block2a10.ENA1
clocken1 => ram_block2a11.ENA1
clocken1 => ram_block2a12.ENA1
clocken1 => ram_block2a13.ENA1
clocken1 => ram_block2a14.ENA1
clocken1 => ram_block2a15.ENA1
clocken1 => ram_block2a16.ENA1
clocken1 => ram_block2a17.ENA1
data_a[0] => ram_block2a0.PORTADATAIN
data_a[1] => ram_block2a1.PORTADATAIN
data_a[2] => ram_block2a2.PORTADATAIN
data_a[3] => ram_block2a3.PORTADATAIN
data_a[4] => ram_block2a4.PORTADATAIN
data_a[5] => ram_block2a5.PORTADATAIN
data_a[6] => ram_block2a6.PORTADATAIN
data_a[7] => ram_block2a7.PORTADATAIN
data_a[8] => ram_block2a8.PORTADATAIN
data_a[9] => ram_block2a9.PORTADATAIN
data_a[10] => ram_block2a10.PORTADATAIN
data_a[11] => ram_block2a11.PORTADATAIN
data_a[12] => ram_block2a12.PORTADATAIN
data_a[13] => ram_block2a13.PORTADATAIN
data_a[14] => ram_block2a14.PORTADATAIN
data_a[15] => ram_block2a15.PORTADATAIN
data_a[16] => ram_block2a16.PORTADATAIN
data_a[17] => ram_block2a17.PORTADATAIN
q_b[0] <= ram_block2a0.PORTBDATAOUT
q_b[1] <= ram_block2a1.PORTBDATAOUT
q_b[2] <= ram_block2a2.PORTBDATAOUT
q_b[3] <= ram_block2a3.PORTBDATAOUT
q_b[4] <= ram_block2a4.PORTBDATAOUT
q_b[5] <= ram_block2a5.PORTBDATAOUT
q_b[6] <= ram_block2a6.PORTBDATAOUT
q_b[7] <= ram_block2a7.PORTBDATAOUT
q_b[8] <= ram_block2a8.PORTBDATAOUT
q_b[9] <= ram_block2a9.PORTBDATAOUT
q_b[10] <= ram_block2a10.PORTBDATAOUT
q_b[11] <= ram_block2a11.PORTBDATAOUT
q_b[12] <= ram_block2a12.PORTBDATAOUT
q_b[13] <= ram_block2a13.PORTBDATAOUT
q_b[14] <= ram_block2a14.PORTBDATAOUT
q_b[15] <= ram_block2a15.PORTBDATAOUT
q_b[16] <= ram_block2a16.PORTBDATAOUT
q_b[17] <= ram_block2a17.PORTBDATAOUT
wren_a => ram_block2a0.PORTAWE
wren_a => ram_block2a0.ENA0
wren_a => ram_block2a1.PORTAWE
wren_a => ram_block2a1.ENA0
wren_a => ram_block2a2.PORTAWE
wren_a => ram_block2a2.ENA0
wren_a => ram_block2a3.PORTAWE
wren_a => ram_block2a3.ENA0
wren_a => ram_block2a4.PORTAWE
wren_a => ram_block2a4.ENA0
wren_a => ram_block2a5.PORTAWE
wren_a => ram_block2a5.ENA0
wren_a => ram_block2a6.PORTAWE
wren_a => ram_block2a6.ENA0
wren_a => ram_block2a7.PORTAWE
wren_a => ram_block2a7.ENA0
wren_a => ram_block2a8.PORTAWE
wren_a => ram_block2a8.ENA0
wren_a => ram_block2a9.PORTAWE
wren_a => ram_block2a9.ENA0
wren_a => ram_block2a10.PORTAWE
wren_a => ram_block2a10.ENA0
wren_a => ram_block2a11.PORTAWE
wren_a => ram_block2a11.ENA0
wren_a => ram_block2a12.PORTAWE
wren_a => ram_block2a12.ENA0
wren_a => ram_block2a13.PORTAWE
wren_a => ram_block2a13.ENA0
wren_a => ram_block2a14.PORTAWE
wren_a => ram_block2a14.ENA0
wren_a => ram_block2a15.PORTAWE
wren_a => ram_block2a15.ENA0
wren_a => ram_block2a16.PORTAWE
wren_a => ram_block2a16.ENA0
wren_a => ram_block2a17.PORTAWE
wren_a => ram_block2a17.ENA0


|block|lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|cntr_fjb:rd_ptr_count
aclr => counter_reg_bit3a[5].ACLR
aclr => counter_reg_bit3a[4].ACLR
aclr => counter_reg_bit3a[3].ACLR
aclr => counter_reg_bit3a[2].ACLR
aclr => counter_reg_bit3a[1].ACLR
aclr => counter_reg_bit3a[0].ACLR
clock => counter_reg_bit3a[5].CLK
clock => counter_reg_bit3a[4].CLK
clock => counter_reg_bit3a[3].CLK
clock => counter_reg_bit3a[2].CLK
clock => counter_reg_bit3a[1].CLK
clock => counter_reg_bit3a[0].CLK
q[0] <= counter_reg_bit3a[0].REGOUT
q[1] <= counter_reg_bit3a[1].REGOUT
q[2] <= counter_reg_bit3a[2].REGOUT
q[3] <= counter_reg_bit3a[3].REGOUT
q[4] <= counter_reg_bit3a[4].REGOUT
q[5] <= counter_reg_bit3a[5].REGOUT


|block|lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|cntr_fjb:wr_ptr
aclr => counter_reg_bit3a[5].ACLR
aclr => counter_reg_bit3a[4].ACLR
aclr => counter_reg_bit3a[3].ACLR
aclr => counter_reg_bit3a[2].ACLR
aclr => counter_reg_bit3a[1].ACLR
aclr => counter_reg_bit3a[0].ACLR
clock => counter_reg_bit3a[5].CLK
clock => counter_reg_bit3a[4].CLK
clock => counter_reg_bit3a[3].CLK
clock => counter_reg_bit3a[2].CLK
clock => counter_reg_bit3a[1].CLK
clock => counter_reg_bit3a[0].CLK
q[0] <= counter_reg_bit3a[0].REGOUT
q[1] <= counter_reg_bit3a[1].REGOUT
q[2] <= counter_reg_bit3a[2].REGOUT
q[3] <= counter_reg_bit3a[3].REGOUT
q[4] <= counter_reg_bit3a[4].REGOUT
q[5] <= counter_reg_bit3a[5].REGOUT


|block|p2s:inst28
clk => count[6].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => cnt.CLK
clk => data_temp[1][17].CLK
clk => data_temp[1][16].CLK
clk => data_temp[1][15].CLK
clk => data_temp[1][14].CLK
clk => data_temp[1][13].CLK
clk => data_temp[1][12].CLK
clk => data_temp[1][11].CLK
clk => data_temp[1][10].CLK
clk => data_temp[1][9].CLK
clk => data_temp[1][8].CLK
clk => data_temp[1][7].CLK
clk => data_temp[1][6].CLK
clk => data_temp[1][5].CLK
clk => data_temp[1][4].CLK
clk => data_temp[1][3].CLK
clk => data_temp[1][2].CLK
clk => data_temp[1][1].CLK
clk => data_temp[1][0].CLK
clk => data_temp[0][17].CLK
clk => data_temp[0][16].CLK
clk => data_temp[0][15].CLK
clk => data_temp[0][14].CLK
clk => data_temp[0][13].CLK
clk => data_temp[0][12].CLK
clk => data_temp[0][11].CLK
clk => data_temp[0][10].CLK
clk => data_temp[0][9].CLK
clk => data_temp[0][8].CLK
clk => data_temp[0][7].CLK
clk => data_temp[0][6].CLK
clk => data_temp[0][5].CLK
clk => data_temp[0][4].CLK
clk => data_temp[0][3].CLK
clk => data_temp[0][2].CLK
clk => data_temp[0][1].CLK
clk => data_temp[0][0].CLK
reset => source_valid~0.IN0
reset => count[6].ACLR
reset => count[5].ACLR
reset => count[4].ACLR
reset => count[3].ACLR
reset => count[2].ACLR
reset => count[1].ACLR
reset => count[0].ACLR
reset => cnt.ACLR
reset => data_temp[1][17].ACLR
reset => data_temp[1][16].ACLR
reset => data_temp[1][15].ACLR
reset => data_temp[1][14].ACLR
reset => data_temp[1][13].ACLR
reset => data_temp[1][12].ACLR
reset => data_temp[1][11].ACLR
reset => data_temp[1][10].ACLR
reset => data_temp[1][9].ACLR
reset => data_temp[1][8].ACLR
reset => data_temp[1][7].ACLR
reset => data_temp[1][6].ACLR
reset => data_temp[1][5].ACLR
reset => data_temp[1][4].ACLR
reset => data_temp[1][3].ACLR
reset => data_temp[1][2].ACLR
reset => data_temp[1][1].ACLR
reset => data_temp[1][0].ACLR
reset => data_temp[0][17].ACLR
reset => data_temp[0][16].ACLR
reset => data_temp[0][15].ACLR
reset => data_temp[0][14].ACLR
reset => data_temp[0][13].ACLR
reset => data_temp[0][12].ACLR
reset => data_temp[0][11].ACLR
reset => data_temp[0][10].ACLR
reset => data_temp[0][9].ACLR
reset => data_temp[0][8].ACLR
reset => data_temp[0][7].ACLR
reset => data_temp[0][6].ACLR
reset => data_temp[0][5].ACLR
reset => data_temp[0][4].ACLR
reset => data_temp[0][3].ACLR
reset => data_temp[0][2].ACLR
reset => data_temp[0][1].ACLR
reset => data_temp[0][0].ACLR
sink_valid => data_temp~35.OUTPUTSELECT
sink_valid => data_temp~34.OUTPUTSELECT
sink_valid => data_temp~33.OUTPUTSELECT
sink_valid => data_temp~32.OUTPUTSELECT
sink_valid => data_temp~31.OUTPUTSELECT
sink_valid => data_temp~30.OUTPUTSELECT
sink_valid => data_temp~29.OUTPUTSELECT
sink_valid => data_temp~28.OUTPUTSELECT
sink_valid => data_temp~27.OUTPUTSELECT
sink_valid => data_temp~26.OUTPUTSELECT
sink_valid => data_temp~25.OUTPUTSELECT
sink_valid => data_temp~24.OUTPUTSELECT
sink_valid => data_temp~23.OUTPUTSELECT
sink_valid => data_temp~22.OUTPUTSELECT
sink_valid => data_temp~21.OUTPUTSELECT
sink_valid => data_temp~20.OUTPUTSELECT
sink_valid => data_temp~19.OUTPUTSELECT
sink_valid => data_temp~18.OUTPUTSELECT
sink_valid => data_temp~17.OUTPUTSELECT
sink_valid => data_temp~16.OUTPUTSELECT
sink_valid => data_temp~15.OUTPUTSELECT
sink_valid => data_temp~14.OUTPUTSELECT
sink_valid => data_temp~13.OUTPUTSELECT
sink_valid => data_temp~12.OUTPUTSELECT
sink_valid => data_temp~11.OUTPUTSELECT
sink_valid => data_temp~10.OUTPUTSELECT
sink_valid => data_temp~9.OUTPUTSELECT
sink_valid => data_temp~8.OUTPUTSELECT
sink_valid => data_temp~7.OUTPUTSELECT
sink_valid => data_temp~6.OUTPUTSELECT
sink_valid => data_temp~5.OUTPUTSELECT
sink_valid => data_temp~4.OUTPUTSELECT
sink_valid => data_temp~3.OUTPUTSELECT
sink_valid => data_temp~2.OUTPUTSELECT
sink_valid => data_temp~1.OUTPUTSELECT
sink_valid => data_temp~0.OUTPUTSELECT
sink_valid => count~13.OUTPUTSELECT
sink_valid => count~12.OUTPUTSELECT
sink_valid => count~11.OUTPUTSELECT
sink_valid => count~10.OUTPUTSELECT
sink_valid => count~9.OUTPUTSELECT
sink_valid => count~8.OUTPUTSELECT
sink_valid => count~7.OUTPUTSELECT
sink_valid => cnt~0.OUTPUTSELECT
data_in0[0] => data_temp~35.DATAB
data_in0[1] => data_temp~34.DATAB
data_in0[2] => data_temp~33.DATAB
data_in0[3] => data_temp~32.DATAB
data_in0[4] => data_temp~31.DATAB
data_in0[5] => data_temp~30.DATAB
data_in0[6] => data_temp~29.DATAB
data_in0[7] => data_temp~28.DATAB
data_in0[8] => data_temp~27.DATAB
data_in0[9] => data_temp~26.DATAB
data_in0[10] => data_temp~25.DATAB
data_in0[11] => data_temp~24.DATAB
data_in0[12] => data_temp~23.DATAB
data_in0[13] => data_temp~22.DATAB
data_in0[14] => data_temp~21.DATAB
data_in0[15] => data_temp~20.DATAB
data_in0[16] => data_temp~19.DATAB
data_in0[17] => data_temp~18.DATAB
data_in1[0] => data_temp~17.DATAB
data_in1[1] => data_temp~16.DATAB
data_in1[2] => data_temp~15.DATAB
data_in1[3] => data_temp~14.DATAB
data_in1[4] => data_temp~13.DATAB
data_in1[5] => data_temp~12.DATAB
data_in1[6] => data_temp~11.DATAB
data_in1[7] => data_temp~10.DATAB
data_in1[8] => data_temp~9.DATAB
data_in1[9] => data_temp~8.DATAB
data_in1[10] => data_temp~7.DATAB
data_in1[11] => data_temp~6.DATAB
data_in1[12] => data_temp~5.DATAB
data_in1[13] => data_temp~4.DATAB
data_in1[14] => data_temp~3.DATAB
data_in1[15] => data_temp~2.DATAB
data_in1[16] => data_temp~1.DATAB
data_in1[17] => data_temp~0.DATAB
data_out[0] <= data_out~37.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out~36.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out~35.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out~34.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out~33.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out~32.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out~31.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out~30.DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= data_out~29.DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= data_out~28.DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= data_out~27.DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= data_out~26.DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= data_out~25.DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= data_out~24.DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= data_out~23.DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= data_out~22.DB_MAX_OUTPUT_PORT_TYPE
data_out[16] <= data_out~21.DB_MAX_OUTPUT_PORT_TYPE
data_out[17] <= data_out~20.DB_MAX_OUTPUT_PORT_TYPE
source_valid <= source_valid~0.DB_MAX_OUTPUT_PORT_TYPE


|block|butterfly:inst48
clk => clk~0.IN3
reset => real_a[16].ACLR
reset => real_a[15].ACLR
reset => real_a[14].ACLR
reset => real_a[13].ACLR
reset => real_a[12].ACLR
reset => real_a[11].ACLR
reset => real_a[10].ACLR
reset => real_a[9].ACLR
reset => real_a[8].ACLR
reset => real_a[7].ACLR
reset => real_a[6].ACLR
reset => real_a[5].ACLR
reset => real_a[4].ACLR
reset => real_a[3].ACLR
reset => real_a[2].ACLR
reset => real_a[1].ACLR
reset => real_a[0].ACLR
reset => imag_a[16].ACLR
reset => imag_a[15].ACLR
reset => imag_a[14].ACLR
reset => imag_a[13].ACLR
reset => imag_a[12].ACLR
reset => imag_a[11].ACLR
reset => imag_a[10].ACLR
reset => imag_a[9].ACLR
reset => imag_a[8].ACLR
reset => imag_a[7].ACLR
reset => imag_a[6].ACLR
reset => imag_a[5].ACLR
reset => imag_a[4].ACLR
reset => imag_a[3].ACLR
reset => imag_a[2].ACLR
reset => imag_a[1].ACLR
reset => imag_a[0].ACLR
reset => real_b[16].ACLR
reset => real_b[15].ACLR
reset => real_b[14].ACLR
reset => real_b[13].ACLR
reset => real_b[12].ACLR
reset => real_b[11].ACLR
reset => real_b[10].ACLR
reset => real_b[9].ACLR
reset => real_b[8].ACLR
reset => real_b[7].ACLR
reset => real_b[6].ACLR
reset => real_b[5].ACLR
reset => real_b[4].ACLR
reset => real_b[3].ACLR
reset => real_b[2].ACLR
reset => real_b[1].ACLR
reset => real_b[0].ACLR
reset => imag_b[16].ACLR
reset => imag_b[15].ACLR
reset => imag_b[14].ACLR
reset => imag_b[13].ACLR
reset => imag_b[12].ACLR
reset => imag_b[11].ACLR
reset => imag_b[10].ACLR
reset => imag_b[9].ACLR
reset => imag_b[8].ACLR
reset => imag_b[7].ACLR
reset => imag_b[6].ACLR
reset => imag_b[5].ACLR
reset => imag_b[4].ACLR
reset => imag_b[3].ACLR
reset => imag_b[2].ACLR
reset => imag_b[1].ACLR
reset => imag_b[0].ACLR
reset => real_WN_in[16].ACLR
reset => real_WN_in[15].ACLR
reset => real_WN_in[14].ACLR
reset => real_WN_in[13].ACLR
reset => real_WN_in[12].ACLR
reset => real_WN_in[11].ACLR
reset => real_WN_in[10].ACLR
reset => real_WN_in[9].ACLR
reset => real_WN_in[8].ACLR
reset => real_WN_in[7].ACLR
reset => real_WN_in[6].ACLR
reset => real_WN_in[5].ACLR
reset => real_WN_in[4].ACLR
reset => real_WN_in[3].ACLR
reset => real_WN_in[2].ACLR
reset => real_WN_in[1].ACLR
reset => real_WN_in[0].ACLR
reset => imag_WN_in[16].ACLR
reset => imag_WN_in[15].ACLR
reset => imag_WN_in[14].ACLR
reset => imag_WN_in[13].ACLR
reset => imag_WN_in[12].ACLR
reset => imag_WN_in[11].ACLR
reset => imag_WN_in[10].ACLR
reset => imag_WN_in[9].ACLR
reset => imag_WN_in[8].ACLR
reset => imag_WN_in[7].ACLR
reset => imag_WN_in[6].ACLR
reset => imag_WN_in[5].ACLR
reset => imag_WN_in[4].ACLR
reset => imag_WN_in[3].ACLR
reset => imag_WN_in[2].ACLR
reset => imag_WN_in[1].ACLR
reset => imag_WN_in[0].ACLR
reset => cnt[7].ACLR
reset => cnt[6].ACLR
reset => cnt[5].ACLR
reset => cnt[4].ACLR
reset => cnt[3].ACLR
reset => cnt[2].ACLR
reset => cnt[1].ACLR
reset => cnt[0].ACLR
reset => current_state~1.IN1
sink_valid => next_state.work.DATAB
sink_valid => next_cnt[0].DATAB
sink_valid => imag_WN_in~33.OUTPUTSELECT
sink_valid => imag_WN_in~32.OUTPUTSELECT
sink_valid => imag_WN_in~31.OUTPUTSELECT
sink_valid => imag_WN_in~30.OUTPUTSELECT
sink_valid => imag_WN_in~29.OUTPUTSELECT
sink_valid => imag_WN_in~28.OUTPUTSELECT
sink_valid => imag_WN_in~27.OUTPUTSELECT
sink_valid => imag_WN_in~26.OUTPUTSELECT
sink_valid => imag_WN_in~25.OUTPUTSELECT
sink_valid => imag_WN_in~24.OUTPUTSELECT
sink_valid => imag_WN_in~23.OUTPUTSELECT
sink_valid => imag_WN_in~22.OUTPUTSELECT
sink_valid => imag_WN_in~21.OUTPUTSELECT
sink_valid => imag_WN_in~20.OUTPUTSELECT
sink_valid => imag_WN_in~19.OUTPUTSELECT
sink_valid => imag_WN_in~18.OUTPUTSELECT
sink_valid => imag_WN_in~17.OUTPUTSELECT
sink_valid => real_WN_in~33.OUTPUTSELECT
sink_valid => real_WN_in~32.OUTPUTSELECT
sink_valid => real_WN_in~31.OUTPUTSELECT
sink_valid => real_WN_in~30.OUTPUTSELECT
sink_valid => real_WN_in~29.OUTPUTSELECT
sink_valid => real_WN_in~28.OUTPUTSELECT
sink_valid => real_WN_in~27.OUTPUTSELECT
sink_valid => real_WN_in~26.OUTPUTSELECT
sink_valid => real_WN_in~25.OUTPUTSELECT
sink_valid => real_WN_in~24.OUTPUTSELECT
sink_valid => real_WN_in~23.OUTPUTSELECT
sink_valid => real_WN_in~22.OUTPUTSELECT
sink_valid => real_WN_in~21.OUTPUTSELECT
sink_valid => real_WN_in~20.OUTPUTSELECT
sink_valid => real_WN_in~19.OUTPUTSELECT
sink_valid => real_WN_in~18.OUTPUTSELECT
sink_valid => real_WN_in~17.OUTPUTSELECT
sink_valid => imag_b~33.OUTPUTSELECT
sink_valid => imag_b~32.OUTPUTSELECT
sink_valid => imag_b~31.OUTPUTSELECT
sink_valid => imag_b~30.OUTPUTSELECT
sink_valid => imag_b~29.OUTPUTSELECT
sink_valid => imag_b~28.OUTPUTSELECT
sink_valid => imag_b~27.OUTPUTSELECT
sink_valid => imag_b~26.OUTPUTSELECT
sink_valid => imag_b~25.OUTPUTSELECT
sink_valid => imag_b~24.OUTPUTSELECT
sink_valid => imag_b~23.OUTPUTSELECT
sink_valid => imag_b~22.OUTPUTSELECT
sink_valid => imag_b~21.OUTPUTSELECT
sink_valid => imag_b~20.OUTPUTSELECT
sink_valid => imag_b~19.OUTPUTSELECT
sink_valid => imag_b~18.OUTPUTSELECT
sink_valid => imag_b~17.OUTPUTSELECT
sink_valid => real_b~33.OUTPUTSELECT
sink_valid => real_b~32.OUTPUTSELECT
sink_valid => real_b~31.OUTPUTSELECT
sink_valid => real_b~30.OUTPUTSELECT
sink_valid => real_b~29.OUTPUTSELECT
sink_valid => real_b~28.OUTPUTSELECT
sink_valid => real_b~27.OUTPUTSELECT
sink_valid => real_b~26.OUTPUTSELECT
sink_valid => real_b~25.OUTPUTSELECT
sink_valid => real_b~24.OUTPUTSELECT
sink_valid => real_b~23.OUTPUTSELECT
sink_valid => real_b~22.OUTPUTSELECT
sink_valid => real_b~21.OUTPUTSELECT
sink_valid => real_b~20.OUTPUTSELECT
sink_valid => real_b~19.OUTPUTSELECT
sink_valid => real_b~18.OUTPUTSELECT
sink_valid => real_b~17.OUTPUTSELECT
sink_valid => imag_a~33.OUTPUTSELECT
sink_valid => imag_a~32.OUTPUTSELECT
sink_valid => imag_a~31.OUTPUTSELECT
sink_valid => imag_a~30.OUTPUTSELECT
sink_valid => imag_a~29.OUTPUTSELECT
sink_valid => imag_a~28.OUTPUTSELECT
sink_valid => imag_a~27.OUTPUTSELECT
sink_valid => imag_a~26.OUTPUTSELECT
sink_valid => imag_a~25.OUTPUTSELECT
sink_valid => imag_a~24.OUTPUTSELECT
sink_valid => imag_a~23.OUTPUTSELECT
sink_valid => imag_a~22.OUTPUTSELECT
sink_valid => imag_a~21.OUTPUTSELECT
sink_valid => imag_a~20.OUTPUTSELECT
sink_valid => imag_a~19.OUTPUTSELECT
sink_valid => imag_a~18.OUTPUTSELECT
sink_valid => imag_a~17.OUTPUTSELECT
sink_valid => real_a~33.OUTPUTSELECT
sink_valid => real_a~32.OUTPUTSELECT
sink_valid => real_a~31.OUTPUTSELECT
sink_valid => real_a~30.OUTPUTSELECT
sink_valid => real_a~29.OUTPUTSELECT
sink_valid => real_a~28.OUTPUTSELECT
sink_valid => real_a~27.OUTPUTSELECT
sink_valid => real_a~26.OUTPUTSELECT
sink_valid => real_a~25.OUTPUTSELECT
sink_valid => real_a~24.OUTPUTSELECT
sink_valid => real_a~23.OUTPUTSELECT
sink_valid => real_a~22.OUTPUTSELECT
sink_valid => real_a~21.OUTPUTSELECT
sink_valid => real_a~20.OUTPUTSELECT
sink_valid => real_a~19.OUTPUTSELECT
sink_valid => real_a~18.OUTPUTSELECT
sink_valid => real_a~17.OUTPUTSELECT
sink_valid => next_state.idle.DATAB
ar_in[0] => real_a~33.DATAB
ar_in[1] => real_a~32.DATAB
ar_in[2] => real_a~31.DATAB
ar_in[3] => real_a~30.DATAB
ar_in[4] => real_a~29.DATAB
ar_in[5] => real_a~28.DATAB
ar_in[6] => real_a~27.DATAB
ar_in[7] => real_a~26.DATAB
ar_in[8] => real_a~25.DATAB
ar_in[9] => real_a~24.DATAB
ar_in[10] => real_a~23.DATAB
ar_in[11] => real_a~22.DATAB
ar_in[12] => real_a~21.DATAB
ar_in[13] => real_a~20.DATAB
ar_in[14] => real_a~19.DATAB
ar_in[15] => real_a~18.DATAB
ar_in[15] => real_a~17.DATAB
ai_in[0] => imag_a~33.DATAB
ai_in[1] => imag_a~32.DATAB
ai_in[2] => imag_a~31.DATAB
ai_in[3] => imag_a~30.DATAB
ai_in[4] => imag_a~29.DATAB
ai_in[5] => imag_a~28.DATAB
ai_in[6] => imag_a~27.DATAB
ai_in[7] => imag_a~26.DATAB
ai_in[8] => imag_a~25.DATAB
ai_in[9] => imag_a~24.DATAB
ai_in[10] => imag_a~23.DATAB
ai_in[11] => imag_a~22.DATAB
ai_in[12] => imag_a~21.DATAB
ai_in[13] => imag_a~20.DATAB
ai_in[14] => imag_a~19.DATAB
ai_in[15] => imag_a~18.DATAB
ai_in[15] => imag_a~17.DATAB
br_in[0] => real_b~33.DATAB
br_in[1] => real_b~32.DATAB
br_in[2] => real_b~31.DATAB
br_in[3] => real_b~30.DATAB
br_in[4] => real_b~29.DATAB
br_in[5] => real_b~28.DATAB
br_in[6] => real_b~27.DATAB
br_in[7] => real_b~26.DATAB
br_in[8] => real_b~25.DATAB
br_in[9] => real_b~24.DATAB
br_in[10] => real_b~23.DATAB
br_in[11] => real_b~22.DATAB
br_in[12] => real_b~21.DATAB
br_in[13] => real_b~20.DATAB
br_in[14] => real_b~19.DATAB
br_in[15] => real_b~18.DATAB
br_in[15] => real_b~17.DATAB
bi_in[0] => imag_b~33.DATAB
bi_in[1] => imag_b~32.DATAB
bi_in[2] => imag_b~31.DATAB
bi_in[3] => imag_b~30.DATAB
bi_in[4] => imag_b~29.DATAB
bi_in[5] => imag_b~28.DATAB
bi_in[6] => imag_b~27.DATAB
bi_in[7] => imag_b~26.DATAB
bi_in[8] => imag_b~25.DATAB
bi_in[9] => imag_b~24.DATAB
bi_in[10] => imag_b~23.DATAB
bi_in[11] => imag_b~22.DATAB
bi_in[12] => imag_b~21.DATAB
bi_in[13] => imag_b~20.DATAB
bi_in[14] => imag_b~19.DATAB
bi_in[15] => imag_b~18.DATAB
bi_in[15] => imag_b~17.DATAB
WNr_in[0] => real_WN_in~33.DATAB
WNr_in[1] => real_WN_in~32.DATAB
WNr_in[2] => real_WN_in~31.DATAB
WNr_in[3] => real_WN_in~30.DATAB
WNr_in[4] => real_WN_in~29.DATAB
WNr_in[5] => real_WN_in~28.DATAB
WNr_in[6] => real_WN_in~27.DATAB
WNr_in[7] => real_WN_in~26.DATAB
WNr_in[8] => real_WN_in~25.DATAB
WNr_in[9] => real_WN_in~24.DATAB
WNr_in[10] => real_WN_in~23.DATAB
WNr_in[11] => real_WN_in~22.DATAB
WNr_in[12] => real_WN_in~21.DATAB
WNr_in[13] => real_WN_in~20.DATAB
WNr_in[14] => real_WN_in~19.DATAB
WNr_in[15] => real_WN_in~18.DATAB
WNr_in[15] => real_WN_in~17.DATAB
WNi_in[0] => imag_WN_in~33.DATAB
WNi_in[1] => imag_WN_in~32.DATAB
WNi_in[2] => imag_WN_in~31.DATAB
WNi_in[3] => imag_WN_in~30.DATAB
WNi_in[4] => imag_WN_in~29.DATAB
WNi_in[5] => imag_WN_in~28.DATAB
WNi_in[6] => imag_WN_in~27.DATAB
WNi_in[7] => imag_WN_in~26.DATAB
WNi_in[8] => imag_WN_in~25.DATAB
WNi_in[9] => imag_WN_in~24.DATAB
WNi_in[10] => imag_WN_in~23.DATAB
WNi_in[11] => imag_WN_in~22.DATAB
WNi_in[12] => imag_WN_in~21.DATAB
WNi_in[13] => imag_WN_in~20.DATAB
WNi_in[14] => imag_WN_in~19.DATAB
WNi_in[15] => imag_WN_in~18.DATAB
WNi_in[15] => imag_WN_in~17.DATAB
ar_out[0] <= ar_out~17.DB_MAX_OUTPUT_PORT_TYPE
ar_out[1] <= ar_out~16.DB_MAX_OUTPUT_PORT_TYPE
ar_out[2] <= ar_out~15.DB_MAX_OUTPUT_PORT_TYPE
ar_out[3] <= ar_out~14.DB_MAX_OUTPUT_PORT_TYPE
ar_out[4] <= ar_out~13.DB_MAX_OUTPUT_PORT_TYPE
ar_out[5] <= ar_out~12.DB_MAX_OUTPUT_PORT_TYPE
ar_out[6] <= ar_out~11.DB_MAX_OUTPUT_PORT_TYPE
ar_out[7] <= ar_out~10.DB_MAX_OUTPUT_PORT_TYPE
ar_out[8] <= ar_out~9.DB_MAX_OUTPUT_PORT_TYPE
ar_out[9] <= ar_out~8.DB_MAX_OUTPUT_PORT_TYPE
ar_out[10] <= ar_out~7.DB_MAX_OUTPUT_PORT_TYPE
ar_out[11] <= ar_out~6.DB_MAX_OUTPUT_PORT_TYPE
ar_out[12] <= ar_out~5.DB_MAX_OUTPUT_PORT_TYPE
ar_out[13] <= ar_out~4.DB_MAX_OUTPUT_PORT_TYPE
ar_out[14] <= ar_out~3.DB_MAX_OUTPUT_PORT_TYPE
ar_out[15] <= ar_out~2.DB_MAX_OUTPUT_PORT_TYPE
ar_out[16] <= ar_out~1.DB_MAX_OUTPUT_PORT_TYPE
ar_out[17] <= ar_out~0.DB_MAX_OUTPUT_PORT_TYPE
ai_out[0] <= ai_out~17.DB_MAX_OUTPUT_PORT_TYPE
ai_out[1] <= ai_out~16.DB_MAX_OUTPUT_PORT_TYPE
ai_out[2] <= ai_out~15.DB_MAX_OUTPUT_PORT_TYPE
ai_out[3] <= ai_out~14.DB_MAX_OUTPUT_PORT_TYPE
ai_out[4] <= ai_out~13.DB_MAX_OUTPUT_PORT_TYPE
ai_out[5] <= ai_out~12.DB_MAX_OUTPUT_PORT_TYPE
ai_out[6] <= ai_out~11.DB_MAX_OUTPUT_PORT_TYPE
ai_out[7] <= ai_out~10.DB_MAX_OUTPUT_PORT_TYPE
ai_out[8] <= ai_out~9.DB_MAX_OUTPUT_PORT_TYPE
ai_out[9] <= ai_out~8.DB_MAX_OUTPUT_PORT_TYPE
ai_out[10] <= ai_out~7.DB_MAX_OUTPUT_PORT_TYPE
ai_out[11] <= ai_out~6.DB_MAX_OUTPUT_PORT_TYPE
ai_out[12] <= ai_out~5.DB_MAX_OUTPUT_PORT_TYPE
ai_out[13] <= ai_out~4.DB_MAX_OUTPUT_PORT_TYPE
ai_out[14] <= ai_out~3.DB_MAX_OUTPUT_PORT_TYPE
ai_out[15] <= ai_out~2.DB_MAX_OUTPUT_PORT_TYPE
ai_out[16] <= ai_out~1.DB_MAX_OUTPUT_PORT_TYPE
ai_out[17] <= ai_out~0.DB_MAX_OUTPUT_PORT_TYPE
br_out[0] <= br_out~17.DB_MAX_OUTPUT_PORT_TYPE
br_out[1] <= br_out~16.DB_MAX_OUTPUT_PORT_TYPE
br_out[2] <= br_out~15.DB_MAX_OUTPUT_PORT_TYPE
br_out[3] <= br_out~14.DB_MAX_OUTPUT_PORT_TYPE
br_out[4] <= br_out~13.DB_MAX_OUTPUT_PORT_TYPE
br_out[5] <= br_out~12.DB_MAX_OUTPUT_PORT_TYPE
br_out[6] <= br_out~11.DB_MAX_OUTPUT_PORT_TYPE
br_out[7] <= br_out~10.DB_MAX_OUTPUT_PORT_TYPE
br_out[8] <= br_out~9.DB_MAX_OUTPUT_PORT_TYPE
br_out[9] <= br_out~8.DB_MAX_OUTPUT_PORT_TYPE
br_out[10] <= br_out~7.DB_MAX_OUTPUT_PORT_TYPE
br_out[11] <= br_out~6.DB_MAX_OUTPUT_PORT_TYPE
br_out[12] <= br_out~5.DB_MAX_OUTPUT_PORT_TYPE
br_out[13] <= br_out~4.DB_MAX_OUTPUT_PORT_TYPE
br_out[14] <= br_out~3.DB_MAX_OUTPUT_PORT_TYPE
br_out[15] <= br_out~2.DB_MAX_OUTPUT_PORT_TYPE
br_out[16] <= br_out~1.DB_MAX_OUTPUT_PORT_TYPE
br_out[17] <= br_out~0.DB_MAX_OUTPUT_PORT_TYPE
bi_out[0] <= bi_out~17.DB_MAX_OUTPUT_PORT_TYPE
bi_out[1] <= bi_out~16.DB_MAX_OUTPUT_PORT_TYPE
bi_out[2] <= bi_out~15.DB_MAX_OUTPUT_PORT_TYPE
bi_out[3] <= bi_out~14.DB_MAX_OUTPUT_PORT_TYPE
bi_out[4] <= bi_out~13.DB_MAX_OUTPUT_PORT_TYPE
bi_out[5] <= bi_out~12.DB_MAX_OUTPUT_PORT_TYPE
bi_out[6] <= bi_out~11.DB_MAX_OUTPUT_PORT_TYPE
bi_out[7] <= bi_out~10.DB_MAX_OUTPUT_PORT_TYPE
bi_out[8] <= bi_out~9.DB_MAX_OUTPUT_PORT_TYPE
bi_out[9] <= bi_out~8.DB_MAX_OUTPUT_PORT_TYPE
bi_out[10] <= bi_out~7.DB_MAX_OUTPUT_PORT_TYPE
bi_out[11] <= bi_out~6.DB_MAX_OUTPUT_PORT_TYPE
bi_out[12] <= bi_out~5.DB_MAX_OUTPUT_PORT_TYPE
bi_out[13] <= bi_out~4.DB_MAX_OUTPUT_PORT_TYPE
bi_out[14] <= bi_out~3.DB_MAX_OUTPUT_PORT_TYPE
bi_out[15] <= bi_out~2.DB_MAX_OUTPUT_PORT_TYPE
bi_out[16] <= bi_out~1.DB_MAX_OUTPUT_PORT_TYPE
bi_out[17] <= bi_out~0.DB_MAX_OUTPUT_PORT_TYPE
source_valid <= LessThan2.DB_MAX_OUTPUT_PORT_TYPE


|block|butterfly:inst48|ADD_17:add_real
clock => clock~0.IN1
dataa[0] => dataa[0]~16.IN1
dataa[1] => dataa[1]~15.IN1
dataa[2] => dataa[2]~14.IN1
dataa[3] => dataa[3]~13.IN1
dataa[4] => dataa[4]~12.IN1
dataa[5] => dataa[5]~11.IN1
dataa[6] => dataa[6]~10.IN1
dataa[7] => dataa[7]~9.IN1
dataa[8] => dataa[8]~8.IN1
dataa[9] => dataa[9]~7.IN1
dataa[10] => dataa[10]~6.IN1
dataa[11] => dataa[11]~5.IN1
dataa[12] => dataa[12]~4.IN1
dataa[13] => dataa[13]~3.IN1
dataa[14] => dataa[14]~2.IN1
dataa[15] => dataa[15]~1.IN1
dataa[16] => dataa[16]~0.IN1
datab[0] => datab[0]~16.IN1
datab[1] => datab[1]~15.IN1
datab[2] => datab[2]~14.IN1
datab[3] => datab[3]~13.IN1
datab[4] => datab[4]~12.IN1
datab[5] => datab[5]~11.IN1
datab[6] => datab[6]~10.IN1
datab[7] => datab[7]~9.IN1
datab[8] => datab[8]~8.IN1
datab[9] => datab[9]~7.IN1
datab[10] => datab[10]~6.IN1
datab[11] => datab[11]~5.IN1
datab[12] => datab[12]~4.IN1
datab[13] => datab[13]~3.IN1
datab[14] => datab[14]~2.IN1
datab[15] => datab[15]~1.IN1
datab[16] => datab[16]~0.IN1
result[0] <= lpm_add_sub:lpm_add_sub_component.result
result[1] <= lpm_add_sub:lpm_add_sub_component.result
result[2] <= lpm_add_sub:lpm_add_sub_component.result
result[3] <= lpm_add_sub:lpm_add_sub_component.result
result[4] <= lpm_add_sub:lpm_add_sub_component.result
result[5] <= lpm_add_sub:lpm_add_sub_component.result
result[6] <= lpm_add_sub:lpm_add_sub_component.result
result[7] <= lpm_add_sub:lpm_add_sub_component.result
result[8] <= lpm_add_sub:lpm_add_sub_component.result
result[9] <= lpm_add_sub:lpm_add_sub_component.result
result[10] <= lpm_add_sub:lpm_add_sub_component.result
result[11] <= lpm_add_sub:lpm_add_sub_component.result
result[12] <= lpm_add_sub:lpm_add_sub_component.result
result[13] <= lpm_add_sub:lpm_add_sub_component.result
result[14] <= lpm_add_sub:lpm_add_sub_component.result
result[15] <= lpm_add_sub:lpm_add_sub_component.result
result[16] <= lpm_add_sub:lpm_add_sub_component.result


|block|butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component
dataa[0] => add_sub_vmg:auto_generated.dataa[0]
dataa[1] => add_sub_vmg:auto_generated.dataa[1]
dataa[2] => add_sub_vmg:auto_generated.dataa[2]
dataa[3] => add_sub_vmg:auto_generated.dataa[3]
dataa[4] => add_sub_vmg:auto_generated.dataa[4]
dataa[5] => add_sub_vmg:auto_generated.dataa[5]
dataa[6] => add_sub_vmg:auto_generated.dataa[6]
dataa[7] => add_sub_vmg:auto_generated.dataa[7]
dataa[8] => add_sub_vmg:auto_generated.dataa[8]
dataa[9] => add_sub_vmg:auto_generated.dataa[9]
dataa[10] => add_sub_vmg:auto_generated.dataa[10]
dataa[11] => add_sub_vmg:auto_generated.dataa[11]
dataa[12] => add_sub_vmg:auto_generated.dataa[12]
dataa[13] => add_sub_vmg:auto_generated.dataa[13]
dataa[14] => add_sub_vmg:auto_generated.dataa[14]
dataa[15] => add_sub_vmg:auto_generated.dataa[15]
dataa[16] => add_sub_vmg:auto_generated.dataa[16]
datab[0] => add_sub_vmg:auto_generated.datab[0]
datab[1] => add_sub_vmg:auto_generated.datab[1]
datab[2] => add_sub_vmg:auto_generated.datab[2]
datab[3] => add_sub_vmg:auto_generated.datab[3]
datab[4] => add_sub_vmg:auto_generated.datab[4]
datab[5] => add_sub_vmg:auto_generated.datab[5]
datab[6] => add_sub_vmg:auto_generated.datab[6]
datab[7] => add_sub_vmg:auto_generated.datab[7]
datab[8] => add_sub_vmg:auto_generated.datab[8]
datab[9] => add_sub_vmg:auto_generated.datab[9]
datab[10] => add_sub_vmg:auto_generated.datab[10]
datab[11] => add_sub_vmg:auto_generated.datab[11]
datab[12] => add_sub_vmg:auto_generated.datab[12]
datab[13] => add_sub_vmg:auto_generated.datab[13]
datab[14] => add_sub_vmg:auto_generated.datab[14]
datab[15] => add_sub_vmg:auto_generated.datab[15]
datab[16] => add_sub_vmg:auto_generated.datab[16]
cin => ~NO_FANOUT~
add_sub => ~NO_FANOUT~
clock => add_sub_vmg:auto_generated.clock
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= add_sub_vmg:auto_generated.result[0]
result[1] <= add_sub_vmg:auto_generated.result[1]
result[2] <= add_sub_vmg:auto_generated.result[2]
result[3] <= add_sub_vmg:auto_generated.result[3]
result[4] <= add_sub_vmg:auto_generated.result[4]
result[5] <= add_sub_vmg:auto_generated.result[5]
result[6] <= add_sub_vmg:auto_generated.result[6]
result[7] <= add_sub_vmg:auto_generated.result[7]
result[8] <= add_sub_vmg:auto_generated.result[8]
result[9] <= add_sub_vmg:auto_generated.result[9]
result[10] <= add_sub_vmg:auto_generated.result[10]
result[11] <= add_sub_vmg:auto_generated.result[11]
result[12] <= add_sub_vmg:auto_generated.result[12]
result[13] <= add_sub_vmg:auto_generated.result[13]
result[14] <= add_sub_vmg:auto_generated.result[14]
result[15] <= add_sub_vmg:auto_generated.result[15]
result[16] <= add_sub_vmg:auto_generated.result[16]
cout <= <GND>
overflow <= <GND>


|block|butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component|add_sub_vmg:auto_generated
clock => pipeline_dffe[67].CLK
clock => pipeline_dffe[66].CLK
clock => pipeline_dffe[65].CLK
clock => pipeline_dffe[64].CLK
clock => pipeline_dffe[63].CLK
clock => pipeline_dffe[62].CLK
clock => pipeline_dffe[61].CLK
clock => pipeline_dffe[60].CLK
clock => pipeline_dffe[59].CLK
clock => pipeline_dffe[58].CLK
clock => pipeline_dffe[57].CLK
clock => pipeline_dffe[56].CLK
clock => pipeline_dffe[55].CLK
clock => pipeline_dffe[54].CLK
clock => pipeline_dffe[53].CLK
clock => pipeline_dffe[52].CLK
clock => pipeline_dffe[51].CLK
clock => pipeline_dffe[50].CLK
clock => pipeline_dffe[49].CLK
clock => pipeline_dffe[48].CLK
clock => pipeline_dffe[47].CLK
clock => pipeline_dffe[46].CLK
clock => pipeline_dffe[45].CLK
clock => pipeline_dffe[44].CLK
clock => pipeline_dffe[43].CLK
clock => pipeline_dffe[42].CLK
clock => pipeline_dffe[41].CLK
clock => pipeline_dffe[40].CLK
clock => pipeline_dffe[39].CLK
clock => pipeline_dffe[38].CLK
clock => pipeline_dffe[37].CLK
clock => pipeline_dffe[36].CLK
clock => pipeline_dffe[35].CLK
clock => pipeline_dffe[34].CLK
clock => pipeline_dffe[33].CLK
clock => pipeline_dffe[32].CLK
clock => pipeline_dffe[31].CLK
clock => pipeline_dffe[30].CLK
clock => pipeline_dffe[29].CLK
clock => pipeline_dffe[28].CLK
clock => pipeline_dffe[27].CLK
clock => pipeline_dffe[26].CLK
clock => pipeline_dffe[25].CLK
clock => pipeline_dffe[24].CLK
clock => pipeline_dffe[23].CLK
clock => pipeline_dffe[22].CLK
clock => pipeline_dffe[21].CLK
clock => pipeline_dffe[20].CLK
clock => pipeline_dffe[19].CLK
clock => pipeline_dffe[18].CLK
clock => pipeline_dffe[17].CLK
clock => pipeline_dffe[16].CLK
clock => pipeline_dffe[15].CLK
clock => pipeline_dffe[14].CLK
clock => pipeline_dffe[13].CLK
clock => pipeline_dffe[12].CLK
clock => pipeline_dffe[11].CLK
clock => pipeline_dffe[10].CLK
clock => pipeline_dffe[9].CLK
clock => pipeline_dffe[8].CLK
clock => pipeline_dffe[7].CLK
clock => pipeline_dffe[6].CLK
clock => pipeline_dffe[5].CLK
clock => pipeline_dffe[4].CLK
clock => pipeline_dffe[3].CLK
clock => pipeline_dffe[2].CLK
clock => pipeline_dffe[1].CLK
clock => pipeline_dffe[0].CLK
dataa[0] => op_1.IN32
dataa[1] => op_1.IN30
dataa[2] => op_1.IN28
dataa[3] => op_1.IN26
dataa[4] => op_1.IN24
dataa[5] => op_1.IN22
dataa[6] => op_1.IN20
dataa[7] => op_1.IN18
dataa[8] => op_1.IN16
dataa[9] => op_1.IN14
dataa[10] => op_1.IN12
dataa[11] => op_1.IN10
dataa[12] => op_1.IN8
dataa[13] => op_1.IN6
dataa[14] => op_1.IN4
dataa[15] => op_1.IN2
dataa[16] => op_1.IN0
datab[0] => op_1.IN33
datab[1] => op_1.IN31
datab[2] => op_1.IN29
datab[3] => op_1.IN27
datab[4] => op_1.IN25
datab[5] => op_1.IN23
datab[6] => op_1.IN21
datab[7] => op_1.IN19
datab[8] => op_1.IN17
datab[9] => op_1.IN15
datab[10] => op_1.IN13
datab[11] => op_1.IN11
datab[12] => op_1.IN9
datab[13] => op_1.IN7
datab[14] => op_1.IN5
datab[15] => op_1.IN3
datab[16] => op_1.IN1
result[0] <= pipeline_dffe[51].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= pipeline_dffe[52].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= pipeline_dffe[53].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= pipeline_dffe[54].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= pipeline_dffe[55].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= pipeline_dffe[56].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= pipeline_dffe[57].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= pipeline_dffe[58].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= pipeline_dffe[59].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= pipeline_dffe[60].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= pipeline_dffe[61].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= pipeline_dffe[62].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= pipeline_dffe[63].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= pipeline_dffe[64].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= pipeline_dffe[65].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= pipeline_dffe[66].DB_MAX_OUTPUT_PORT_TYPE
result[16] <= pipeline_dffe[67].DB_MAX_OUTPUT_PORT_TYPE


|block|butterfly:inst48|ADD_17:add_imag
clock => clock~0.IN1
dataa[0] => dataa[0]~16.IN1
dataa[1] => dataa[1]~15.IN1
dataa[2] => dataa[2]~14.IN1
dataa[3] => dataa[3]~13.IN1
dataa[4] => dataa[4]~12.IN1
dataa[5] => dataa[5]~11.IN1
dataa[6] => dataa[6]~10.IN1
dataa[7] => dataa[7]~9.IN1
dataa[8] => dataa[8]~8.IN1
dataa[9] => dataa[9]~7.IN1
dataa[10] => dataa[10]~6.IN1
dataa[11] => dataa[11]~5.IN1
dataa[12] => dataa[12]~4.IN1
dataa[13] => dataa[13]~3.IN1
dataa[14] => dataa[14]~2.IN1
dataa[15] => dataa[15]~1.IN1
dataa[16] => dataa[16]~0.IN1
datab[0] => datab[0]~16.IN1
datab[1] => datab[1]~15.IN1
datab[2] => datab[2]~14.IN1
datab[3] => datab[3]~13.IN1
datab[4] => datab[4]~12.IN1
datab[5] => datab[5]~11.IN1
datab[6] => datab[6]~10.IN1
datab[7] => datab[7]~9.IN1
datab[8] => datab[8]~8.IN1
datab[9] => datab[9]~7.IN1
datab[10] => datab[10]~6.IN1
datab[11] => datab[11]~5.IN1
datab[12] => datab[12]~4.IN1
datab[13] => datab[13]~3.IN1
datab[14] => datab[14]~2.IN1
datab[15] => datab[15]~1.IN1
datab[16] => datab[16]~0.IN1
result[0] <= lpm_add_sub:lpm_add_sub_component.result
result[1] <= lpm_add_sub:lpm_add_sub_component.result
result[2] <= lpm_add_sub:lpm_add_sub_component.result
result[3] <= lpm_add_sub:lpm_add_sub_component.result
result[4] <= lpm_add_sub:lpm_add_sub_component.result
result[5] <= lpm_add_sub:lpm_add_sub_component.result
result[6] <= lpm_add_sub:lpm_add_sub_component.result
result[7] <= lpm_add_sub:lpm_add_sub_component.result
result[8] <= lpm_add_sub:lpm_add_sub_component.result
result[9] <= lpm_add_sub:lpm_add_sub_component.result
result[10] <= lpm_add_sub:lpm_add_sub_component.result
result[11] <= lpm_add_sub:lpm_add_sub_component.result
result[12] <= lpm_add_sub:lpm_add_sub_component.result
result[13] <= lpm_add_sub:lpm_add_sub_component.result
result[14] <= lpm_add_sub:lpm_add_sub_component.result
result[15] <= lpm_add_sub:lpm_add_sub_component.result
result[16] <= lpm_add_sub:lpm_add_sub_component.result


|block|butterfly:inst48|ADD_17:add_imag|lpm_add_sub:lpm_add_sub_component
dataa[0] => add_sub_vmg:auto_generated.dataa[0]
dataa[1] => add_sub_vmg:auto_generated.dataa[1]
dataa[2] => add_sub_vmg:auto_generated.dataa[2]
dataa[3] => add_sub_vmg:auto_generated.dataa[3]
dataa[4] => add_sub_vmg:auto_generated.dataa[4]
dataa[5] => add_sub_vmg:auto_generated.dataa[5]
dataa[6] => add_sub_vmg:auto_generated.dataa[6]
dataa[7] => add_sub_vmg:auto_generated.dataa[7]
dataa[8] => add_sub_vmg:auto_generated.dataa[8]
dataa[9] => add_sub_vmg:auto_generated.dataa[9]
dataa[10] => add_sub_vmg:auto_generated.dataa[10]
dataa[11] => add_sub_vmg:auto_generated.dataa[11]
dataa[12] => add_sub_vmg:auto_generated.dataa[12]
dataa[13] => add_sub_vmg:auto_generated.dataa[13]
dataa[14] => add_sub_vmg:auto_generated.dataa[14]
dataa[15] => add_sub_vmg:auto_generated.dataa[15]
dataa[16] => add_sub_vmg:auto_generated.dataa[16]
datab[0] => add_sub_vmg:auto_generated.datab[0]
datab[1] => add_sub_vmg:auto_generated.datab[1]
datab[2] => add_sub_vmg:auto_generated.datab[2]
datab[3] => add_sub_vmg:auto_generated.datab[3]
datab[4] => add_sub_vmg:auto_generated.datab[4]
datab[5] => add_sub_vmg:auto_generated.datab[5]
datab[6] => add_sub_vmg:auto_generated.datab[6]
datab[7] => add_sub_vmg:auto_generated.datab[7]
datab[8] => add_sub_vmg:auto_generated.datab[8]
datab[9] => add_sub_vmg:auto_generated.datab[9]
datab[10] => add_sub_vmg:auto_generated.datab[10]
datab[11] => add_sub_vmg:auto_generated.datab[11]
datab[12] => add_sub_vmg:auto_generated.datab[12]
datab[13] => add_sub_vmg:auto_generated.datab[13]
datab[14] => add_sub_vmg:auto_generated.datab[14]
datab[15] => add_sub_vmg:auto_generated.datab[15]
datab[16] => add_sub_vmg:auto_generated.datab[16]
cin => ~NO_FANOUT~
add_sub => ~NO_FANOUT~
clock => add_sub_vmg:auto_generated.clock
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= add_sub_vmg:auto_generated.result[0]
result[1] <= add_sub_vmg:auto_generated.result[1]
result[2] <= add_sub_vmg:auto_generated.result[2]
result[3] <= add_sub_vmg:auto_generated.result[3]
result[4] <= add_sub_vmg:auto_generated.result[4]
result[5] <= add_sub_vmg:auto_generated.result[5]
result[6] <= add_sub_vmg:auto_generated.result[6]
result[7] <= add_sub_vmg:auto_generated.result[7]
result[8] <= add_sub_vmg:auto_generated.result[8]
result[9] <= add_sub_vmg:auto_generated.result[9]
result[10] <= add_sub_vmg:auto_generated.result[10]
result[11] <= add_sub_vmg:auto_generated.result[11]
result[12] <= add_sub_vmg:auto_generated.result[12]
result[13] <= add_sub_vmg:auto_generated.result[13]
result[14] <= add_sub_vmg:auto_generated.result[14]
result[15] <= add_sub_vmg:auto_generated.result[15]
result[16] <= add_sub_vmg:auto_generated.result[16]
cout <= <GND>
overflow <= <GND>


|block|butterfly:inst48|ADD_17:add_imag|lpm_add_sub:lpm_add_sub_component|add_sub_vmg:auto_generated
clock => pipeline_dffe[67].CLK
clock => pipeline_dffe[66].CLK
clock => pipeline_dffe[65].CLK
clock => pipeline_dffe[64].CLK
clock => pipeline_dffe[63].CLK
clock => pipeline_dffe[62].CLK
clock => pipeline_dffe[61].CLK
clock => pipeline_dffe[60].CLK
clock => pipeline_dffe[59].CLK
clock => pipeline_dffe[58].CLK
clock => pipeline_dffe[57].CLK
clock => pipeline_dffe[56].CLK
clock => pipeline_dffe[55].CLK
clock => pipeline_dffe[54].CLK
clock => pipeline_dffe[53].CLK
clock => pipeline_dffe[52].CLK
clock => pipeline_dffe[51].CLK
clock => pipeline_dffe[50].CLK
clock => pipeline_dffe[49].CLK
clock => pipeline_dffe[48].CLK
clock => pipeline_dffe[47].CLK
clock => pipeline_dffe[46].CLK
clock => pipeline_dffe[45].CLK
clock => pipeline_dffe[44].CLK
clock => pipeline_dffe[43].CLK
clock => pipeline_dffe[42].CLK
clock => pipeline_dffe[41].CLK
clock => pipeline_dffe[40].CLK
clock => pipeline_dffe[39].CLK
clock => pipeline_dffe[38].CLK
clock => pipeline_dffe[37].CLK
clock => pipeline_dffe[36].CLK
clock => pipeline_dffe[35].CLK
clock => pipeline_dffe[34].CLK
clock => pipeline_dffe[33].CLK
clock => pipeline_dffe[32].CLK
clock => pipeline_dffe[31].CLK
clock => pipeline_dffe[30].CLK
clock => pipeline_dffe[29].CLK
clock => pipeline_dffe[28].CLK
clock => pipeline_dffe[27].CLK
clock => pipeline_dffe[26].CLK
clock => pipeline_dffe[25].CLK
clock => pipeline_dffe[24].CLK
clock => pipeline_dffe[23].CLK
clock => pipeline_dffe[22].CLK
clock => pipeline_dffe[21].CLK
clock => pipeline_dffe[20].CLK
clock => pipeline_dffe[19].CLK
clock => pipeline_dffe[18].CLK
clock => pipeline_dffe[17].CLK
clock => pipeline_dffe[16].CLK
clock => pipeline_dffe[15].CLK
clock => pipeline_dffe[14].CLK
clock => pipeline_dffe[13].CLK
clock => pipeline_dffe[12].CLK
clock => pipeline_dffe[11].CLK
clock => pipeline_dffe[10].CLK
clock => pipeline_dffe[9].CLK
clock => pipeline_dffe[8].CLK
clock => pipeline_dffe[7].CLK
clock => pipeline_dffe[6].CLK
clock => pipeline_dffe[5].CLK
clock => pipeline_dffe[4].CLK
clock => pipeline_dffe[3].CLK
clock => pipeline_dffe[2].CLK
clock => pipeline_dffe[1].CLK
clock => pipeline_dffe[0].CLK
dataa[0] => op_1.IN32
dataa[1] => op_1.IN30
dataa[2] => op_1.IN28
dataa[3] => op_1.IN26
dataa[4] => op_1.IN24
dataa[5] => op_1.IN22
dataa[6] => op_1.IN20
dataa[7] => op_1.IN18
dataa[8] => op_1.IN16
dataa[9] => op_1.IN14
dataa[10] => op_1.IN12
dataa[11] => op_1.IN10
dataa[12] => op_1.IN8
dataa[13] => op_1.IN6
dataa[14] => op_1.IN4
dataa[15] => op_1.IN2
dataa[16] => op_1.IN0
datab[0] => op_1.IN33
datab[1] => op_1.IN31
datab[2] => op_1.IN29
datab[3] => op_1.IN27
datab[4] => op_1.IN25
datab[5] => op_1.IN23
datab[6] => op_1.IN21
datab[7] => op_1.IN19
datab[8] => op_1.IN17
datab[9] => op_1.IN15
datab[10] => op_1.IN13
datab[11] => op_1.IN11
datab[12] => op_1.IN9
datab[13] => op_1.IN7
datab[14] => op_1.IN5
datab[15] => op_1.IN3
datab[16] => op_1.IN1
result[0] <= pipeline_dffe[51].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= pipeline_dffe[52].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= pipeline_dffe[53].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= pipeline_dffe[54].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= pipeline_dffe[55].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= pipeline_dffe[56].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= pipeline_dffe[57].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= pipeline_dffe[58].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= pipeline_dffe[59].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= pipeline_dffe[60].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= pipeline_dffe[61].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= pipeline_dffe[62].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= pipeline_dffe[63].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= pipeline_dffe[64].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= pipeline_dffe[65].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= pipeline_dffe[66].DB_MAX_OUTPUT_PORT_TYPE
result[16] <= pipeline_dffe[67].DB_MAX_OUTPUT_PORT_TYPE


|block|butterfly:inst48|SUB_17:sub_real
dataa[0] => dataa[0]~16.IN1
dataa[1] => dataa[1]~15.IN1
dataa[2] => dataa[2]~14.IN1
dataa[3] => dataa[3]~13.IN1
dataa[4] => dataa[4]~12.IN1
dataa[5] => dataa[5]~11.IN1
dataa[6] => dataa[6]~10.IN1
dataa[7] => dataa[7]~9.IN1
dataa[8] => dataa[8]~8.IN1
dataa[9] => dataa[9]~7.IN1
dataa[10] => dataa[10]~6.IN1
dataa[11] => dataa[11]~5.IN1
dataa[12] => dataa[12]~4.IN1
dataa[13] => dataa[13]~3.IN1
dataa[14] => dataa[14]~2.IN1
dataa[15] => dataa[15]~1.IN1
dataa[16] => dataa[16]~0.IN1
datab[0] => datab[0]~16.IN1
datab[1] => datab[1]~15.IN1
datab[2] => datab[2]~14.IN1
datab[3] => datab[3]~13.IN1
datab[4] => datab[4]~12.IN1
datab[5] => datab[5]~11.IN1
datab[6] => datab[6]~10.IN1
datab[7] => datab[7]~9.IN1
datab[8] => datab[8]~8.IN1
datab[9] => datab[9]~7.IN1
datab[10] => datab[10]~6.IN1
datab[11] => datab[11]~5.IN1
datab[12] => datab[12]~4.IN1
datab[13] => datab[13]~3.IN1
datab[14] => datab[14]~2.IN1
datab[15] => datab[15]~1.IN1
datab[16] => datab[16]~0.IN1
result[0] <= lpm_add_sub:lpm_add_sub_component.result
result[1] <= lpm_add_sub:lpm_add_sub_component.result
result[2] <= lpm_add_sub:lpm_add_sub_component.result
result[3] <= lpm_add_sub:lpm_add_sub_component.result
result[4] <= lpm_add_sub:lpm_add_sub_component.result
result[5] <= lpm_add_sub:lpm_add_sub_component.result
result[6] <= lpm_add_sub:lpm_add_sub_component.result
result[7] <= lpm_add_sub:lpm_add_sub_component.result
result[8] <= lpm_add_sub:lpm_add_sub_component.result
result[9] <= lpm_add_sub:lpm_add_sub_component.result
result[10] <= lpm_add_sub:lpm_add_sub_component.result
result[11] <= lpm_add_sub:lpm_add_sub_component.result
result[12] <= lpm_add_sub:lpm_add_sub_component.result
result[13] <= lpm_add_sub:lpm_add_sub_component.result
result[14] <= lpm_add_sub:lpm_add_sub_component.result
result[15] <= lpm_add_sub:lpm_add_sub_component.result
result[16] <= lpm_add_sub:lpm_add_sub_component.result


|block|butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component
dataa[0] => add_sub_4qe:auto_generated.dataa[0]
dataa[1] => add_sub_4qe:auto_generated.dataa[1]
dataa[2] => add_sub_4qe:auto_generated.dataa[2]
dataa[3] => add_sub_4qe:auto_generated.dataa[3]
dataa[4] => add_sub_4qe:auto_generated.dataa[4]
dataa[5] => add_sub_4qe:auto_generated.dataa[5]
dataa[6] => add_sub_4qe:auto_generated.dataa[6]
dataa[7] => add_sub_4qe:auto_generated.dataa[7]
dataa[8] => add_sub_4qe:auto_generated.dataa[8]
dataa[9] => add_sub_4qe:auto_generated.dataa[9]
dataa[10] => add_sub_4qe:auto_generated.dataa[10]
dataa[11] => add_sub_4qe:auto_generated.dataa[11]
dataa[12] => add_sub_4qe:auto_generated.dataa[12]
dataa[13] => add_sub_4qe:auto_generated.dataa[13]
dataa[14] => add_sub_4qe:auto_generated.dataa[14]
dataa[15] => add_sub_4qe:auto_generated.dataa[15]
dataa[16] => add_sub_4qe:auto_generated.dataa[16]
datab[0] => add_sub_4qe:auto_generated.datab[0]
datab[1] => add_sub_4qe:auto_generated.datab[1]
datab[2] => add_sub_4qe:auto_generated.datab[2]
datab[3] => add_sub_4qe:auto_generated.datab[3]
datab[4] => add_sub_4qe:auto_generated.datab[4]
datab[5] => add_sub_4qe:auto_generated.datab[5]
datab[6] => add_sub_4qe:auto_generated.datab[6]
datab[7] => add_sub_4qe:auto_generated.datab[7]
datab[8] => add_sub_4qe:auto_generated.datab[8]
datab[9] => add_sub_4qe:auto_generated.datab[9]
datab[10] => add_sub_4qe:auto_generated.datab[10]
datab[11] => add_sub_4qe:auto_generated.datab[11]
datab[12] => add_sub_4qe:auto_generated.datab[12]
datab[13] => add_sub_4qe:auto_generated.datab[13]
datab[14] => add_sub_4qe:auto_generated.datab[14]
datab[15] => add_sub_4qe:auto_generated.datab[15]
datab[16] => add_sub_4qe:auto_generated.datab[16]
cin => ~NO_FANOUT~
add_sub => ~NO_FANOUT~
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= add_sub_4qe:auto_generated.result[0]
result[1] <= add_sub_4qe:auto_generated.result[1]
result[2] <= add_sub_4qe:auto_generated.result[2]
result[3] <= add_sub_4qe:auto_generated.result[3]
result[4] <= add_sub_4qe:auto_generated.result[4]
result[5] <= add_sub_4qe:auto_generated.result[5]
result[6] <= add_sub_4qe:auto_generated.result[6]
result[7] <= add_sub_4qe:auto_generated.result[7]
result[8] <= add_sub_4qe:auto_generated.result[8]
result[9] <= add_sub_4qe:auto_generated.result[9]
result[10] <= add_sub_4qe:auto_generated.result[10]
result[11] <= add_sub_4qe:auto_generated.result[11]
result[12] <= add_sub_4qe:auto_generated.result[12]
result[13] <= add_sub_4qe:auto_generated.result[13]
result[14] <= add_sub_4qe:auto_generated.result[14]
result[15] <= add_sub_4qe:auto_generated.result[15]
result[16] <= add_sub_4qe:auto_generated.result[16]
cout <= <GND>
overflow <= <GND>


|block|butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated
dataa[0] => op_1.IN33
dataa[1] => op_1.IN31
dataa[2] => op_1.IN29
dataa[3] => op_1.IN27
dataa[4] => op_1.IN25
dataa[5] => op_1.IN23
dataa[6] => op_1.IN21
dataa[7] => op_1.IN19
dataa[8] => op_1.IN17
dataa[9] => op_1.IN15
dataa[10] => op_1.IN13
dataa[11] => op_1.IN11
dataa[12] => op_1.IN9
dataa[13] => op_1.IN7
dataa[14] => op_1.IN5
dataa[15] => op_1.IN3
dataa[16] => op_1.IN1
datab[0] => op_1.IN34
datab[1] => op_1.IN32
datab[2] => op_1.IN30
datab[3] => op_1.IN28
datab[4] => op_1.IN26
datab[5] => op_1.IN24
datab[6] => op_1.IN22
datab[7] => op_1.IN20
datab[8] => op_1.IN18
datab[9] => op_1.IN16
datab[10] => op_1.IN14
datab[11] => op_1.IN12
datab[12] => op_1.IN10
datab[13] => op_1.IN8
datab[14] => op_1.IN6
datab[15] => op_1.IN4
datab[16] => op_1.IN2
result[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[9] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[10] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[11] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[12] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[13] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[14] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[15] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[16] <= op_1.DB_MAX_OUTPUT_PORT_TYPE


|block|butterfly:inst48|SUB_17:sub_imag
dataa[0] => dataa[0]~16.IN1
dataa[1] => dataa[1]~15.IN1
dataa[2] => dataa[2]~14.IN1
dataa[3] => dataa[3]~13.IN1
dataa[4] => dataa[4]~12.IN1
dataa[5] => dataa[5]~11.IN1
dataa[6] => dataa[6]~10.IN1
dataa[7] => dataa[7]~9.IN1
dataa[8] => dataa[8]~8.IN1
dataa[9] => dataa[9]~7.IN1
dataa[10] => dataa[10]~6.IN1
dataa[11] => dataa[11]~5.IN1
dataa[12] => dataa[12]~4.IN1
dataa[13] => dataa[13]~3.IN1
dataa[14] => dataa[14]~2.IN1
dataa[15] => dataa[15]~1.IN1
dataa[16] => dataa[16]~0.IN1
datab[0] => datab[0]~16.IN1
datab[1] => datab[1]~15.IN1
datab[2] => datab[2]~14.IN1
datab[3] => datab[3]~13.IN1
datab[4] => datab[4]~12.IN1
datab[5] => datab[5]~11.IN1
datab[6] => datab[6]~10.IN1
datab[7] => datab[7]~9.IN1
datab[8] => datab[8]~8.IN1
datab[9] => datab[9]~7.IN1
datab[10] => datab[10]~6.IN1
datab[11] => datab[11]~5.IN1
datab[12] => datab[12]~4.IN1
datab[13] => datab[13]~3.IN1
datab[14] => datab[14]~2.IN1
datab[15] => datab[15]~1.IN1
datab[16] => datab[16]~0.IN1
result[0] <= lpm_add_sub:lpm_add_sub_component.result
result[1] <= lpm_add_sub:lpm_add_sub_component.result
result[2] <= lpm_add_sub:lpm_add_sub_component.result
result[3] <= lpm_add_sub:lpm_add_sub_component.result
result[4] <= lpm_add_sub:lpm_add_sub_component.result
result[5] <= lpm_add_sub:lpm_add_sub_component.result
result[6] <= lpm_add_sub:lpm_add_sub_component.result
result[7] <= lpm_add_sub:lpm_add_sub_component.result
result[8] <= lpm_add_sub:lpm_add_sub_component.result
result[9] <= lpm_add_sub:lpm_add_sub_component.result
result[10] <= lpm_add_sub:lpm_add_sub_component.result
result[11] <= lpm_add_sub:lpm_add_sub_component.result
result[12] <= lpm_add_sub:lpm_add_sub_component.result
result[13] <= lpm_add_sub:lpm_add_sub_component.result
result[14] <= lpm_add_sub:lpm_add_sub_component.result
result[15] <= lpm_add_sub:lpm_add_sub_component.result
result[16] <= lpm_add_sub:lpm_add_sub_component.result


|block|butterfly:inst48|SUB_17:sub_imag|lpm_add_sub:lpm_add_sub_component
dataa[0] => add_sub_4qe:auto_generated.dataa[0]
dataa[1] => add_sub_4qe:auto_generated.dataa[1]
dataa[2] => add_sub_4qe:auto_generated.dataa[2]
dataa[3] => add_sub_4qe:auto_generated.dataa[3]
dataa[4] => add_sub_4qe:auto_generated.dataa[4]
dataa[5] => add_sub_4qe:auto_generated.dataa[5]
dataa[6] => add_sub_4qe:auto_generated.dataa[6]
dataa[7] => add_sub_4qe:auto_generated.dataa[7]
dataa[8] => add_sub_4qe:auto_generated.dataa[8]
dataa[9] => add_sub_4qe:auto_generated.dataa[9]
dataa[10] => add_sub_4qe:auto_generated.dataa[10]
dataa[11] => add_sub_4qe:auto_generated.dataa[11]
dataa[12] => add_sub_4qe:auto_generated.dataa[12]
dataa[13] => add_sub_4qe:auto_generated.dataa[13]
dataa[14] => add_sub_4qe:auto_generated.dataa[14]
dataa[15] => add_sub_4qe:auto_generated.dataa[15]
dataa[16] => add_sub_4qe:auto_generated.dataa[16]
datab[0] => add_sub_4qe:auto_generated.datab[0]
datab[1] => add_sub_4qe:auto_generated.datab[1]
datab[2] => add_sub_4qe:auto_generated.datab[2]
datab[3] => add_sub_4qe:auto_generated.datab[3]
datab[4] => add_sub_4qe:auto_generated.datab[4]
datab[5] => add_sub_4qe:auto_generated.datab[5]
datab[6] => add_sub_4qe:auto_generated.datab[6]
datab[7] => add_sub_4qe:auto_generated.datab[7]
datab[8] => add_sub_4qe:auto_generated.datab[8]
datab[9] => add_sub_4qe:auto_generated.datab[9]
datab[10] => add_sub_4qe:auto_generated.datab[10]
datab[11] => add_sub_4qe:auto_generated.datab[11]
datab[12] => add_sub_4qe:auto_generated.datab[12]
datab[13] => add_sub_4qe:auto_generated.datab[13]
datab[14] => add_sub_4qe:auto_generated.datab[14]
datab[15] => add_sub_4qe:auto_generated.datab[15]
datab[16] => add_sub_4qe:auto_generated.datab[16]
cin => ~NO_FANOUT~
add_sub => ~NO_FANOUT~
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= add_sub_4qe:auto_generated.result[0]
result[1] <= add_sub_4qe:auto_generated.result[1]
result[2] <= add_sub_4qe:auto_generated.result[2]
result[3] <= add_sub_4qe:auto_generated.result[3]
result[4] <= add_sub_4qe:auto_generated.result[4]
result[5] <= add_sub_4qe:auto_generated.result[5]
result[6] <= add_sub_4qe:auto_generated.result[6]
result[7] <= add_sub_4qe:auto_generated.result[7]
result[8] <= add_sub_4qe:auto_generated.result[8]
result[9] <= add_sub_4qe:auto_generated.result[9]
result[10] <= add_sub_4qe:auto_generated.result[10]
result[11] <= add_sub_4qe:auto_generated.result[11]
result[12] <= add_sub_4qe:auto_generated.result[12]
result[13] <= add_sub_4qe:auto_generated.result[13]
result[14] <= add_sub_4qe:auto_generated.result[14]
result[15] <= add_sub_4qe:auto_generated.result[15]
result[16] <= add_sub_4qe:auto_generated.result[16]
cout <= <GND>
overflow <= <GND>


|block|butterfly:inst48|SUB_17:sub_imag|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated
dataa[0] => op_1.IN33
dataa[1] => op_1.IN31
dataa[2] => op_1.IN29
dataa[3] => op_1.IN27
dataa[4] => op_1.IN25
dataa[5] => op_1.IN23
dataa[6] => op_1.IN21
dataa[7] => op_1.IN19
dataa[8] => op_1.IN17
dataa[9] => op_1.IN15
dataa[10] => op_1.IN13
dataa[11] => op_1.IN11
dataa[12] => op_1.IN9
dataa[13] => op_1.IN7
dataa[14] => op_1.IN5
dataa[15] => op_1.IN3
dataa[16] => op_1.IN1
datab[0] => op_1.IN34
datab[1] => op_1.IN32
datab[2] => op_1.IN30
datab[3] => op_1.IN28
datab[4] => op_1.IN26
datab[5] => op_1.IN24
datab[6] => op_1.IN22
datab[7] => op_1.IN20
datab[8] => op_1.IN18
datab[9] => op_1.IN16
datab[10] => op_1.IN14
datab[11] => op_1.IN12
datab[12] => op_1.IN10
datab[13] => op_1.IN8
datab[14] => op_1.IN6
datab[15] => op_1.IN4
datab[16] => op_1.IN2
result[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[9] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[10] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[11] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[12] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[13] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[14] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[15] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
result[16] <= op_1.DB_MAX_OUTPUT_PORT_TYPE


|block|butterfly:inst48|complex_mult:mult
clock => clock~0.IN1
dataa_imag[0] => dataa_imag[0]~16.IN1
dataa_imag[1] => dataa_imag[1]~15.IN1
dataa_imag[2] => dataa_imag[2]~14.IN1
dataa_imag[3] => dataa_imag[3]~13.IN1
dataa_imag[4] => dataa_imag[4]~12.IN1
dataa_imag[5] => dataa_imag[5]~11.IN1
dataa_imag[6] => dataa_imag[6]~10.IN1
dataa_imag[7] => dataa_imag[7]~9.IN1
dataa_imag[8] => dataa_imag[8]~8.IN1
dataa_imag[9] => dataa_imag[9]~7.IN1
dataa_imag[10] => dataa_imag[10]~6.IN1
dataa_imag[11] => dataa_imag[11]~5.IN1
dataa_imag[12] => dataa_imag[12]~4.IN1
dataa_imag[13] => dataa_imag[13]~3.IN1
dataa_imag[14] => dataa_imag[14]~2.IN1
dataa_imag[15] => dataa_imag[15]~1.IN1
dataa_imag[16] => dataa_imag[16]~0.IN1
dataa_real[0] => dataa_real[0]~16.IN1
dataa_real[1] => dataa_real[1]~15.IN1
dataa_real[2] => dataa_real[2]~14.IN1
dataa_real[3] => dataa_real[3]~13.IN1
dataa_real[4] => dataa_real[4]~12.IN1
dataa_real[5] => dataa_real[5]~11.IN1
dataa_real[6] => dataa_real[6]~10.IN1
dataa_real[7] => dataa_real[7]~9.IN1
dataa_real[8] => dataa_real[8]~8.IN1
dataa_real[9] => dataa_real[9]~7.IN1
dataa_real[10] => dataa_real[10]~6.IN1
dataa_real[11] => dataa_real[11]~5.IN1
dataa_real[12] => dataa_real[12]~4.IN1
dataa_real[13] => dataa_real[13]~3.IN1
dataa_real[14] => dataa_real[14]~2.IN1
dataa_real[15] => dataa_real[15]~1.IN1
dataa_real[16] => dataa_real[16]~0.IN1
datab_imag[0] => datab_imag[0]~16.IN1
datab_imag[1] => datab_imag[1]~15.IN1
datab_imag[2] => datab_imag[2]~14.IN1
datab_imag[3] => datab_imag[3]~13.IN1
datab_imag[4] => datab_imag[4]~12.IN1
datab_imag[5] => datab_imag[5]~11.IN1
datab_imag[6] => datab_imag[6]~10.IN1
datab_imag[7] => datab_imag[7]~9.IN1
datab_imag[8] => datab_imag[8]~8.IN1
datab_imag[9] => datab_imag[9]~7.IN1
datab_imag[10] => datab_imag[10]~6.IN1
datab_imag[11] => datab_imag[11]~5.IN1
datab_imag[12] => datab_imag[12]~4.IN1
datab_imag[13] => datab_imag[13]~3.IN1
datab_imag[14] => datab_imag[14]~2.IN1
datab_imag[15] => datab_imag[15]~1.IN1
datab_imag[16] => datab_imag[16]~0.IN1
datab_real[0] => datab_real[0]~16.IN1
datab_real[1] => datab_real[1]~15.IN1
datab_real[2] => datab_real[2]~14.IN1
datab_real[3] => datab_real[3]~13.IN1
datab_real[4] => datab_real[4]~12.IN1
datab_real[5] => datab_real[5]~11.IN1
datab_real[6] => datab_real[6]~10.IN1
datab_real[7] => datab_real[7]~9.IN1
datab_real[8] => datab_real[8]~8.IN1
datab_real[9] => datab_real[9]~7.IN1
datab_real[10] => datab_real[10]~6.IN1
datab_real[11] => datab_real[11]~5.IN1
datab_real[12] => datab_real[12]~4.IN1
datab_real[13] => datab_real[13]~3.IN1
datab_real[14] => datab_real[14]~2.IN1
datab_real[15] => datab_real[15]~1.IN1
datab_real[16] => datab_real[16]~0.IN1
result_imag[0] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[1] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[2] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[3] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[4] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[5] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[6] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[7] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[8] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[9] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[10] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[11] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[12] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[13] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[14] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[15] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[16] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[17] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[18] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[19] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[20] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[21] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[22] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[23] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[24] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[25] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[26] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[27] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[28] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[29] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[30] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[31] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[32] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_imag[33] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_imag
result_real[0] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[1] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[2] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[3] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[4] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[5] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[6] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[7] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[8] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[9] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[10] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[11] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[12] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[13] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[14] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[15] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[16] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[17] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[18] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[19] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[20] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[21] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[22] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[23] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[24] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[25] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[26] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[27] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[28] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[29] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[30] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[31] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[32] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real
result_real[33] <= complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component.result_real


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component
clock => clock~0.IN9
dataa_imag[0] => inputa_imag[0].IN2
dataa_imag[1] => inputa_imag[1].IN2
dataa_imag[2] => inputa_imag[2].IN2
dataa_imag[3] => inputa_imag[3].IN2
dataa_imag[4] => inputa_imag[4].IN2
dataa_imag[5] => inputa_imag[5].IN2
dataa_imag[6] => inputa_imag[6].IN2
dataa_imag[7] => inputa_imag[7].IN2
dataa_imag[8] => inputa_imag[8].IN2
dataa_imag[9] => inputa_imag[9].IN2
dataa_imag[10] => inputa_imag[10].IN2
dataa_imag[11] => inputa_imag[11].IN2
dataa_imag[12] => inputa_imag[12].IN2
dataa_imag[13] => inputa_imag[13].IN2
dataa_imag[14] => inputa_imag[14].IN2
dataa_imag[15] => inputa_imag[15].IN2
dataa_imag[16] => inputa_imag[16].IN3
dataa_real[0] => inputa_real[0].IN2
dataa_real[1] => inputa_real[1].IN2
dataa_real[2] => inputa_real[2].IN2
dataa_real[3] => inputa_real[3].IN2
dataa_real[4] => inputa_real[4].IN2
dataa_real[5] => inputa_real[5].IN2
dataa_real[6] => inputa_real[6].IN2
dataa_real[7] => inputa_real[7].IN2
dataa_real[8] => inputa_real[8].IN2
dataa_real[9] => inputa_real[9].IN2
dataa_real[10] => inputa_real[10].IN2
dataa_real[11] => inputa_real[11].IN2
dataa_real[12] => inputa_real[12].IN2
dataa_real[13] => inputa_real[13].IN2
dataa_real[14] => inputa_real[14].IN2
dataa_real[15] => inputa_real[15].IN2
dataa_real[16] => inputa_real[16].IN3
datab_imag[0] => inputb_imag[0].IN3
datab_imag[1] => inputb_imag[1].IN3
datab_imag[2] => inputb_imag[2].IN3
datab_imag[3] => inputb_imag[3].IN3
datab_imag[4] => inputb_imag[4].IN3
datab_imag[5] => inputb_imag[5].IN3
datab_imag[6] => inputb_imag[6].IN3
datab_imag[7] => inputb_imag[7].IN3
datab_imag[8] => inputb_imag[8].IN3
datab_imag[9] => inputb_imag[9].IN3
datab_imag[10] => inputb_imag[10].IN3
datab_imag[11] => inputb_imag[11].IN3
datab_imag[12] => inputb_imag[12].IN3
datab_imag[13] => inputb_imag[13].IN3
datab_imag[14] => inputb_imag[14].IN3
datab_imag[15] => inputb_imag[15].IN3
datab_imag[16] => inputb_imag[16].IN4
datab_real[0] => inputb_real[0].IN3
datab_real[1] => inputb_real[1].IN3
datab_real[2] => inputb_real[2].IN3
datab_real[3] => inputb_real[3].IN3
datab_real[4] => inputb_real[4].IN3
datab_real[5] => inputb_real[5].IN3
datab_real[6] => inputb_real[6].IN3
datab_real[7] => inputb_real[7].IN3
datab_real[8] => inputb_real[8].IN3
datab_real[9] => inputb_real[9].IN3
datab_real[10] => inputb_real[10].IN3
datab_real[11] => inputb_real[11].IN3
datab_real[12] => inputb_real[12].IN3
datab_real[13] => inputb_real[13].IN3
datab_real[14] => inputb_real[14].IN3
datab_real[15] => inputb_real[15].IN3
datab_real[16] => inputb_real[16].IN4
result_imag[0] <= lpm_add_sub:adder2.result
result_imag[1] <= lpm_add_sub:adder2.result
result_imag[2] <= lpm_add_sub:adder2.result
result_imag[3] <= lpm_add_sub:adder2.result
result_imag[4] <= lpm_add_sub:adder2.result
result_imag[5] <= lpm_add_sub:adder2.result
result_imag[6] <= lpm_add_sub:adder2.result
result_imag[7] <= lpm_add_sub:adder2.result
result_imag[8] <= lpm_add_sub:adder2.result
result_imag[9] <= lpm_add_sub:adder2.result
result_imag[10] <= lpm_add_sub:adder2.result
result_imag[11] <= lpm_add_sub:adder2.result
result_imag[12] <= lpm_add_sub:adder2.result
result_imag[13] <= lpm_add_sub:adder2.result
result_imag[14] <= lpm_add_sub:adder2.result
result_imag[15] <= lpm_add_sub:adder2.result
result_imag[16] <= lpm_add_sub:adder2.result
result_imag[17] <= lpm_add_sub:adder2.result
result_imag[18] <= lpm_add_sub:adder2.result
result_imag[19] <= lpm_add_sub:adder2.result
result_imag[20] <= lpm_add_sub:adder2.result
result_imag[21] <= lpm_add_sub:adder2.result
result_imag[22] <= lpm_add_sub:adder2.result
result_imag[23] <= lpm_add_sub:adder2.result
result_imag[24] <= lpm_add_sub:adder2.result
result_imag[25] <= lpm_add_sub:adder2.result
result_imag[26] <= lpm_add_sub:adder2.result
result_imag[27] <= lpm_add_sub:adder2.result
result_imag[28] <= lpm_add_sub:adder2.result
result_imag[29] <= lpm_add_sub:adder2.result
result_imag[30] <= lpm_add_sub:adder2.result
result_imag[31] <= lpm_add_sub:adder2.result
result_imag[32] <= lpm_add_sub:adder2.result
result_imag[33] <= lpm_add_sub:adder2.result
result_real[0] <= lpm_add_sub:add_sub7.result
result_real[1] <= lpm_add_sub:add_sub7.result
result_real[2] <= lpm_add_sub:add_sub7.result
result_real[3] <= lpm_add_sub:add_sub7.result
result_real[4] <= lpm_add_sub:add_sub7.result
result_real[5] <= lpm_add_sub:add_sub7.result
result_real[6] <= lpm_add_sub:add_sub7.result
result_real[7] <= lpm_add_sub:add_sub7.result
result_real[8] <= lpm_add_sub:add_sub7.result
result_real[9] <= lpm_add_sub:add_sub7.result
result_real[10] <= lpm_add_sub:add_sub7.result
result_real[11] <= lpm_add_sub:add_sub7.result
result_real[12] <= lpm_add_sub:add_sub7.result
result_real[13] <= lpm_add_sub:add_sub7.result
result_real[14] <= lpm_add_sub:add_sub7.result
result_real[15] <= lpm_add_sub:add_sub7.result
result_real[16] <= lpm_add_sub:add_sub7.result
result_real[17] <= lpm_add_sub:add_sub7.result
result_real[18] <= lpm_add_sub:add_sub7.result
result_real[19] <= lpm_add_sub:add_sub7.result
result_real[20] <= lpm_add_sub:add_sub7.result
result_real[21] <= lpm_add_sub:add_sub7.result
result_real[22] <= lpm_add_sub:add_sub7.result
result_real[23] <= lpm_add_sub:add_sub7.result
result_real[24] <= lpm_add_sub:add_sub7.result
result_real[25] <= lpm_add_sub:add_sub7.result
result_real[26] <= lpm_add_sub:add_sub7.result
result_real[27] <= lpm_add_sub:add_sub7.result
result_real[28] <= lpm_add_sub:add_sub7.result
result_real[29] <= lpm_add_sub:add_sub7.result
result_real[30] <= lpm_add_sub:add_sub7.result
result_real[31] <= lpm_add_sub:add_sub7.result
result_real[32] <= lpm_add_sub:add_sub7.result
result_real[33] <= lpm_add_sub:add_sub7.result


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1
accum_sload => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
aclr2 => ~NO_FANOUT~
aclr3 => ~NO_FANOUT~
addnsub1 => ~NO_FANOUT~
addnsub1_round => ~NO_FANOUT~
addnsub3 => ~NO_FANOUT~
addnsub3_round => ~NO_FANOUT~
chainin[0] => ~NO_FANOUT~
chainout_round => ~NO_FANOUT~
chainout_sat_overflow <= chainout_sat_overflow~0.DB_MAX_OUTPUT_PORT_TYPE
chainout_saturate => ~NO_FANOUT~
clock0 => mult_add_dqa1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clock2 => ~NO_FANOUT~
clock3 => ~NO_FANOUT~
dataa[0] => mult_add_dqa1:auto_generated.dataa[0]
dataa[1] => mult_add_dqa1:auto_generated.dataa[1]
dataa[2] => mult_add_dqa1:auto_generated.dataa[2]
dataa[3] => mult_add_dqa1:auto_generated.dataa[3]
dataa[4] => mult_add_dqa1:auto_generated.dataa[4]
dataa[5] => mult_add_dqa1:auto_generated.dataa[5]
dataa[6] => mult_add_dqa1:auto_generated.dataa[6]
dataa[7] => mult_add_dqa1:auto_generated.dataa[7]
dataa[8] => mult_add_dqa1:auto_generated.dataa[8]
dataa[9] => mult_add_dqa1:auto_generated.dataa[9]
dataa[10] => mult_add_dqa1:auto_generated.dataa[10]
dataa[11] => mult_add_dqa1:auto_generated.dataa[11]
dataa[12] => mult_add_dqa1:auto_generated.dataa[12]
dataa[13] => mult_add_dqa1:auto_generated.dataa[13]
dataa[14] => mult_add_dqa1:auto_generated.dataa[14]
dataa[15] => mult_add_dqa1:auto_generated.dataa[15]
dataa[16] => mult_add_dqa1:auto_generated.dataa[16]
datab[0] => mult_add_dqa1:auto_generated.datab[0]
datab[1] => mult_add_dqa1:auto_generated.datab[1]
datab[2] => mult_add_dqa1:auto_generated.datab[2]
datab[3] => mult_add_dqa1:auto_generated.datab[3]
datab[4] => mult_add_dqa1:auto_generated.datab[4]
datab[5] => mult_add_dqa1:auto_generated.datab[5]
datab[6] => mult_add_dqa1:auto_generated.datab[6]
datab[7] => mult_add_dqa1:auto_generated.datab[7]
datab[8] => mult_add_dqa1:auto_generated.datab[8]
datab[9] => mult_add_dqa1:auto_generated.datab[9]
datab[10] => mult_add_dqa1:auto_generated.datab[10]
datab[11] => mult_add_dqa1:auto_generated.datab[11]
datab[12] => mult_add_dqa1:auto_generated.datab[12]
datab[13] => mult_add_dqa1:auto_generated.datab[13]
datab[14] => mult_add_dqa1:auto_generated.datab[14]
datab[15] => mult_add_dqa1:auto_generated.datab[15]
datab[16] => mult_add_dqa1:auto_generated.datab[16]
ena0 => ~NO_FANOUT~
ena1 => ~NO_FANOUT~
ena2 => ~NO_FANOUT~
ena3 => ~NO_FANOUT~
mult01_round => ~NO_FANOUT~
mult01_saturation => ~NO_FANOUT~
mult0_is_saturated <= mult0_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE
mult1_is_saturated <= mult1_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE
mult23_round => ~NO_FANOUT~
mult23_saturation => ~NO_FANOUT~
mult2_is_saturated <= mult2_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE
mult3_is_saturated <= mult3_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE
output_round => ~NO_FANOUT~
output_saturate => ~NO_FANOUT~
overflow <= overflow~0.DB_MAX_OUTPUT_PORT_TYPE
result[0] <= mult_add_dqa1:auto_generated.result[0]
result[1] <= mult_add_dqa1:auto_generated.result[1]
result[2] <= mult_add_dqa1:auto_generated.result[2]
result[3] <= mult_add_dqa1:auto_generated.result[3]
result[4] <= mult_add_dqa1:auto_generated.result[4]
result[5] <= mult_add_dqa1:auto_generated.result[5]
result[6] <= mult_add_dqa1:auto_generated.result[6]
result[7] <= mult_add_dqa1:auto_generated.result[7]
result[8] <= mult_add_dqa1:auto_generated.result[8]
result[9] <= mult_add_dqa1:auto_generated.result[9]
result[10] <= mult_add_dqa1:auto_generated.result[10]
result[11] <= mult_add_dqa1:auto_generated.result[11]
result[12] <= mult_add_dqa1:auto_generated.result[12]
result[13] <= mult_add_dqa1:auto_generated.result[13]
result[14] <= mult_add_dqa1:auto_generated.result[14]
result[15] <= mult_add_dqa1:auto_generated.result[15]
result[16] <= mult_add_dqa1:auto_generated.result[16]
result[17] <= mult_add_dqa1:auto_generated.result[17]
result[18] <= mult_add_dqa1:auto_generated.result[18]
result[19] <= mult_add_dqa1:auto_generated.result[19]
result[20] <= mult_add_dqa1:auto_generated.result[20]
result[21] <= mult_add_dqa1:auto_generated.result[21]
result[22] <= mult_add_dqa1:auto_generated.result[22]
result[23] <= mult_add_dqa1:auto_generated.result[23]
result[24] <= mult_add_dqa1:auto_generated.result[24]
result[25] <= mult_add_dqa1:auto_generated.result[25]
result[26] <= mult_add_dqa1:auto_generated.result[26]
result[27] <= mult_add_dqa1:auto_generated.result[27]
result[28] <= mult_add_dqa1:auto_generated.result[28]
result[29] <= mult_add_dqa1:auto_generated.result[29]
result[30] <= mult_add_dqa1:auto_generated.result[30]
result[31] <= mult_add_dqa1:auto_generated.result[31]
result[32] <= mult_add_dqa1:auto_generated.result[32]
result[33] <= mult_add_dqa1:auto_generated.result[33]
rotate => ~NO_FANOUT~
scanina[0] => ~NO_FANOUT~
scanina[1] => ~NO_FANOUT~
scanina[2] => ~NO_FANOUT~
scanina[3] => ~NO_FANOUT~
scanina[4] => ~NO_FANOUT~
scanina[5] => ~NO_FANOUT~
scanina[6] => ~NO_FANOUT~
scanina[7] => ~NO_FANOUT~
scanina[8] => ~NO_FANOUT~
scanina[9] => ~NO_FANOUT~
scanina[10] => ~NO_FANOUT~
scanina[11] => ~NO_FANOUT~
scanina[12] => ~NO_FANOUT~
scanina[13] => ~NO_FANOUT~
scanina[14] => ~NO_FANOUT~
scanina[15] => ~NO_FANOUT~
scanina[16] => ~NO_FANOUT~
scaninb[0] => ~NO_FANOUT~
scaninb[1] => ~NO_FANOUT~
scaninb[2] => ~NO_FANOUT~
scaninb[3] => ~NO_FANOUT~
scaninb[4] => ~NO_FANOUT~
scaninb[5] => ~NO_FANOUT~
scaninb[6] => ~NO_FANOUT~
scaninb[7] => ~NO_FANOUT~
scaninb[8] => ~NO_FANOUT~
scaninb[9] => ~NO_FANOUT~
scaninb[10] => ~NO_FANOUT~
scaninb[11] => ~NO_FANOUT~
scaninb[12] => ~NO_FANOUT~
scaninb[13] => ~NO_FANOUT~
scaninb[14] => ~NO_FANOUT~
scaninb[15] => ~NO_FANOUT~
scaninb[16] => ~NO_FANOUT~
scanouta[0] <= scanouta[0]~16.DB_MAX_OUTPUT_PORT_TYPE
scanouta[1] <= scanouta[1]~15.DB_MAX_OUTPUT_PORT_TYPE
scanouta[2] <= scanouta[2]~14.DB_MAX_OUTPUT_PORT_TYPE
scanouta[3] <= scanouta[3]~13.DB_MAX_OUTPUT_PORT_TYPE
scanouta[4] <= scanouta[4]~12.DB_MAX_OUTPUT_PORT_TYPE
scanouta[5] <= scanouta[5]~11.DB_MAX_OUTPUT_PORT_TYPE
scanouta[6] <= scanouta[6]~10.DB_MAX_OUTPUT_PORT_TYPE
scanouta[7] <= scanouta[7]~9.DB_MAX_OUTPUT_PORT_TYPE
scanouta[8] <= scanouta[8]~8.DB_MAX_OUTPUT_PORT_TYPE
scanouta[9] <= scanouta[9]~7.DB_MAX_OUTPUT_PORT_TYPE
scanouta[10] <= scanouta[10]~6.DB_MAX_OUTPUT_PORT_TYPE
scanouta[11] <= scanouta[11]~5.DB_MAX_OUTPUT_PORT_TYPE
scanouta[12] <= scanouta[12]~4.DB_MAX_OUTPUT_PORT_TYPE
scanouta[13] <= scanouta[13]~3.DB_MAX_OUTPUT_PORT_TYPE
scanouta[14] <= scanouta[14]~2.DB_MAX_OUTPUT_PORT_TYPE
scanouta[15] <= scanouta[15]~1.DB_MAX_OUTPUT_PORT_TYPE
scanouta[16] <= scanouta[16]~0.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[0] <= scanoutb[0]~16.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[1] <= scanoutb[1]~15.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[2] <= scanoutb[2]~14.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[3] <= scanoutb[3]~13.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[4] <= scanoutb[4]~12.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[5] <= scanoutb[5]~11.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[6] <= scanoutb[6]~10.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[7] <= scanoutb[7]~9.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[8] <= scanoutb[8]~8.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[9] <= scanoutb[9]~7.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[10] <= scanoutb[10]~6.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[11] <= scanoutb[11]~5.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[12] <= scanoutb[12]~4.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[13] <= scanoutb[13]~3.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[14] <= scanoutb[14]~2.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[15] <= scanoutb[15]~1.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[16] <= scanoutb[16]~0.DB_MAX_OUTPUT_PORT_TYPE
shift_right => ~NO_FANOUT~
signa => ~NO_FANOUT~
signb => ~NO_FANOUT~
sourcea[0] => ~NO_FANOUT~
sourceb[0] => ~NO_FANOUT~
zero_chainout => ~NO_FANOUT~
zero_loopback => ~NO_FANOUT~


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1|mult_add_dqa1:auto_generated
clock0 => ded_mult_1t51:ded_mult1.clock[0]
clock0 => dffe2a[33].CLK
clock0 => dffe2a[32].CLK
clock0 => dffe2a[31].CLK
clock0 => dffe2a[30].CLK
clock0 => dffe2a[29].CLK
clock0 => dffe2a[28].CLK
clock0 => dffe2a[27].CLK
clock0 => dffe2a[26].CLK
clock0 => dffe2a[25].CLK
clock0 => dffe2a[24].CLK
clock0 => dffe2a[23].CLK
clock0 => dffe2a[22].CLK
clock0 => dffe2a[21].CLK
clock0 => dffe2a[20].CLK
clock0 => dffe2a[19].CLK
clock0 => dffe2a[18].CLK
clock0 => dffe2a[17].CLK
clock0 => dffe2a[16].CLK
clock0 => dffe2a[15].CLK
clock0 => dffe2a[14].CLK
clock0 => dffe2a[13].CLK
clock0 => dffe2a[12].CLK
clock0 => dffe2a[11].CLK
clock0 => dffe2a[10].CLK
clock0 => dffe2a[9].CLK
clock0 => dffe2a[8].CLK
clock0 => dffe2a[7].CLK
clock0 => dffe2a[6].CLK
clock0 => dffe2a[5].CLK
clock0 => dffe2a[4].CLK
clock0 => dffe2a[3].CLK
clock0 => dffe2a[2].CLK
clock0 => dffe2a[1].CLK
clock0 => dffe2a[0].CLK
dataa[0] => ded_mult_1t51:ded_mult1.dataa[0]
dataa[1] => ded_mult_1t51:ded_mult1.dataa[1]
dataa[2] => ded_mult_1t51:ded_mult1.dataa[2]
dataa[3] => ded_mult_1t51:ded_mult1.dataa[3]
dataa[4] => ded_mult_1t51:ded_mult1.dataa[4]
dataa[5] => ded_mult_1t51:ded_mult1.dataa[5]
dataa[6] => ded_mult_1t51:ded_mult1.dataa[6]
dataa[7] => ded_mult_1t51:ded_mult1.dataa[7]
dataa[8] => ded_mult_1t51:ded_mult1.dataa[8]
dataa[9] => ded_mult_1t51:ded_mult1.dataa[9]
dataa[10] => ded_mult_1t51:ded_mult1.dataa[10]
dataa[11] => ded_mult_1t51:ded_mult1.dataa[11]
dataa[12] => ded_mult_1t51:ded_mult1.dataa[12]
dataa[13] => ded_mult_1t51:ded_mult1.dataa[13]
dataa[14] => ded_mult_1t51:ded_mult1.dataa[14]
dataa[15] => ded_mult_1t51:ded_mult1.dataa[15]
dataa[16] => ded_mult_1t51:ded_mult1.dataa[16]
datab[0] => ded_mult_1t51:ded_mult1.datab[0]
datab[1] => ded_mult_1t51:ded_mult1.datab[1]
datab[2] => ded_mult_1t51:ded_mult1.datab[2]
datab[3] => ded_mult_1t51:ded_mult1.datab[3]
datab[4] => ded_mult_1t51:ded_mult1.datab[4]
datab[5] => ded_mult_1t51:ded_mult1.datab[5]
datab[6] => ded_mult_1t51:ded_mult1.datab[6]
datab[7] => ded_mult_1t51:ded_mult1.datab[7]
datab[8] => ded_mult_1t51:ded_mult1.datab[8]
datab[9] => ded_mult_1t51:ded_mult1.datab[9]
datab[10] => ded_mult_1t51:ded_mult1.datab[10]
datab[11] => ded_mult_1t51:ded_mult1.datab[11]
datab[12] => ded_mult_1t51:ded_mult1.datab[12]
datab[13] => ded_mult_1t51:ded_mult1.datab[13]
datab[14] => ded_mult_1t51:ded_mult1.datab[14]
datab[15] => ded_mult_1t51:ded_mult1.datab[15]
datab[16] => ded_mult_1t51:ded_mult1.datab[16]
result[0] <= dffe2a[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= dffe2a[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= dffe2a[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= dffe2a[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= dffe2a[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= dffe2a[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= dffe2a[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= dffe2a[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= dffe2a[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= dffe2a[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= dffe2a[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= dffe2a[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= dffe2a[12].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= dffe2a[13].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= dffe2a[14].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= dffe2a[15].DB_MAX_OUTPUT_PORT_TYPE
result[16] <= dffe2a[16].DB_MAX_OUTPUT_PORT_TYPE
result[17] <= dffe2a[17].DB_MAX_OUTPUT_PORT_TYPE
result[18] <= dffe2a[18].DB_MAX_OUTPUT_PORT_TYPE
result[19] <= dffe2a[19].DB_MAX_OUTPUT_PORT_TYPE
result[20] <= dffe2a[20].DB_MAX_OUTPUT_PORT_TYPE
result[21] <= dffe2a[21].DB_MAX_OUTPUT_PORT_TYPE
result[22] <= dffe2a[22].DB_MAX_OUTPUT_PORT_TYPE
result[23] <= dffe2a[23].DB_MAX_OUTPUT_PORT_TYPE
result[24] <= dffe2a[24].DB_MAX_OUTPUT_PORT_TYPE
result[25] <= dffe2a[25].DB_MAX_OUTPUT_PORT_TYPE
result[26] <= dffe2a[26].DB_MAX_OUTPUT_PORT_TYPE
result[27] <= dffe2a[27].DB_MAX_OUTPUT_PORT_TYPE
result[28] <= dffe2a[28].DB_MAX_OUTPUT_PORT_TYPE
result[29] <= dffe2a[29].DB_MAX_OUTPUT_PORT_TYPE
result[30] <= dffe2a[30].DB_MAX_OUTPUT_PORT_TYPE
result[31] <= dffe2a[31].DB_MAX_OUTPUT_PORT_TYPE
result[32] <= dffe2a[32].DB_MAX_OUTPUT_PORT_TYPE
result[33] <= dffe2a[33].DB_MAX_OUTPUT_PORT_TYPE


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1|mult_add_dqa1:auto_generated|ded_mult_1t51:ded_mult1
aclr[0] => mac_mult3.ACLR
aclr[1] => ~NO_FANOUT~
aclr[2] => ~NO_FANOUT~
aclr[3] => ~NO_FANOUT~
clock[0] => mac_mult3.CLK
clock[1] => ~NO_FANOUT~
clock[2] => ~NO_FANOUT~
clock[3] => ~NO_FANOUT~
dataa[0] => mac_mult3.DATAA
dataa[1] => mac_mult3.DATAA1
dataa[2] => mac_mult3.DATAA2
dataa[3] => mac_mult3.DATAA3
dataa[4] => mac_mult3.DATAA4
dataa[5] => mac_mult3.DATAA5
dataa[6] => mac_mult3.DATAA6
dataa[7] => mac_mult3.DATAA7
dataa[8] => mac_mult3.DATAA8
dataa[9] => mac_mult3.DATAA9
dataa[10] => mac_mult3.DATAA10
dataa[11] => mac_mult3.DATAA11
dataa[12] => mac_mult3.DATAA12
dataa[13] => mac_mult3.DATAA13
dataa[14] => mac_mult3.DATAA14
dataa[15] => mac_mult3.DATAA15
dataa[16] => mac_mult3.DATAA16
datab[0] => mac_mult3.DATAB
datab[1] => mac_mult3.DATAB1
datab[2] => mac_mult3.DATAB2
datab[3] => mac_mult3.DATAB3
datab[4] => mac_mult3.DATAB4
datab[5] => mac_mult3.DATAB5
datab[6] => mac_mult3.DATAB6
datab[7] => mac_mult3.DATAB7
datab[8] => mac_mult3.DATAB8
datab[9] => mac_mult3.DATAB9
datab[10] => mac_mult3.DATAB10
datab[11] => mac_mult3.DATAB11
datab[12] => mac_mult3.DATAB12
datab[13] => mac_mult3.DATAB13
datab[14] => mac_mult3.DATAB14
datab[15] => mac_mult3.DATAB15
datab[16] => mac_mult3.DATAB16
ena[0] => mac_mult3.ENA
ena[1] => ~NO_FANOUT~
ena[2] => ~NO_FANOUT~
ena[3] => ~NO_FANOUT~
result[0] <= dffpipe_b3c:pre_result.q[0]
result[1] <= dffpipe_b3c:pre_result.q[1]
result[2] <= dffpipe_b3c:pre_result.q[2]
result[3] <= dffpipe_b3c:pre_result.q[3]
result[4] <= dffpipe_b3c:pre_result.q[4]
result[5] <= dffpipe_b3c:pre_result.q[5]
result[6] <= dffpipe_b3c:pre_result.q[6]
result[7] <= dffpipe_b3c:pre_result.q[7]
result[8] <= dffpipe_b3c:pre_result.q[8]
result[9] <= dffpipe_b3c:pre_result.q[9]
result[10] <= dffpipe_b3c:pre_result.q[10]
result[11] <= dffpipe_b3c:pre_result.q[11]
result[12] <= dffpipe_b3c:pre_result.q[12]
result[13] <= dffpipe_b3c:pre_result.q[13]
result[14] <= dffpipe_b3c:pre_result.q[14]
result[15] <= dffpipe_b3c:pre_result.q[15]
result[16] <= dffpipe_b3c:pre_result.q[16]
result[17] <= dffpipe_b3c:pre_result.q[17]
result[18] <= dffpipe_b3c:pre_result.q[18]
result[19] <= dffpipe_b3c:pre_result.q[19]
result[20] <= dffpipe_b3c:pre_result.q[20]
result[21] <= dffpipe_b3c:pre_result.q[21]
result[22] <= dffpipe_b3c:pre_result.q[22]
result[23] <= dffpipe_b3c:pre_result.q[23]
result[24] <= dffpipe_b3c:pre_result.q[24]
result[25] <= dffpipe_b3c:pre_result.q[25]
result[26] <= dffpipe_b3c:pre_result.q[26]
result[27] <= dffpipe_b3c:pre_result.q[27]
result[28] <= dffpipe_b3c:pre_result.q[28]
result[29] <= dffpipe_b3c:pre_result.q[29]
result[30] <= dffpipe_b3c:pre_result.q[30]
result[31] <= dffpipe_b3c:pre_result.q[31]
result[32] <= dffpipe_b3c:pre_result.q[32]
result[33] <= dffpipe_b3c:pre_result.q[33]


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1|mult_add_dqa1:auto_generated|ded_mult_1t51:ded_mult1|dffpipe_b3c:pre_result
d[0] => q[0].DATAIN
d[1] => q[1].DATAIN
d[2] => q[2].DATAIN
d[3] => q[3].DATAIN
d[4] => q[4].DATAIN
d[5] => q[5].DATAIN
d[6] => q[6].DATAIN
d[7] => q[7].DATAIN
d[8] => q[8].DATAIN
d[9] => q[9].DATAIN
d[10] => q[10].DATAIN
d[11] => q[11].DATAIN
d[12] => q[12].DATAIN
d[13] => q[13].DATAIN
d[14] => q[14].DATAIN
d[15] => q[15].DATAIN
d[16] => q[16].DATAIN
d[17] => q[17].DATAIN
d[18] => q[18].DATAIN
d[19] => q[19].DATAIN
d[20] => q[20].DATAIN
d[21] => q[21].DATAIN
d[22] => q[22].DATAIN
d[23] => q[23].DATAIN
d[24] => q[24].DATAIN
d[25] => q[25].DATAIN
d[26] => q[26].DATAIN
d[27] => q[27].DATAIN
d[28] => q[28].DATAIN
d[29] => q[29].DATAIN
d[30] => q[30].DATAIN
d[31] => q[31].DATAIN
d[32] => q[32].DATAIN
d[33] => q[33].DATAIN
q[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= d[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= d[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= d[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= d[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= d[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= d[12].DB_MAX_OUTPUT_PORT_TYPE
q[13] <= d[13].DB_MAX_OUTPUT_PORT_TYPE
q[14] <= d[14].DB_MAX_OUTPUT_PORT_TYPE
q[15] <= d[15].DB_MAX_OUTPUT_PORT_TYPE
q[16] <= d[16].DB_MAX_OUTPUT_PORT_TYPE
q[17] <= d[17].DB_MAX_OUTPUT_PORT_TYPE
q[18] <= d[18].DB_MAX_OUTPUT_PORT_TYPE
q[19] <= d[19].DB_MAX_OUTPUT_PORT_TYPE
q[20] <= d[20].DB_MAX_OUTPUT_PORT_TYPE
q[21] <= d[21].DB_MAX_OUTPUT_PORT_TYPE
q[22] <= d[22].DB_MAX_OUTPUT_PORT_TYPE
q[23] <= d[23].DB_MAX_OUTPUT_PORT_TYPE
q[24] <= d[24].DB_MAX_OUTPUT_PORT_TYPE
q[25] <= d[25].DB_MAX_OUTPUT_PORT_TYPE
q[26] <= d[26].DB_MAX_OUTPUT_PORT_TYPE
q[27] <= d[27].DB_MAX_OUTPUT_PORT_TYPE
q[28] <= d[28].DB_MAX_OUTPUT_PORT_TYPE
q[29] <= d[29].DB_MAX_OUTPUT_PORT_TYPE
q[30] <= d[30].DB_MAX_OUTPUT_PORT_TYPE
q[31] <= d[31].DB_MAX_OUTPUT_PORT_TYPE
q[32] <= d[32].DB_MAX_OUTPUT_PORT_TYPE
q[33] <= d[33].DB_MAX_OUTPUT_PORT_TYPE


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add2
accum_sload => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
aclr2 => ~NO_FANOUT~
aclr3 => ~NO_FANOUT~
addnsub1 => ~NO_FANOUT~
addnsub1_round => ~NO_FANOUT~
addnsub3 => ~NO_FANOUT~
addnsub3_round => ~NO_FANOUT~
chainin[0] => ~NO_FANOUT~
chainout_round => ~NO_FANOUT~
chainout_sat_overflow <= chainout_sat_overflow~0.DB_MAX_OUTPUT_PORT_TYPE
chainout_saturate => ~NO_FANOUT~
clock0 => mult_add_dqa1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clock2 => ~NO_FANOUT~
clock3 => ~NO_FANOUT~
dataa[0] => mult_add_dqa1:auto_generated.dataa[0]
dataa[1] => mult_add_dqa1:auto_generated.dataa[1]
dataa[2] => mult_add_dqa1:auto_generated.dataa[2]
dataa[3] => mult_add_dqa1:auto_generated.dataa[3]
dataa[4] => mult_add_dqa1:auto_generated.dataa[4]
dataa[5] => mult_add_dqa1:auto_generated.dataa[5]
dataa[6] => mult_add_dqa1:auto_generated.dataa[6]
dataa[7] => mult_add_dqa1:auto_generated.dataa[7]
dataa[8] => mult_add_dqa1:auto_generated.dataa[8]
dataa[9] => mult_add_dqa1:auto_generated.dataa[9]
dataa[10] => mult_add_dqa1:auto_generated.dataa[10]
dataa[11] => mult_add_dqa1:auto_generated.dataa[11]
dataa[12] => mult_add_dqa1:auto_generated.dataa[12]
dataa[13] => mult_add_dqa1:auto_generated.dataa[13]
dataa[14] => mult_add_dqa1:auto_generated.dataa[14]
dataa[15] => mult_add_dqa1:auto_generated.dataa[15]
dataa[16] => mult_add_dqa1:auto_generated.dataa[16]
datab[0] => mult_add_dqa1:auto_generated.datab[0]
datab[1] => mult_add_dqa1:auto_generated.datab[1]
datab[2] => mult_add_dqa1:auto_generated.datab[2]
datab[3] => mult_add_dqa1:auto_generated.datab[3]
datab[4] => mult_add_dqa1:auto_generated.datab[4]
datab[5] => mult_add_dqa1:auto_generated.datab[5]
datab[6] => mult_add_dqa1:auto_generated.datab[6]
datab[7] => mult_add_dqa1:auto_generated.datab[7]
datab[8] => mult_add_dqa1:auto_generated.datab[8]
datab[9] => mult_add_dqa1:auto_generated.datab[9]
datab[10] => mult_add_dqa1:auto_generated.datab[10]
datab[11] => mult_add_dqa1:auto_generated.datab[11]
datab[12] => mult_add_dqa1:auto_generated.datab[12]
datab[13] => mult_add_dqa1:auto_generated.datab[13]
datab[14] => mult_add_dqa1:auto_generated.datab[14]
datab[15] => mult_add_dqa1:auto_generated.datab[15]
datab[16] => mult_add_dqa1:auto_generated.datab[16]
ena0 => ~NO_FANOUT~
ena1 => ~NO_FANOUT~
ena2 => ~NO_FANOUT~
ena3 => ~NO_FANOUT~
mult01_round => ~NO_FANOUT~
mult01_saturation => ~NO_FANOUT~
mult0_is_saturated <= mult0_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE
mult1_is_saturated <= mult1_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE
mult23_round => ~NO_FANOUT~
mult23_saturation => ~NO_FANOUT~
mult2_is_saturated <= mult2_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE
mult3_is_saturated <= mult3_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE
output_round => ~NO_FANOUT~
output_saturate => ~NO_FANOUT~
overflow <= overflow~0.DB_MAX_OUTPUT_PORT_TYPE
result[0] <= mult_add_dqa1:auto_generated.result[0]
result[1] <= mult_add_dqa1:auto_generated.result[1]
result[2] <= mult_add_dqa1:auto_generated.result[2]
result[3] <= mult_add_dqa1:auto_generated.result[3]
result[4] <= mult_add_dqa1:auto_generated.result[4]
result[5] <= mult_add_dqa1:auto_generated.result[5]
result[6] <= mult_add_dqa1:auto_generated.result[6]
result[7] <= mult_add_dqa1:auto_generated.result[7]
result[8] <= mult_add_dqa1:auto_generated.result[8]
result[9] <= mult_add_dqa1:auto_generated.result[9]
result[10] <= mult_add_dqa1:auto_generated.result[10]
result[11] <= mult_add_dqa1:auto_generated.result[11]
result[12] <= mult_add_dqa1:auto_generated.result[12]
result[13] <= mult_add_dqa1:auto_generated.result[13]
result[14] <= mult_add_dqa1:auto_generated.result[14]
result[15] <= mult_add_dqa1:auto_generated.result[15]
result[16] <= mult_add_dqa1:auto_generated.result[16]
result[17] <= mult_add_dqa1:auto_generated.result[17]
result[18] <= mult_add_dqa1:auto_generated.result[18]
result[19] <= mult_add_dqa1:auto_generated.result[19]
result[20] <= mult_add_dqa1:auto_generated.result[20]
result[21] <= mult_add_dqa1:auto_generated.result[21]
result[22] <= mult_add_dqa1:auto_generated.result[22]
result[23] <= mult_add_dqa1:auto_generated.result[23]
result[24] <= mult_add_dqa1:auto_generated.result[24]
result[25] <= mult_add_dqa1:auto_generated.result[25]
result[26] <= mult_add_dqa1:auto_generated.result[26]
result[27] <= mult_add_dqa1:auto_generated.result[27]
result[28] <= mult_add_dqa1:auto_generated.result[28]
result[29] <= mult_add_dqa1:auto_generated.result[29]
result[30] <= mult_add_dqa1:auto_generated.result[30]
result[31] <= mult_add_dqa1:auto_generated.result[31]
result[32] <= mult_add_dqa1:auto_generated.result[32]
result[33] <= mult_add_dqa1:auto_generated.result[33]
rotate => ~NO_FANOUT~
scanina[0] => ~NO_FANOUT~
scanina[1] => ~NO_FANOUT~
scanina[2] => ~NO_FANOUT~
scanina[3] => ~NO_FANOUT~
scanina[4] => ~NO_FANOUT~
scanina[5] => ~NO_FANOUT~
scanina[6] => ~NO_FANOUT~
scanina[7] => ~NO_FANOUT~
scanina[8] => ~NO_FANOUT~
scanina[9] => ~NO_FANOUT~
scanina[10] => ~NO_FANOUT~
scanina[11] => ~NO_FANOUT~
scanina[12] => ~NO_FANOUT~
scanina[13] => ~NO_FANOUT~
scanina[14] => ~NO_FANOUT~
scanina[15] => ~NO_FANOUT~
scanina[16] => ~NO_FANOUT~
scaninb[0] => ~NO_FANOUT~
scaninb[1] => ~NO_FANOUT~
scaninb[2] => ~NO_FANOUT~
scaninb[3] => ~NO_FANOUT~
scaninb[4] => ~NO_FANOUT~
scaninb[5] => ~NO_FANOUT~
scaninb[6] => ~NO_FANOUT~
scaninb[7] => ~NO_FANOUT~
scaninb[8] => ~NO_FANOUT~
scaninb[9] => ~NO_FANOUT~
scaninb[10] => ~NO_FANOUT~
scaninb[11] => ~NO_FANOUT~
scaninb[12] => ~NO_FANOUT~
scaninb[13] => ~NO_FANOUT~
scaninb[14] => ~NO_FANOUT~
scaninb[15] => ~NO_FANOUT~
scaninb[16] => ~NO_FANOUT~
scanouta[0] <= scanouta[0]~16.DB_MAX_OUTPUT_PORT_TYPE
scanouta[1] <= scanouta[1]~15.DB_MAX_OUTPUT_PORT_TYPE
scanouta[2] <= scanouta[2]~14.DB_MAX_OUTPUT_PORT_TYPE
scanouta[3] <= scanouta[3]~13.DB_MAX_OUTPUT_PORT_TYPE
scanouta[4] <= scanouta[4]~12.DB_MAX_OUTPUT_PORT_TYPE
scanouta[5] <= scanouta[5]~11.DB_MAX_OUTPUT_PORT_TYPE
scanouta[6] <= scanouta[6]~10.DB_MAX_OUTPUT_PORT_TYPE
scanouta[7] <= scanouta[7]~9.DB_MAX_OUTPUT_PORT_TYPE
scanouta[8] <= scanouta[8]~8.DB_MAX_OUTPUT_PORT_TYPE
scanouta[9] <= scanouta[9]~7.DB_MAX_OUTPUT_PORT_TYPE
scanouta[10] <= scanouta[10]~6.DB_MAX_OUTPUT_PORT_TYPE
scanouta[11] <= scanouta[11]~5.DB_MAX_OUTPUT_PORT_TYPE
scanouta[12] <= scanouta[12]~4.DB_MAX_OUTPUT_PORT_TYPE
scanouta[13] <= scanouta[13]~3.DB_MAX_OUTPUT_PORT_TYPE
scanouta[14] <= scanouta[14]~2.DB_MAX_OUTPUT_PORT_TYPE
scanouta[15] <= scanouta[15]~1.DB_MAX_OUTPUT_PORT_TYPE
scanouta[16] <= scanouta[16]~0.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[0] <= scanoutb[0]~16.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[1] <= scanoutb[1]~15.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[2] <= scanoutb[2]~14.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[3] <= scanoutb[3]~13.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[4] <= scanoutb[4]~12.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[5] <= scanoutb[5]~11.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[6] <= scanoutb[6]~10.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[7] <= scanoutb[7]~9.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[8] <= scanoutb[8]~8.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[9] <= scanoutb[9]~7.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[10] <= scanoutb[10]~6.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[11] <= scanoutb[11]~5.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[12] <= scanoutb[12]~4.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[13] <= scanoutb[13]~3.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[14] <= scanoutb[14]~2.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[15] <= scanoutb[15]~1.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[16] <= scanoutb[16]~0.DB_MAX_OUTPUT_PORT_TYPE
shift_right => ~NO_FANOUT~
signa => ~NO_FANOUT~
signb => ~NO_FANOUT~
sourcea[0] => ~NO_FANOUT~
sourceb[0] => ~NO_FANOUT~
zero_chainout => ~NO_FANOUT~
zero_loopback => ~NO_FANOUT~


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add2|mult_add_dqa1:auto_generated
clock0 => ded_mult_1t51:ded_mult1.clock[0]
clock0 => dffe2a[33].CLK
clock0 => dffe2a[32].CLK
clock0 => dffe2a[31].CLK
clock0 => dffe2a[30].CLK
clock0 => dffe2a[29].CLK
clock0 => dffe2a[28].CLK
clock0 => dffe2a[27].CLK
clock0 => dffe2a[26].CLK
clock0 => dffe2a[25].CLK
clock0 => dffe2a[24].CLK
clock0 => dffe2a[23].CLK
clock0 => dffe2a[22].CLK
clock0 => dffe2a[21].CLK
clock0 => dffe2a[20].CLK
clock0 => dffe2a[19].CLK
clock0 => dffe2a[18].CLK
clock0 => dffe2a[17].CLK
clock0 => dffe2a[16].CLK
clock0 => dffe2a[15].CLK
clock0 => dffe2a[14].CLK
clock0 => dffe2a[13].CLK
clock0 => dffe2a[12].CLK
clock0 => dffe2a[11].CLK
clock0 => dffe2a[10].CLK
clock0 => dffe2a[9].CLK
clock0 => dffe2a[8].CLK
clock0 => dffe2a[7].CLK
clock0 => dffe2a[6].CLK
clock0 => dffe2a[5].CLK
clock0 => dffe2a[4].CLK
clock0 => dffe2a[3].CLK
clock0 => dffe2a[2].CLK
clock0 => dffe2a[1].CLK
clock0 => dffe2a[0].CLK
dataa[0] => ded_mult_1t51:ded_mult1.dataa[0]
dataa[1] => ded_mult_1t51:ded_mult1.dataa[1]
dataa[2] => ded_mult_1t51:ded_mult1.dataa[2]
dataa[3] => ded_mult_1t51:ded_mult1.dataa[3]
dataa[4] => ded_mult_1t51:ded_mult1.dataa[4]
dataa[5] => ded_mult_1t51:ded_mult1.dataa[5]
dataa[6] => ded_mult_1t51:ded_mult1.dataa[6]
dataa[7] => ded_mult_1t51:ded_mult1.dataa[7]
dataa[8] => ded_mult_1t51:ded_mult1.dataa[8]
dataa[9] => ded_mult_1t51:ded_mult1.dataa[9]
dataa[10] => ded_mult_1t51:ded_mult1.dataa[10]
dataa[11] => ded_mult_1t51:ded_mult1.dataa[11]
dataa[12] => ded_mult_1t51:ded_mult1.dataa[12]
dataa[13] => ded_mult_1t51:ded_mult1.dataa[13]
dataa[14] => ded_mult_1t51:ded_mult1.dataa[14]
dataa[15] => ded_mult_1t51:ded_mult1.dataa[15]
dataa[16] => ded_mult_1t51:ded_mult1.dataa[16]
datab[0] => ded_mult_1t51:ded_mult1.datab[0]
datab[1] => ded_mult_1t51:ded_mult1.datab[1]
datab[2] => ded_mult_1t51:ded_mult1.datab[2]
datab[3] => ded_mult_1t51:ded_mult1.datab[3]
datab[4] => ded_mult_1t51:ded_mult1.datab[4]
datab[5] => ded_mult_1t51:ded_mult1.datab[5]
datab[6] => ded_mult_1t51:ded_mult1.datab[6]
datab[7] => ded_mult_1t51:ded_mult1.datab[7]
datab[8] => ded_mult_1t51:ded_mult1.datab[8]
datab[9] => ded_mult_1t51:ded_mult1.datab[9]
datab[10] => ded_mult_1t51:ded_mult1.datab[10]
datab[11] => ded_mult_1t51:ded_mult1.datab[11]
datab[12] => ded_mult_1t51:ded_mult1.datab[12]
datab[13] => ded_mult_1t51:ded_mult1.datab[13]
datab[14] => ded_mult_1t51:ded_mult1.datab[14]
datab[15] => ded_mult_1t51:ded_mult1.datab[15]
datab[16] => ded_mult_1t51:ded_mult1.datab[16]
result[0] <= dffe2a[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= dffe2a[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= dffe2a[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= dffe2a[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= dffe2a[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= dffe2a[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= dffe2a[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= dffe2a[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= dffe2a[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= dffe2a[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= dffe2a[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= dffe2a[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= dffe2a[12].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= dffe2a[13].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= dffe2a[14].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= dffe2a[15].DB_MAX_OUTPUT_PORT_TYPE
result[16] <= dffe2a[16].DB_MAX_OUTPUT_PORT_TYPE
result[17] <= dffe2a[17].DB_MAX_OUTPUT_PORT_TYPE
result[18] <= dffe2a[18].DB_MAX_OUTPUT_PORT_TYPE
result[19] <= dffe2a[19].DB_MAX_OUTPUT_PORT_TYPE
result[20] <= dffe2a[20].DB_MAX_OUTPUT_PORT_TYPE
result[21] <= dffe2a[21].DB_MAX_OUTPUT_PORT_TYPE
result[22] <= dffe2a[22].DB_MAX_OUTPUT_PORT_TYPE
result[23] <= dffe2a[23].DB_MAX_OUTPUT_PORT_TYPE
result[24] <= dffe2a[24].DB_MAX_OUTPUT_PORT_TYPE
result[25] <= dffe2a[25].DB_MAX_OUTPUT_PORT_TYPE
result[26] <= dffe2a[26].DB_MAX_OUTPUT_PORT_TYPE
result[27] <= dffe2a[27].DB_MAX_OUTPUT_PORT_TYPE
result[28] <= dffe2a[28].DB_MAX_OUTPUT_PORT_TYPE
result[29] <= dffe2a[29].DB_MAX_OUTPUT_PORT_TYPE
result[30] <= dffe2a[30].DB_MAX_OUTPUT_PORT_TYPE
result[31] <= dffe2a[31].DB_MAX_OUTPUT_PORT_TYPE
result[32] <= dffe2a[32].DB_MAX_OUTPUT_PORT_TYPE
result[33] <= dffe2a[33].DB_MAX_OUTPUT_PORT_TYPE


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add2|mult_add_dqa1:auto_generated|ded_mult_1t51:ded_mult1
aclr[0] => mac_mult3.ACLR
aclr[1] => ~NO_FANOUT~
aclr[2] => ~NO_FANOUT~
aclr[3] => ~NO_FANOUT~
clock[0] => mac_mult3.CLK
clock[1] => ~NO_FANOUT~
clock[2] => ~NO_FANOUT~
clock[3] => ~NO_FANOUT~
dataa[0] => mac_mult3.DATAA
dataa[1] => mac_mult3.DATAA1
dataa[2] => mac_mult3.DATAA2
dataa[3] => mac_mult3.DATAA3
dataa[4] => mac_mult3.DATAA4
dataa[5] => mac_mult3.DATAA5
dataa[6] => mac_mult3.DATAA6
dataa[7] => mac_mult3.DATAA7
dataa[8] => mac_mult3.DATAA8
dataa[9] => mac_mult3.DATAA9
dataa[10] => mac_mult3.DATAA10
dataa[11] => mac_mult3.DATAA11
dataa[12] => mac_mult3.DATAA12
dataa[13] => mac_mult3.DATAA13
dataa[14] => mac_mult3.DATAA14
dataa[15] => mac_mult3.DATAA15
dataa[16] => mac_mult3.DATAA16
datab[0] => mac_mult3.DATAB
datab[1] => mac_mult3.DATAB1
datab[2] => mac_mult3.DATAB2
datab[3] => mac_mult3.DATAB3
datab[4] => mac_mult3.DATAB4
datab[5] => mac_mult3.DATAB5
datab[6] => mac_mult3.DATAB6
datab[7] => mac_mult3.DATAB7
datab[8] => mac_mult3.DATAB8
datab[9] => mac_mult3.DATAB9
datab[10] => mac_mult3.DATAB10
datab[11] => mac_mult3.DATAB11
datab[12] => mac_mult3.DATAB12
datab[13] => mac_mult3.DATAB13
datab[14] => mac_mult3.DATAB14
datab[15] => mac_mult3.DATAB15
datab[16] => mac_mult3.DATAB16
ena[0] => mac_mult3.ENA
ena[1] => ~NO_FANOUT~
ena[2] => ~NO_FANOUT~
ena[3] => ~NO_FANOUT~
result[0] <= dffpipe_b3c:pre_result.q[0]
result[1] <= dffpipe_b3c:pre_result.q[1]
result[2] <= dffpipe_b3c:pre_result.q[2]
result[3] <= dffpipe_b3c:pre_result.q[3]
result[4] <= dffpipe_b3c:pre_result.q[4]
result[5] <= dffpipe_b3c:pre_result.q[5]
result[6] <= dffpipe_b3c:pre_result.q[6]
result[7] <= dffpipe_b3c:pre_result.q[7]
result[8] <= dffpipe_b3c:pre_result.q[8]
result[9] <= dffpipe_b3c:pre_result.q[9]
result[10] <= dffpipe_b3c:pre_result.q[10]
result[11] <= dffpipe_b3c:pre_result.q[11]
result[12] <= dffpipe_b3c:pre_result.q[12]
result[13] <= dffpipe_b3c:pre_result.q[13]
result[14] <= dffpipe_b3c:pre_result.q[14]
result[15] <= dffpipe_b3c:pre_result.q[15]
result[16] <= dffpipe_b3c:pre_result.q[16]
result[17] <= dffpipe_b3c:pre_result.q[17]
result[18] <= dffpipe_b3c:pre_result.q[18]
result[19] <= dffpipe_b3c:pre_result.q[19]
result[20] <= dffpipe_b3c:pre_result.q[20]
result[21] <= dffpipe_b3c:pre_result.q[21]
result[22] <= dffpipe_b3c:pre_result.q[22]
result[23] <= dffpipe_b3c:pre_result.q[23]
result[24] <= dffpipe_b3c:pre_result.q[24]
result[25] <= dffpipe_b3c:pre_result.q[25]
result[26] <= dffpipe_b3c:pre_result.q[26]
result[27] <= dffpipe_b3c:pre_result.q[27]
result[28] <= dffpipe_b3c:pre_result.q[28]
result[29] <= dffpipe_b3c:pre_result.q[29]
result[30] <= dffpipe_b3c:pre_result.q[30]
result[31] <= dffpipe_b3c:pre_result.q[31]
result[32] <= dffpipe_b3c:pre_result.q[32]
result[33] <= dffpipe_b3c:pre_result.q[33]


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add2|mult_add_dqa1:auto_generated|ded_mult_1t51:ded_mult1|dffpipe_b3c:pre_result
d[0] => q[0].DATAIN
d[1] => q[1].DATAIN
d[2] => q[2].DATAIN
d[3] => q[3].DATAIN
d[4] => q[4].DATAIN
d[5] => q[5].DATAIN
d[6] => q[6].DATAIN
d[7] => q[7].DATAIN
d[8] => q[8].DATAIN
d[9] => q[9].DATAIN
d[10] => q[10].DATAIN
d[11] => q[11].DATAIN
d[12] => q[12].DATAIN
d[13] => q[13].DATAIN
d[14] => q[14].DATAIN
d[15] => q[15].DATAIN
d[16] => q[16].DATAIN
d[17] => q[17].DATAIN
d[18] => q[18].DATAIN
d[19] => q[19].DATAIN
d[20] => q[20].DATAIN
d[21] => q[21].DATAIN
d[22] => q[22].DATAIN
d[23] => q[23].DATAIN
d[24] => q[24].DATAIN
d[25] => q[25].DATAIN
d[26] => q[26].DATAIN
d[27] => q[27].DATAIN
d[28] => q[28].DATAIN
d[29] => q[29].DATAIN
d[30] => q[30].DATAIN
d[31] => q[31].DATAIN
d[32] => q[32].DATAIN
d[33] => q[33].DATAIN
q[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= d[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= d[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= d[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= d[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= d[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= d[12].DB_MAX_OUTPUT_PORT_TYPE
q[13] <= d[13].DB_MAX_OUTPUT_PORT_TYPE
q[14] <= d[14].DB_MAX_OUTPUT_PORT_TYPE
q[15] <= d[15].DB_MAX_OUTPUT_PORT_TYPE
q[16] <= d[16].DB_MAX_OUTPUT_PORT_TYPE
q[17] <= d[17].DB_MAX_OUTPUT_PORT_TYPE
q[18] <= d[18].DB_MAX_OUTPUT_PORT_TYPE
q[19] <= d[19].DB_MAX_OUTPUT_PORT_TYPE
q[20] <= d[20].DB_MAX_OUTPUT_PORT_TYPE
q[21] <= d[21].DB_MAX_OUTPUT_PORT_TYPE
q[22] <= d[22].DB_MAX_OUTPUT_PORT_TYPE
q[23] <= d[23].DB_MAX_OUTPUT_PORT_TYPE
q[24] <= d[24].DB_MAX_OUTPUT_PORT_TYPE
q[25] <= d[25].DB_MAX_OUTPUT_PORT_TYPE
q[26] <= d[26].DB_MAX_OUTPUT_PORT_TYPE
q[27] <= d[27].DB_MAX_OUTPUT_PORT_TYPE
q[28] <= d[28].DB_MAX_OUTPUT_PORT_TYPE
q[29] <= d[29].DB_MAX_OUTPUT_PORT_TYPE
q[30] <= d[30].DB_MAX_OUTPUT_PORT_TYPE
q[31] <= d[31].DB_MAX_OUTPUT_PORT_TYPE
q[32] <= d[32].DB_MAX_OUTPUT_PORT_TYPE
q[33] <= d[33].DB_MAX_OUTPUT_PORT_TYPE


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6
accum_sload => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
aclr2 => ~NO_FANOUT~
aclr3 => ~NO_FANOUT~
addnsub1 => ~NO_FANOUT~
addnsub1_round => ~NO_FANOUT~
addnsub3 => ~NO_FANOUT~
addnsub3_round => ~NO_FANOUT~
chainin[0] => ~NO_FANOUT~
chainout_round => ~NO_FANOUT~
chainout_sat_overflow <= chainout_sat_overflow~0.DB_MAX_OUTPUT_PORT_TYPE
chainout_saturate => ~NO_FANOUT~
clock0 => mult_add_ie81:auto_generated.clock0
clock1 => ~NO_FANOUT~
clock2 => ~NO_FANOUT~
clock3 => ~NO_FANOUT~
dataa[0] => mult_add_ie81:auto_generated.dataa[0]
dataa[1] => mult_add_ie81:auto_generated.dataa[1]
dataa[2] => mult_add_ie81:auto_generated.dataa[2]
dataa[3] => mult_add_ie81:auto_generated.dataa[3]
dataa[4] => mult_add_ie81:auto_generated.dataa[4]
dataa[5] => mult_add_ie81:auto_generated.dataa[5]
dataa[6] => mult_add_ie81:auto_generated.dataa[6]
dataa[7] => mult_add_ie81:auto_generated.dataa[7]
dataa[8] => mult_add_ie81:auto_generated.dataa[8]
dataa[9] => mult_add_ie81:auto_generated.dataa[9]
dataa[10] => mult_add_ie81:auto_generated.dataa[10]
dataa[11] => mult_add_ie81:auto_generated.dataa[11]
dataa[12] => mult_add_ie81:auto_generated.dataa[12]
dataa[13] => mult_add_ie81:auto_generated.dataa[13]
dataa[14] => mult_add_ie81:auto_generated.dataa[14]
dataa[15] => mult_add_ie81:auto_generated.dataa[15]
dataa[16] => mult_add_ie81:auto_generated.dataa[16]
dataa[17] => mult_add_ie81:auto_generated.dataa[17]
datab[0] => mult_add_ie81:auto_generated.datab[0]
datab[1] => mult_add_ie81:auto_generated.datab[1]
datab[2] => mult_add_ie81:auto_generated.datab[2]
datab[3] => mult_add_ie81:auto_generated.datab[3]
datab[4] => mult_add_ie81:auto_generated.datab[4]
datab[5] => mult_add_ie81:auto_generated.datab[5]
datab[6] => mult_add_ie81:auto_generated.datab[6]
datab[7] => mult_add_ie81:auto_generated.datab[7]
datab[8] => mult_add_ie81:auto_generated.datab[8]
datab[9] => mult_add_ie81:auto_generated.datab[9]
datab[10] => mult_add_ie81:auto_generated.datab[10]
datab[11] => mult_add_ie81:auto_generated.datab[11]
datab[12] => mult_add_ie81:auto_generated.datab[12]
datab[13] => mult_add_ie81:auto_generated.datab[13]
datab[14] => mult_add_ie81:auto_generated.datab[14]
datab[15] => mult_add_ie81:auto_generated.datab[15]
datab[16] => mult_add_ie81:auto_generated.datab[16]
datab[17] => mult_add_ie81:auto_generated.datab[17]
ena0 => ~NO_FANOUT~
ena1 => ~NO_FANOUT~
ena2 => ~NO_FANOUT~
ena3 => ~NO_FANOUT~
mult01_round => ~NO_FANOUT~
mult01_saturation => ~NO_FANOUT~
mult0_is_saturated <= mult0_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE
mult1_is_saturated <= mult1_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE
mult23_round => ~NO_FANOUT~
mult23_saturation => ~NO_FANOUT~
mult2_is_saturated <= mult2_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE
mult3_is_saturated <= mult3_is_saturated~0.DB_MAX_OUTPUT_PORT_TYPE
output_round => ~NO_FANOUT~
output_saturate => ~NO_FANOUT~
overflow <= overflow~0.DB_MAX_OUTPUT_PORT_TYPE
result[0] <= mult_add_ie81:auto_generated.result[0]
result[1] <= mult_add_ie81:auto_generated.result[1]
result[2] <= mult_add_ie81:auto_generated.result[2]
result[3] <= mult_add_ie81:auto_generated.result[3]
result[4] <= mult_add_ie81:auto_generated.result[4]
result[5] <= mult_add_ie81:auto_generated.result[5]
result[6] <= mult_add_ie81:auto_generated.result[6]
result[7] <= mult_add_ie81:auto_generated.result[7]
result[8] <= mult_add_ie81:auto_generated.result[8]
result[9] <= mult_add_ie81:auto_generated.result[9]
result[10] <= mult_add_ie81:auto_generated.result[10]
result[11] <= mult_add_ie81:auto_generated.result[11]
result[12] <= mult_add_ie81:auto_generated.result[12]
result[13] <= mult_add_ie81:auto_generated.result[13]
result[14] <= mult_add_ie81:auto_generated.result[14]
result[15] <= mult_add_ie81:auto_generated.result[15]
result[16] <= mult_add_ie81:auto_generated.result[16]
result[17] <= mult_add_ie81:auto_generated.result[17]
result[18] <= mult_add_ie81:auto_generated.result[18]
result[19] <= mult_add_ie81:auto_generated.result[19]
result[20] <= mult_add_ie81:auto_generated.result[20]
result[21] <= mult_add_ie81:auto_generated.result[21]
result[22] <= mult_add_ie81:auto_generated.result[22]
result[23] <= mult_add_ie81:auto_generated.result[23]
result[24] <= mult_add_ie81:auto_generated.result[24]
result[25] <= mult_add_ie81:auto_generated.result[25]
result[26] <= mult_add_ie81:auto_generated.result[26]
result[27] <= mult_add_ie81:auto_generated.result[27]
result[28] <= mult_add_ie81:auto_generated.result[28]
result[29] <= mult_add_ie81:auto_generated.result[29]
result[30] <= mult_add_ie81:auto_generated.result[30]
result[31] <= mult_add_ie81:auto_generated.result[31]
result[32] <= mult_add_ie81:auto_generated.result[32]
result[33] <= mult_add_ie81:auto_generated.result[33]
result[34] <= mult_add_ie81:auto_generated.result[34]
result[35] <= mult_add_ie81:auto_generated.result[35]
rotate => ~NO_FANOUT~
scanina[0] => ~NO_FANOUT~
scanina[1] => ~NO_FANOUT~
scanina[2] => ~NO_FANOUT~
scanina[3] => ~NO_FANOUT~
scanina[4] => ~NO_FANOUT~
scanina[5] => ~NO_FANOUT~
scanina[6] => ~NO_FANOUT~
scanina[7] => ~NO_FANOUT~
scanina[8] => ~NO_FANOUT~
scanina[9] => ~NO_FANOUT~
scanina[10] => ~NO_FANOUT~
scanina[11] => ~NO_FANOUT~
scanina[12] => ~NO_FANOUT~
scanina[13] => ~NO_FANOUT~
scanina[14] => ~NO_FANOUT~
scanina[15] => ~NO_FANOUT~
scanina[16] => ~NO_FANOUT~
scanina[17] => ~NO_FANOUT~
scaninb[0] => ~NO_FANOUT~
scaninb[1] => ~NO_FANOUT~
scaninb[2] => ~NO_FANOUT~
scaninb[3] => ~NO_FANOUT~
scaninb[4] => ~NO_FANOUT~
scaninb[5] => ~NO_FANOUT~
scaninb[6] => ~NO_FANOUT~
scaninb[7] => ~NO_FANOUT~
scaninb[8] => ~NO_FANOUT~
scaninb[9] => ~NO_FANOUT~
scaninb[10] => ~NO_FANOUT~
scaninb[11] => ~NO_FANOUT~
scaninb[12] => ~NO_FANOUT~
scaninb[13] => ~NO_FANOUT~
scaninb[14] => ~NO_FANOUT~
scaninb[15] => ~NO_FANOUT~
scaninb[16] => ~NO_FANOUT~
scaninb[17] => ~NO_FANOUT~
scanouta[0] <= scanouta[0]~17.DB_MAX_OUTPUT_PORT_TYPE
scanouta[1] <= scanouta[1]~16.DB_MAX_OUTPUT_PORT_TYPE
scanouta[2] <= scanouta[2]~15.DB_MAX_OUTPUT_PORT_TYPE
scanouta[3] <= scanouta[3]~14.DB_MAX_OUTPUT_PORT_TYPE
scanouta[4] <= scanouta[4]~13.DB_MAX_OUTPUT_PORT_TYPE
scanouta[5] <= scanouta[5]~12.DB_MAX_OUTPUT_PORT_TYPE
scanouta[6] <= scanouta[6]~11.DB_MAX_OUTPUT_PORT_TYPE
scanouta[7] <= scanouta[7]~10.DB_MAX_OUTPUT_PORT_TYPE
scanouta[8] <= scanouta[8]~9.DB_MAX_OUTPUT_PORT_TYPE
scanouta[9] <= scanouta[9]~8.DB_MAX_OUTPUT_PORT_TYPE
scanouta[10] <= scanouta[10]~7.DB_MAX_OUTPUT_PORT_TYPE
scanouta[11] <= scanouta[11]~6.DB_MAX_OUTPUT_PORT_TYPE
scanouta[12] <= scanouta[12]~5.DB_MAX_OUTPUT_PORT_TYPE
scanouta[13] <= scanouta[13]~4.DB_MAX_OUTPUT_PORT_TYPE
scanouta[14] <= scanouta[14]~3.DB_MAX_OUTPUT_PORT_TYPE
scanouta[15] <= scanouta[15]~2.DB_MAX_OUTPUT_PORT_TYPE
scanouta[16] <= scanouta[16]~1.DB_MAX_OUTPUT_PORT_TYPE
scanouta[17] <= scanouta[17]~0.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[0] <= scanoutb[0]~17.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[1] <= scanoutb[1]~16.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[2] <= scanoutb[2]~15.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[3] <= scanoutb[3]~14.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[4] <= scanoutb[4]~13.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[5] <= scanoutb[5]~12.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[6] <= scanoutb[6]~11.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[7] <= scanoutb[7]~10.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[8] <= scanoutb[8]~9.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[9] <= scanoutb[9]~8.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[10] <= scanoutb[10]~7.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[11] <= scanoutb[11]~6.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[12] <= scanoutb[12]~5.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[13] <= scanoutb[13]~4.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[14] <= scanoutb[14]~3.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[15] <= scanoutb[15]~2.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[16] <= scanoutb[16]~1.DB_MAX_OUTPUT_PORT_TYPE
scanoutb[17] <= scanoutb[17]~0.DB_MAX_OUTPUT_PORT_TYPE
shift_right => ~NO_FANOUT~
signa => ~NO_FANOUT~
signb => ~NO_FANOUT~
sourcea[0] => ~NO_FANOUT~
sourceb[0] => ~NO_FANOUT~
zero_chainout => ~NO_FANOUT~
zero_loopback => ~NO_FANOUT~


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6|mult_add_ie81:auto_generated
clock0 => dffe2a[35].CLK
clock0 => dffe2a[34].CLK
clock0 => dffe2a[33].CLK
clock0 => dffe2a[32].CLK
clock0 => dffe2a[31].CLK
clock0 => dffe2a[30].CLK
clock0 => dffe2a[29].CLK
clock0 => dffe2a[28].CLK
clock0 => dffe2a[27].CLK
clock0 => dffe2a[26].CLK
clock0 => dffe2a[25].CLK
clock0 => dffe2a[24].CLK
clock0 => dffe2a[23].CLK
clock0 => dffe2a[22].CLK
clock0 => dffe2a[21].CLK
clock0 => dffe2a[20].CLK
clock0 => dffe2a[19].CLK
clock0 => dffe2a[18].CLK
clock0 => dffe2a[17].CLK
clock0 => dffe2a[16].CLK
clock0 => dffe2a[15].CLK
clock0 => dffe2a[14].CLK
clock0 => dffe2a[13].CLK
clock0 => dffe2a[12].CLK
clock0 => dffe2a[11].CLK
clock0 => dffe2a[10].CLK
clock0 => dffe2a[9].CLK
clock0 => dffe2a[8].CLK
clock0 => dffe2a[7].CLK
clock0 => dffe2a[6].CLK
clock0 => dffe2a[5].CLK
clock0 => dffe2a[4].CLK
clock0 => dffe2a[3].CLK
clock0 => dffe2a[2].CLK
clock0 => dffe2a[1].CLK
clock0 => dffe2a[0].CLK
dataa[0] => ded_mult_2a21:ded_mult1.dataa[0]
dataa[1] => ded_mult_2a21:ded_mult1.dataa[1]
dataa[2] => ded_mult_2a21:ded_mult1.dataa[2]
dataa[3] => ded_mult_2a21:ded_mult1.dataa[3]
dataa[4] => ded_mult_2a21:ded_mult1.dataa[4]
dataa[5] => ded_mult_2a21:ded_mult1.dataa[5]
dataa[6] => ded_mult_2a21:ded_mult1.dataa[6]
dataa[7] => ded_mult_2a21:ded_mult1.dataa[7]
dataa[8] => ded_mult_2a21:ded_mult1.dataa[8]
dataa[9] => ded_mult_2a21:ded_mult1.dataa[9]
dataa[10] => ded_mult_2a21:ded_mult1.dataa[10]
dataa[11] => ded_mult_2a21:ded_mult1.dataa[11]
dataa[12] => ded_mult_2a21:ded_mult1.dataa[12]
dataa[13] => ded_mult_2a21:ded_mult1.dataa[13]
dataa[14] => ded_mult_2a21:ded_mult1.dataa[14]
dataa[15] => ded_mult_2a21:ded_mult1.dataa[15]
dataa[16] => ded_mult_2a21:ded_mult1.dataa[16]
dataa[17] => ded_mult_2a21:ded_mult1.dataa[17]
datab[0] => ded_mult_2a21:ded_mult1.datab[0]
datab[1] => ded_mult_2a21:ded_mult1.datab[1]
datab[2] => ded_mult_2a21:ded_mult1.datab[2]
datab[3] => ded_mult_2a21:ded_mult1.datab[3]
datab[4] => ded_mult_2a21:ded_mult1.datab[4]
datab[5] => ded_mult_2a21:ded_mult1.datab[5]
datab[6] => ded_mult_2a21:ded_mult1.datab[6]
datab[7] => ded_mult_2a21:ded_mult1.datab[7]
datab[8] => ded_mult_2a21:ded_mult1.datab[8]
datab[9] => ded_mult_2a21:ded_mult1.datab[9]
datab[10] => ded_mult_2a21:ded_mult1.datab[10]
datab[11] => ded_mult_2a21:ded_mult1.datab[11]
datab[12] => ded_mult_2a21:ded_mult1.datab[12]
datab[13] => ded_mult_2a21:ded_mult1.datab[13]
datab[14] => ded_mult_2a21:ded_mult1.datab[14]
datab[15] => ded_mult_2a21:ded_mult1.datab[15]
datab[16] => ded_mult_2a21:ded_mult1.datab[16]
datab[17] => ded_mult_2a21:ded_mult1.datab[17]
result[0] <= dffe2a[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= dffe2a[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= dffe2a[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= dffe2a[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= dffe2a[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= dffe2a[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= dffe2a[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= dffe2a[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= dffe2a[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= dffe2a[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= dffe2a[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= dffe2a[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= dffe2a[12].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= dffe2a[13].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= dffe2a[14].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= dffe2a[15].DB_MAX_OUTPUT_PORT_TYPE
result[16] <= dffe2a[16].DB_MAX_OUTPUT_PORT_TYPE
result[17] <= dffe2a[17].DB_MAX_OUTPUT_PORT_TYPE
result[18] <= dffe2a[18].DB_MAX_OUTPUT_PORT_TYPE
result[19] <= dffe2a[19].DB_MAX_OUTPUT_PORT_TYPE
result[20] <= dffe2a[20].DB_MAX_OUTPUT_PORT_TYPE
result[21] <= dffe2a[21].DB_MAX_OUTPUT_PORT_TYPE
result[22] <= dffe2a[22].DB_MAX_OUTPUT_PORT_TYPE
result[23] <= dffe2a[23].DB_MAX_OUTPUT_PORT_TYPE
result[24] <= dffe2a[24].DB_MAX_OUTPUT_PORT_TYPE
result[25] <= dffe2a[25].DB_MAX_OUTPUT_PORT_TYPE
result[26] <= dffe2a[26].DB_MAX_OUTPUT_PORT_TYPE
result[27] <= dffe2a[27].DB_MAX_OUTPUT_PORT_TYPE
result[28] <= dffe2a[28].DB_MAX_OUTPUT_PORT_TYPE
result[29] <= dffe2a[29].DB_MAX_OUTPUT_PORT_TYPE
result[30] <= dffe2a[30].DB_MAX_OUTPUT_PORT_TYPE
result[31] <= dffe2a[31].DB_MAX_OUTPUT_PORT_TYPE
result[32] <= dffe2a[32].DB_MAX_OUTPUT_PORT_TYPE
result[33] <= dffe2a[33].DB_MAX_OUTPUT_PORT_TYPE
result[34] <= dffe2a[34].DB_MAX_OUTPUT_PORT_TYPE
result[35] <= dffe2a[35].DB_MAX_OUTPUT_PORT_TYPE


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6|mult_add_ie81:auto_generated|ded_mult_2a21:ded_mult1
dataa[0] => mac_mult3.DATAA
dataa[1] => mac_mult3.DATAA1
dataa[2] => mac_mult3.DATAA2
dataa[3] => mac_mult3.DATAA3
dataa[4] => mac_mult3.DATAA4
dataa[5] => mac_mult3.DATAA5
dataa[6] => mac_mult3.DATAA6
dataa[7] => mac_mult3.DATAA7
dataa[8] => mac_mult3.DATAA8
dataa[9] => mac_mult3.DATAA9
dataa[10] => mac_mult3.DATAA10
dataa[11] => mac_mult3.DATAA11
dataa[12] => mac_mult3.DATAA12
dataa[13] => mac_mult3.DATAA13
dataa[14] => mac_mult3.DATAA14
dataa[15] => mac_mult3.DATAA15
dataa[16] => mac_mult3.DATAA16
dataa[17] => mac_mult3.DATAA17
datab[0] => mac_mult3.DATAB
datab[1] => mac_mult3.DATAB1
datab[2] => mac_mult3.DATAB2
datab[3] => mac_mult3.DATAB3
datab[4] => mac_mult3.DATAB4
datab[5] => mac_mult3.DATAB5
datab[6] => mac_mult3.DATAB6
datab[7] => mac_mult3.DATAB7
datab[8] => mac_mult3.DATAB8
datab[9] => mac_mult3.DATAB9
datab[10] => mac_mult3.DATAB10
datab[11] => mac_mult3.DATAB11
datab[12] => mac_mult3.DATAB12
datab[13] => mac_mult3.DATAB13
datab[14] => mac_mult3.DATAB14
datab[15] => mac_mult3.DATAB15
datab[16] => mac_mult3.DATAB16
datab[17] => mac_mult3.DATAB17
result[0] <= dffpipe_d3c:pre_result.q[0]
result[1] <= dffpipe_d3c:pre_result.q[1]
result[2] <= dffpipe_d3c:pre_result.q[2]
result[3] <= dffpipe_d3c:pre_result.q[3]
result[4] <= dffpipe_d3c:pre_result.q[4]
result[5] <= dffpipe_d3c:pre_result.q[5]
result[6] <= dffpipe_d3c:pre_result.q[6]
result[7] <= dffpipe_d3c:pre_result.q[7]
result[8] <= dffpipe_d3c:pre_result.q[8]
result[9] <= dffpipe_d3c:pre_result.q[9]
result[10] <= dffpipe_d3c:pre_result.q[10]
result[11] <= dffpipe_d3c:pre_result.q[11]
result[12] <= dffpipe_d3c:pre_result.q[12]
result[13] <= dffpipe_d3c:pre_result.q[13]
result[14] <= dffpipe_d3c:pre_result.q[14]
result[15] <= dffpipe_d3c:pre_result.q[15]
result[16] <= dffpipe_d3c:pre_result.q[16]
result[17] <= dffpipe_d3c:pre_result.q[17]
result[18] <= dffpipe_d3c:pre_result.q[18]
result[19] <= dffpipe_d3c:pre_result.q[19]
result[20] <= dffpipe_d3c:pre_result.q[20]
result[21] <= dffpipe_d3c:pre_result.q[21]
result[22] <= dffpipe_d3c:pre_result.q[22]
result[23] <= dffpipe_d3c:pre_result.q[23]
result[24] <= dffpipe_d3c:pre_result.q[24]
result[25] <= dffpipe_d3c:pre_result.q[25]
result[26] <= dffpipe_d3c:pre_result.q[26]
result[27] <= dffpipe_d3c:pre_result.q[27]
result[28] <= dffpipe_d3c:pre_result.q[28]
result[29] <= dffpipe_d3c:pre_result.q[29]
result[30] <= dffpipe_d3c:pre_result.q[30]
result[31] <= dffpipe_d3c:pre_result.q[31]
result[32] <= dffpipe_d3c:pre_result.q[32]
result[33] <= dffpipe_d3c:pre_result.q[33]
result[34] <= dffpipe_d3c:pre_result.q[34]
result[35] <= dffpipe_d3c:pre_result.q[35]


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6|mult_add_ie81:auto_generated|ded_mult_2a21:ded_mult1|dffpipe_d3c:pre_result
d[0] => q[0].DATAIN
d[1] => q[1].DATAIN
d[2] => q[2].DATAIN
d[3] => q[3].DATAIN
d[4] => q[4].DATAIN
d[5] => q[5].DATAIN
d[6] => q[6].DATAIN
d[7] => q[7].DATAIN
d[8] => q[8].DATAIN
d[9] => q[9].DATAIN
d[10] => q[10].DATAIN
d[11] => q[11].DATAIN
d[12] => q[12].DATAIN
d[13] => q[13].DATAIN
d[14] => q[14].DATAIN
d[15] => q[15].DATAIN
d[16] => q[16].DATAIN
d[17] => q[17].DATAIN
d[18] => q[18].DATAIN
d[19] => q[19].DATAIN
d[20] => q[20].DATAIN
d[21] => q[21].DATAIN
d[22] => q[22].DATAIN
d[23] => q[23].DATAIN
d[24] => q[24].DATAIN
d[25] => q[25].DATAIN
d[26] => q[26].DATAIN
d[27] => q[27].DATAIN
d[28] => q[28].DATAIN
d[29] => q[29].DATAIN
d[30] => q[30].DATAIN
d[31] => q[31].DATAIN
d[32] => q[32].DATAIN
d[33] => q[33].DATAIN
d[34] => q[34].DATAIN
d[35] => q[35].DATAIN
q[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= d[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= d[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= d[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= d[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= d[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= d[12].DB_MAX_OUTPUT_PORT_TYPE
q[13] <= d[13].DB_MAX_OUTPUT_PORT_TYPE
q[14] <= d[14].DB_MAX_OUTPUT_PORT_TYPE
q[15] <= d[15].DB_MAX_OUTPUT_PORT_TYPE
q[16] <= d[16].DB_MAX_OUTPUT_PORT_TYPE
q[17] <= d[17].DB_MAX_OUTPUT_PORT_TYPE
q[18] <= d[18].DB_MAX_OUTPUT_PORT_TYPE
q[19] <= d[19].DB_MAX_OUTPUT_PORT_TYPE
q[20] <= d[20].DB_MAX_OUTPUT_PORT_TYPE
q[21] <= d[21].DB_MAX_OUTPUT_PORT_TYPE
q[22] <= d[22].DB_MAX_OUTPUT_PORT_TYPE
q[23] <= d[23].DB_MAX_OUTPUT_PORT_TYPE
q[24] <= d[24].DB_MAX_OUTPUT_PORT_TYPE
q[25] <= d[25].DB_MAX_OUTPUT_PORT_TYPE
q[26] <= d[26].DB_MAX_OUTPUT_PORT_TYPE
q[27] <= d[27].DB_MAX_OUTPUT_PORT_TYPE
q[28] <= d[28].DB_MAX_OUTPUT_PORT_TYPE
q[29] <= d[29].DB_MAX_OUTPUT_PORT_TYPE
q[30] <= d[30].DB_MAX_OUTPUT_PORT_TYPE
q[31] <= d[31].DB_MAX_OUTPUT_PORT_TYPE
q[32] <= d[32].DB_MAX_OUTPUT_PORT_TYPE
q[33] <= d[33].DB_MAX_OUTPUT_PORT_TYPE
q[34] <= d[34].DB_MAX_OUTPUT_PORT_TYPE
q[35] <= d[35].DB_MAX_OUTPUT_PORT_TYPE


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:add_sub7
dataa[0] => add_sub_esf:auto_generated.dataa[0]
dataa[1] => add_sub_esf:auto_generated.dataa[1]
dataa[2] => add_sub_esf:auto_generated.dataa[2]
dataa[3] => add_sub_esf:auto_generated.dataa[3]
dataa[4] => add_sub_esf:auto_generated.dataa[4]
dataa[5] => add_sub_esf:auto_generated.dataa[5]
dataa[6] => add_sub_esf:auto_generated.dataa[6]
dataa[7] => add_sub_esf:auto_generated.dataa[7]
dataa[8] => add_sub_esf:auto_generated.dataa[8]
dataa[9] => add_sub_esf:auto_generated.dataa[9]
dataa[10] => add_sub_esf:auto_generated.dataa[10]
dataa[11] => add_sub_esf:auto_generated.dataa[11]
dataa[12] => add_sub_esf:auto_generated.dataa[12]
dataa[13] => add_sub_esf:auto_generated.dataa[13]
dataa[14] => add_sub_esf:auto_generated.dataa[14]
dataa[15] => add_sub_esf:auto_generated.dataa[15]
dataa[16] => add_sub_esf:auto_generated.dataa[16]
dataa[17] => add_sub_esf:auto_generated.dataa[17]
dataa[18] => add_sub_esf:auto_generated.dataa[18]
dataa[19] => add_sub_esf:auto_generated.dataa[19]
dataa[20] => add_sub_esf:auto_generated.dataa[20]
dataa[21] => add_sub_esf:auto_generated.dataa[21]
dataa[22] => add_sub_esf:auto_generated.dataa[22]
dataa[23] => add_sub_esf:auto_generated.dataa[23]
dataa[24] => add_sub_esf:auto_generated.dataa[24]
dataa[25] => add_sub_esf:auto_generated.dataa[25]
dataa[26] => add_sub_esf:auto_generated.dataa[26]
dataa[27] => add_sub_esf:auto_generated.dataa[27]
dataa[28] => add_sub_esf:auto_generated.dataa[28]
dataa[29] => add_sub_esf:auto_generated.dataa[29]
dataa[30] => add_sub_esf:auto_generated.dataa[30]
dataa[31] => add_sub_esf:auto_generated.dataa[31]
dataa[32] => add_sub_esf:auto_generated.dataa[32]
dataa[33] => add_sub_esf:auto_generated.dataa[33]
dataa[34] => add_sub_esf:auto_generated.dataa[34]
datab[0] => add_sub_esf:auto_generated.datab[0]
datab[1] => add_sub_esf:auto_generated.datab[1]
datab[2] => add_sub_esf:auto_generated.datab[2]
datab[3] => add_sub_esf:auto_generated.datab[3]
datab[4] => add_sub_esf:auto_generated.datab[4]
datab[5] => add_sub_esf:auto_generated.datab[5]
datab[6] => add_sub_esf:auto_generated.datab[6]
datab[7] => add_sub_esf:auto_generated.datab[7]
datab[8] => add_sub_esf:auto_generated.datab[8]
datab[9] => add_sub_esf:auto_generated.datab[9]
datab[10] => add_sub_esf:auto_generated.datab[10]
datab[11] => add_sub_esf:auto_generated.datab[11]
datab[12] => add_sub_esf:auto_generated.datab[12]
datab[13] => add_sub_esf:auto_generated.datab[13]
datab[14] => add_sub_esf:auto_generated.datab[14]
datab[15] => add_sub_esf:auto_generated.datab[15]
datab[16] => add_sub_esf:auto_generated.datab[16]
datab[17] => add_sub_esf:auto_generated.datab[17]
datab[18] => add_sub_esf:auto_generated.datab[18]
datab[19] => add_sub_esf:auto_generated.datab[19]
datab[20] => add_sub_esf:auto_generated.datab[20]
datab[21] => add_sub_esf:auto_generated.datab[21]
datab[22] => add_sub_esf:auto_generated.datab[22]
datab[23] => add_sub_esf:auto_generated.datab[23]
datab[24] => add_sub_esf:auto_generated.datab[24]
datab[25] => add_sub_esf:auto_generated.datab[25]
datab[26] => add_sub_esf:auto_generated.datab[26]
datab[27] => add_sub_esf:auto_generated.datab[27]
datab[28] => add_sub_esf:auto_generated.datab[28]
datab[29] => add_sub_esf:auto_generated.datab[29]
datab[30] => add_sub_esf:auto_generated.datab[30]
datab[31] => add_sub_esf:auto_generated.datab[31]
datab[32] => add_sub_esf:auto_generated.datab[32]
datab[33] => add_sub_esf:auto_generated.datab[33]
datab[34] => add_sub_esf:auto_generated.datab[34]
cin => ~NO_FANOUT~
add_sub => ~NO_FANOUT~
clock => add_sub_esf:auto_generated.clock
aclr => add_sub_esf:auto_generated.aclr
clken => add_sub_esf:auto_generated.clken
result[0] <= add_sub_esf:auto_generated.result[0]
result[1] <= add_sub_esf:auto_generated.result[1]
result[2] <= add_sub_esf:auto_generated.result[2]
result[3] <= add_sub_esf:auto_generated.result[3]
result[4] <= add_sub_esf:auto_generated.result[4]
result[5] <= add_sub_esf:auto_generated.result[5]
result[6] <= add_sub_esf:auto_generated.result[6]
result[7] <= add_sub_esf:auto_generated.result[7]
result[8] <= add_sub_esf:auto_generated.result[8]
result[9] <= add_sub_esf:auto_generated.result[9]
result[10] <= add_sub_esf:auto_generated.result[10]
result[11] <= add_sub_esf:auto_generated.result[11]
result[12] <= add_sub_esf:auto_generated.result[12]
result[13] <= add_sub_esf:auto_generated.result[13]
result[14] <= add_sub_esf:auto_generated.result[14]
result[15] <= add_sub_esf:auto_generated.result[15]
result[16] <= add_sub_esf:auto_generated.result[16]
result[17] <= add_sub_esf:auto_generated.result[17]
result[18] <= add_sub_esf:auto_generated.result[18]
result[19] <= add_sub_esf:auto_generated.result[19]
result[20] <= add_sub_esf:auto_generated.result[20]
result[21] <= add_sub_esf:auto_generated.result[21]
result[22] <= add_sub_esf:auto_generated.result[22]
result[23] <= add_sub_esf:auto_generated.result[23]
result[24] <= add_sub_esf:auto_generated.result[24]
result[25] <= add_sub_esf:auto_generated.result[25]
result[26] <= add_sub_esf:auto_generated.result[26]
result[27] <= add_sub_esf:auto_generated.result[27]
result[28] <= add_sub_esf:auto_generated.result[28]
result[29] <= add_sub_esf:auto_generated.result[29]
result[30] <= add_sub_esf:auto_generated.result[30]
result[31] <= add_sub_esf:auto_generated.result[31]
result[32] <= add_sub_esf:auto_generated.result[32]
result[33] <= add_sub_esf:auto_generated.result[33]
result[34] <= add_sub_esf:auto_generated.result[34]
cout <= <GND>
overflow <= <GND>


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:add_sub7|add_sub_esf:auto_generated
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
clock => pipeline_dffe[34].CLK
clock => pipeline_dffe[33].CLK
clock => pipeline_dffe[32].CLK
clock => pipeline_dffe[31].CLK
clock => pipeline_dffe[30].CLK
clock => pipeline_dffe[29].CLK
clock => pipeline_dffe[28].CLK
clock => pipeline_dffe[27].CLK
clock => pipeline_dffe[26].CLK
clock => pipeline_dffe[25].CLK
clock => pipeline_dffe[24].CLK
clock => pipeline_dffe[23].CLK
clock => pipeline_dffe[22].CLK
clock => pipeline_dffe[21].CLK
clock => pipeline_dffe[20].CLK
clock => pipeline_dffe[19].CLK
clock => pipeline_dffe[18].CLK
clock => pipeline_dffe[17].CLK
clock => pipeline_dffe[16].CLK
clock => pipeline_dffe[15].CLK
clock => pipeline_dffe[14].CLK
clock => pipeline_dffe[13].CLK
clock => pipeline_dffe[12].CLK
clock => pipeline_dffe[11].CLK
clock => pipeline_dffe[10].CLK
clock => pipeline_dffe[9].CLK
clock => pipeline_dffe[8].CLK
clock => pipeline_dffe[7].CLK
clock => pipeline_dffe[6].CLK
clock => pipeline_dffe[5].CLK
clock => pipeline_dffe[4].CLK
clock => pipeline_dffe[3].CLK
clock => pipeline_dffe[2].CLK
clock => pipeline_dffe[1].CLK
clock => pipeline_dffe[0].CLK
dataa[0] => op_1.IN68
dataa[1] => op_1.IN66
dataa[2] => op_1.IN64
dataa[3] => op_1.IN62
dataa[4] => op_1.IN60
dataa[5] => op_1.IN58
dataa[6] => op_1.IN56
dataa[7] => op_1.IN54
dataa[8] => op_1.IN52
dataa[9] => op_1.IN50
dataa[10] => op_1.IN48
dataa[11] => op_1.IN46
dataa[12] => op_1.IN44
dataa[13] => op_1.IN42
dataa[14] => op_1.IN40
dataa[15] => op_1.IN38
dataa[16] => op_1.IN36
dataa[17] => op_1.IN34
dataa[18] => op_1.IN32
dataa[19] => op_1.IN30
dataa[20] => op_1.IN28
dataa[21] => op_1.IN26
dataa[22] => op_1.IN24
dataa[23] => op_1.IN22
dataa[24] => op_1.IN20
dataa[25] => op_1.IN18
dataa[26] => op_1.IN16
dataa[27] => op_1.IN14
dataa[28] => op_1.IN12
dataa[29] => op_1.IN10
dataa[30] => op_1.IN8
dataa[31] => op_1.IN6
dataa[32] => op_1.IN4
dataa[33] => op_1.IN2
dataa[34] => op_1.IN0
datab[0] => op_1.IN69
datab[1] => op_1.IN67
datab[2] => op_1.IN65
datab[3] => op_1.IN63
datab[4] => op_1.IN61
datab[5] => op_1.IN59
datab[6] => op_1.IN57
datab[7] => op_1.IN55
datab[8] => op_1.IN53
datab[9] => op_1.IN51
datab[10] => op_1.IN49
datab[11] => op_1.IN47
datab[12] => op_1.IN45
datab[13] => op_1.IN43
datab[14] => op_1.IN41
datab[15] => op_1.IN39
datab[16] => op_1.IN37
datab[17] => op_1.IN35
datab[18] => op_1.IN33
datab[19] => op_1.IN31
datab[20] => op_1.IN29
datab[21] => op_1.IN27
datab[22] => op_1.IN25
datab[23] => op_1.IN23
datab[24] => op_1.IN21
datab[25] => op_1.IN19
datab[26] => op_1.IN17
datab[27] => op_1.IN15
datab[28] => op_1.IN13
datab[29] => op_1.IN11
datab[30] => op_1.IN9
datab[31] => op_1.IN7
datab[32] => op_1.IN5
datab[33] => op_1.IN3
datab[34] => op_1.IN1
result[0] <= pipeline_dffe[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= pipeline_dffe[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= pipeline_dffe[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= pipeline_dffe[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= pipeline_dffe[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= pipeline_dffe[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= pipeline_dffe[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= pipeline_dffe[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= pipeline_dffe[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= pipeline_dffe[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= pipeline_dffe[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= pipeline_dffe[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= pipeline_dffe[12].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= pipeline_dffe[13].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= pipeline_dffe[14].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= pipeline_dffe[15].DB_MAX_OUTPUT_PORT_TYPE
result[16] <= pipeline_dffe[16].DB_MAX_OUTPUT_PORT_TYPE
result[17] <= pipeline_dffe[17].DB_MAX_OUTPUT_PORT_TYPE
result[18] <= pipeline_dffe[18].DB_MAX_OUTPUT_PORT_TYPE
result[19] <= pipeline_dffe[19].DB_MAX_OUTPUT_PORT_TYPE
result[20] <= pipeline_dffe[20].DB_MAX_OUTPUT_PORT_TYPE
result[21] <= pipeline_dffe[21].DB_MAX_OUTPUT_PORT_TYPE
result[22] <= pipeline_dffe[22].DB_MAX_OUTPUT_PORT_TYPE
result[23] <= pipeline_dffe[23].DB_MAX_OUTPUT_PORT_TYPE
result[24] <= pipeline_dffe[24].DB_MAX_OUTPUT_PORT_TYPE
result[25] <= pipeline_dffe[25].DB_MAX_OUTPUT_PORT_TYPE
result[26] <= pipeline_dffe[26].DB_MAX_OUTPUT_PORT_TYPE
result[27] <= pipeline_dffe[27].DB_MAX_OUTPUT_PORT_TYPE
result[28] <= pipeline_dffe[28].DB_MAX_OUTPUT_PORT_TYPE
result[29] <= pipeline_dffe[29].DB_MAX_OUTPUT_PORT_TYPE
result[30] <= pipeline_dffe[30].DB_MAX_OUTPUT_PORT_TYPE
result[31] <= pipeline_dffe[31].DB_MAX_OUTPUT_PORT_TYPE
result[32] <= pipeline_dffe[32].DB_MAX_OUTPUT_PORT_TYPE
result[33] <= pipeline_dffe[33].DB_MAX_OUTPUT_PORT_TYPE
result[34] <= pipeline_dffe[34].DB_MAX_OUTPUT_PORT_TYPE


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder1
dataa[0] => add_sub_5ii:auto_generated.dataa[0]
dataa[1] => add_sub_5ii:auto_generated.dataa[1]
dataa[2] => add_sub_5ii:auto_generated.dataa[2]
dataa[3] => add_sub_5ii:auto_generated.dataa[3]
dataa[4] => add_sub_5ii:auto_generated.dataa[4]
dataa[5] => add_sub_5ii:auto_generated.dataa[5]
dataa[6] => add_sub_5ii:auto_generated.dataa[6]
dataa[7] => add_sub_5ii:auto_generated.dataa[7]
dataa[8] => add_sub_5ii:auto_generated.dataa[8]
dataa[9] => add_sub_5ii:auto_generated.dataa[9]
dataa[10] => add_sub_5ii:auto_generated.dataa[10]
dataa[11] => add_sub_5ii:auto_generated.dataa[11]
dataa[12] => add_sub_5ii:auto_generated.dataa[12]
dataa[13] => add_sub_5ii:auto_generated.dataa[13]
dataa[14] => add_sub_5ii:auto_generated.dataa[14]
dataa[15] => add_sub_5ii:auto_generated.dataa[15]
dataa[16] => add_sub_5ii:auto_generated.dataa[16]
dataa[17] => add_sub_5ii:auto_generated.dataa[17]
datab[0] => add_sub_5ii:auto_generated.datab[0]
datab[1] => add_sub_5ii:auto_generated.datab[1]
datab[2] => add_sub_5ii:auto_generated.datab[2]
datab[3] => add_sub_5ii:auto_generated.datab[3]
datab[4] => add_sub_5ii:auto_generated.datab[4]
datab[5] => add_sub_5ii:auto_generated.datab[5]
datab[6] => add_sub_5ii:auto_generated.datab[6]
datab[7] => add_sub_5ii:auto_generated.datab[7]
datab[8] => add_sub_5ii:auto_generated.datab[8]
datab[9] => add_sub_5ii:auto_generated.datab[9]
datab[10] => add_sub_5ii:auto_generated.datab[10]
datab[11] => add_sub_5ii:auto_generated.datab[11]
datab[12] => add_sub_5ii:auto_generated.datab[12]
datab[13] => add_sub_5ii:auto_generated.datab[13]
datab[14] => add_sub_5ii:auto_generated.datab[14]
datab[15] => add_sub_5ii:auto_generated.datab[15]
datab[16] => add_sub_5ii:auto_generated.datab[16]
datab[17] => add_sub_5ii:auto_generated.datab[17]
cin => ~NO_FANOUT~
add_sub => ~NO_FANOUT~
clock => add_sub_5ii:auto_generated.clock
aclr => add_sub_5ii:auto_generated.aclr
clken => add_sub_5ii:auto_generated.clken
result[0] <= add_sub_5ii:auto_generated.result[0]
result[1] <= add_sub_5ii:auto_generated.result[1]
result[2] <= add_sub_5ii:auto_generated.result[2]
result[3] <= add_sub_5ii:auto_generated.result[3]
result[4] <= add_sub_5ii:auto_generated.result[4]
result[5] <= add_sub_5ii:auto_generated.result[5]
result[6] <= add_sub_5ii:auto_generated.result[6]
result[7] <= add_sub_5ii:auto_generated.result[7]
result[8] <= add_sub_5ii:auto_generated.result[8]
result[9] <= add_sub_5ii:auto_generated.result[9]
result[10] <= add_sub_5ii:auto_generated.result[10]
result[11] <= add_sub_5ii:auto_generated.result[11]
result[12] <= add_sub_5ii:auto_generated.result[12]
result[13] <= add_sub_5ii:auto_generated.result[13]
result[14] <= add_sub_5ii:auto_generated.result[14]
result[15] <= add_sub_5ii:auto_generated.result[15]
result[16] <= add_sub_5ii:auto_generated.result[16]
result[17] <= add_sub_5ii:auto_generated.result[17]
cout <= <GND>
overflow <= <GND>


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder1|add_sub_5ii:auto_generated
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
clock => pipeline_dffe[17].CLK
clock => pipeline_dffe[16].CLK
clock => pipeline_dffe[15].CLK
clock => pipeline_dffe[14].CLK
clock => pipeline_dffe[13].CLK
clock => pipeline_dffe[12].CLK
clock => pipeline_dffe[11].CLK
clock => pipeline_dffe[10].CLK
clock => pipeline_dffe[9].CLK
clock => pipeline_dffe[8].CLK
clock => pipeline_dffe[7].CLK
clock => pipeline_dffe[6].CLK
clock => pipeline_dffe[5].CLK
clock => pipeline_dffe[4].CLK
clock => pipeline_dffe[3].CLK
clock => pipeline_dffe[2].CLK
clock => pipeline_dffe[1].CLK
clock => pipeline_dffe[0].CLK
dataa[0] => op_1.IN34
dataa[1] => op_1.IN32
dataa[2] => op_1.IN30
dataa[3] => op_1.IN28
dataa[4] => op_1.IN26
dataa[5] => op_1.IN24
dataa[6] => op_1.IN22
dataa[7] => op_1.IN20
dataa[8] => op_1.IN18
dataa[9] => op_1.IN16
dataa[10] => op_1.IN14
dataa[11] => op_1.IN12
dataa[12] => op_1.IN10
dataa[13] => op_1.IN8
dataa[14] => op_1.IN6
dataa[15] => op_1.IN4
dataa[16] => op_1.IN2
dataa[17] => op_1.IN0
datab[0] => op_1.IN35
datab[1] => op_1.IN33
datab[2] => op_1.IN31
datab[3] => op_1.IN29
datab[4] => op_1.IN27
datab[5] => op_1.IN25
datab[6] => op_1.IN23
datab[7] => op_1.IN21
datab[8] => op_1.IN19
datab[9] => op_1.IN17
datab[10] => op_1.IN15
datab[11] => op_1.IN13
datab[12] => op_1.IN11
datab[13] => op_1.IN9
datab[14] => op_1.IN7
datab[15] => op_1.IN5
datab[16] => op_1.IN3
datab[17] => op_1.IN1
result[0] <= pipeline_dffe[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= pipeline_dffe[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= pipeline_dffe[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= pipeline_dffe[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= pipeline_dffe[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= pipeline_dffe[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= pipeline_dffe[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= pipeline_dffe[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= pipeline_dffe[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= pipeline_dffe[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= pipeline_dffe[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= pipeline_dffe[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= pipeline_dffe[12].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= pipeline_dffe[13].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= pipeline_dffe[14].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= pipeline_dffe[15].DB_MAX_OUTPUT_PORT_TYPE
result[16] <= pipeline_dffe[16].DB_MAX_OUTPUT_PORT_TYPE
result[17] <= pipeline_dffe[17].DB_MAX_OUTPUT_PORT_TYPE


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder2
dataa[0] => add_sub_6ii:auto_generated.dataa[0]
dataa[1] => add_sub_6ii:auto_generated.dataa[1]
dataa[2] => add_sub_6ii:auto_generated.dataa[2]
dataa[3] => add_sub_6ii:auto_generated.dataa[3]
dataa[4] => add_sub_6ii:auto_generated.dataa[4]
dataa[5] => add_sub_6ii:auto_generated.dataa[5]
dataa[6] => add_sub_6ii:auto_generated.dataa[6]
dataa[7] => add_sub_6ii:auto_generated.dataa[7]
dataa[8] => add_sub_6ii:auto_generated.dataa[8]
dataa[9] => add_sub_6ii:auto_generated.dataa[9]
dataa[10] => add_sub_6ii:auto_generated.dataa[10]
dataa[11] => add_sub_6ii:auto_generated.dataa[11]
dataa[12] => add_sub_6ii:auto_generated.dataa[12]
dataa[13] => add_sub_6ii:auto_generated.dataa[13]
dataa[14] => add_sub_6ii:auto_generated.dataa[14]
dataa[15] => add_sub_6ii:auto_generated.dataa[15]
dataa[16] => add_sub_6ii:auto_generated.dataa[16]
dataa[17] => add_sub_6ii:auto_generated.dataa[17]
dataa[18] => add_sub_6ii:auto_generated.dataa[18]
dataa[19] => add_sub_6ii:auto_generated.dataa[19]
dataa[20] => add_sub_6ii:auto_generated.dataa[20]
dataa[21] => add_sub_6ii:auto_generated.dataa[21]
dataa[22] => add_sub_6ii:auto_generated.dataa[22]
dataa[23] => add_sub_6ii:auto_generated.dataa[23]
dataa[24] => add_sub_6ii:auto_generated.dataa[24]
dataa[25] => add_sub_6ii:auto_generated.dataa[25]
dataa[26] => add_sub_6ii:auto_generated.dataa[26]
dataa[27] => add_sub_6ii:auto_generated.dataa[27]
dataa[28] => add_sub_6ii:auto_generated.dataa[28]
dataa[29] => add_sub_6ii:auto_generated.dataa[29]
dataa[30] => add_sub_6ii:auto_generated.dataa[30]
dataa[31] => add_sub_6ii:auto_generated.dataa[31]
dataa[32] => add_sub_6ii:auto_generated.dataa[32]
dataa[33] => add_sub_6ii:auto_generated.dataa[33]
dataa[34] => add_sub_6ii:auto_generated.dataa[34]
datab[0] => add_sub_6ii:auto_generated.datab[0]
datab[1] => add_sub_6ii:auto_generated.datab[1]
datab[2] => add_sub_6ii:auto_generated.datab[2]
datab[3] => add_sub_6ii:auto_generated.datab[3]
datab[4] => add_sub_6ii:auto_generated.datab[4]
datab[5] => add_sub_6ii:auto_generated.datab[5]
datab[6] => add_sub_6ii:auto_generated.datab[6]
datab[7] => add_sub_6ii:auto_generated.datab[7]
datab[8] => add_sub_6ii:auto_generated.datab[8]
datab[9] => add_sub_6ii:auto_generated.datab[9]
datab[10] => add_sub_6ii:auto_generated.datab[10]
datab[11] => add_sub_6ii:auto_generated.datab[11]
datab[12] => add_sub_6ii:auto_generated.datab[12]
datab[13] => add_sub_6ii:auto_generated.datab[13]
datab[14] => add_sub_6ii:auto_generated.datab[14]
datab[15] => add_sub_6ii:auto_generated.datab[15]
datab[16] => add_sub_6ii:auto_generated.datab[16]
datab[17] => add_sub_6ii:auto_generated.datab[17]
datab[18] => add_sub_6ii:auto_generated.datab[18]
datab[19] => add_sub_6ii:auto_generated.datab[19]
datab[20] => add_sub_6ii:auto_generated.datab[20]
datab[21] => add_sub_6ii:auto_generated.datab[21]
datab[22] => add_sub_6ii:auto_generated.datab[22]
datab[23] => add_sub_6ii:auto_generated.datab[23]
datab[24] => add_sub_6ii:auto_generated.datab[24]
datab[25] => add_sub_6ii:auto_generated.datab[25]
datab[26] => add_sub_6ii:auto_generated.datab[26]
datab[27] => add_sub_6ii:auto_generated.datab[27]
datab[28] => add_sub_6ii:auto_generated.datab[28]
datab[29] => add_sub_6ii:auto_generated.datab[29]
datab[30] => add_sub_6ii:auto_generated.datab[30]
datab[31] => add_sub_6ii:auto_generated.datab[31]
datab[32] => add_sub_6ii:auto_generated.datab[32]
datab[33] => add_sub_6ii:auto_generated.datab[33]
datab[34] => add_sub_6ii:auto_generated.datab[34]
cin => ~NO_FANOUT~
add_sub => ~NO_FANOUT~
clock => add_sub_6ii:auto_generated.clock
aclr => add_sub_6ii:auto_generated.aclr
clken => add_sub_6ii:auto_generated.clken
result[0] <= add_sub_6ii:auto_generated.result[0]
result[1] <= add_sub_6ii:auto_generated.result[1]
result[2] <= add_sub_6ii:auto_generated.result[2]
result[3] <= add_sub_6ii:auto_generated.result[3]
result[4] <= add_sub_6ii:auto_generated.result[4]
result[5] <= add_sub_6ii:auto_generated.result[5]
result[6] <= add_sub_6ii:auto_generated.result[6]
result[7] <= add_sub_6ii:auto_generated.result[7]
result[8] <= add_sub_6ii:auto_generated.result[8]
result[9] <= add_sub_6ii:auto_generated.result[9]
result[10] <= add_sub_6ii:auto_generated.result[10]
result[11] <= add_sub_6ii:auto_generated.result[11]
result[12] <= add_sub_6ii:auto_generated.result[12]
result[13] <= add_sub_6ii:auto_generated.result[13]
result[14] <= add_sub_6ii:auto_generated.result[14]
result[15] <= add_sub_6ii:auto_generated.result[15]
result[16] <= add_sub_6ii:auto_generated.result[16]
result[17] <= add_sub_6ii:auto_generated.result[17]
result[18] <= add_sub_6ii:auto_generated.result[18]
result[19] <= add_sub_6ii:auto_generated.result[19]
result[20] <= add_sub_6ii:auto_generated.result[20]
result[21] <= add_sub_6ii:auto_generated.result[21]
result[22] <= add_sub_6ii:auto_generated.result[22]
result[23] <= add_sub_6ii:auto_generated.result[23]
result[24] <= add_sub_6ii:auto_generated.result[24]
result[25] <= add_sub_6ii:auto_generated.result[25]
result[26] <= add_sub_6ii:auto_generated.result[26]
result[27] <= add_sub_6ii:auto_generated.result[27]
result[28] <= add_sub_6ii:auto_generated.result[28]
result[29] <= add_sub_6ii:auto_generated.result[29]
result[30] <= add_sub_6ii:auto_generated.result[30]
result[31] <= add_sub_6ii:auto_generated.result[31]
result[32] <= add_sub_6ii:auto_generated.result[32]
result[33] <= add_sub_6ii:auto_generated.result[33]
result[34] <= add_sub_6ii:auto_generated.result[34]
cout <= <GND>
overflow <= <GND>


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder2|add_sub_6ii:auto_generated
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
clock => pipeline_dffe[69].CLK
clock => pipeline_dffe[68].CLK
clock => pipeline_dffe[67].CLK
clock => pipeline_dffe[66].CLK
clock => pipeline_dffe[65].CLK
clock => pipeline_dffe[64].CLK
clock => pipeline_dffe[63].CLK
clock => pipeline_dffe[62].CLK
clock => pipeline_dffe[61].CLK
clock => pipeline_dffe[60].CLK
clock => pipeline_dffe[59].CLK
clock => pipeline_dffe[58].CLK
clock => pipeline_dffe[57].CLK
clock => pipeline_dffe[56].CLK
clock => pipeline_dffe[55].CLK
clock => pipeline_dffe[54].CLK
clock => pipeline_dffe[53].CLK
clock => pipeline_dffe[52].CLK
clock => pipeline_dffe[51].CLK
clock => pipeline_dffe[50].CLK
clock => pipeline_dffe[49].CLK
clock => pipeline_dffe[48].CLK
clock => pipeline_dffe[47].CLK
clock => pipeline_dffe[46].CLK
clock => pipeline_dffe[45].CLK
clock => pipeline_dffe[44].CLK
clock => pipeline_dffe[43].CLK
clock => pipeline_dffe[42].CLK
clock => pipeline_dffe[41].CLK
clock => pipeline_dffe[40].CLK
clock => pipeline_dffe[39].CLK
clock => pipeline_dffe[38].CLK
clock => pipeline_dffe[37].CLK
clock => pipeline_dffe[36].CLK
clock => pipeline_dffe[35].CLK
clock => pipeline_dffe[34].CLK
clock => pipeline_dffe[33].CLK
clock => pipeline_dffe[32].CLK
clock => pipeline_dffe[31].CLK
clock => pipeline_dffe[30].CLK
clock => pipeline_dffe[29].CLK
clock => pipeline_dffe[28].CLK
clock => pipeline_dffe[27].CLK
clock => pipeline_dffe[26].CLK
clock => pipeline_dffe[25].CLK
clock => pipeline_dffe[24].CLK
clock => pipeline_dffe[23].CLK
clock => pipeline_dffe[22].CLK
clock => pipeline_dffe[21].CLK
clock => pipeline_dffe[20].CLK
clock => pipeline_dffe[19].CLK
clock => pipeline_dffe[18].CLK
clock => pipeline_dffe[17].CLK
clock => pipeline_dffe[16].CLK
clock => pipeline_dffe[15].CLK
clock => pipeline_dffe[14].CLK
clock => pipeline_dffe[13].CLK
clock => pipeline_dffe[12].CLK
clock => pipeline_dffe[11].CLK
clock => pipeline_dffe[10].CLK
clock => pipeline_dffe[9].CLK
clock => pipeline_dffe[8].CLK
clock => pipeline_dffe[7].CLK
clock => pipeline_dffe[6].CLK
clock => pipeline_dffe[5].CLK
clock => pipeline_dffe[4].CLK
clock => pipeline_dffe[3].CLK
clock => pipeline_dffe[2].CLK
clock => pipeline_dffe[1].CLK
clock => pipeline_dffe[0].CLK
dataa[0] => op_1.IN68
dataa[1] => op_1.IN66
dataa[2] => op_1.IN64
dataa[3] => op_1.IN62
dataa[4] => op_1.IN60
dataa[5] => op_1.IN58
dataa[6] => op_1.IN56
dataa[7] => op_1.IN54
dataa[8] => op_1.IN52
dataa[9] => op_1.IN50
dataa[10] => op_1.IN48
dataa[11] => op_1.IN46
dataa[12] => op_1.IN44
dataa[13] => op_1.IN42
dataa[14] => op_1.IN40
dataa[15] => op_1.IN38
dataa[16] => op_1.IN36
dataa[17] => op_1.IN34
dataa[18] => op_1.IN32
dataa[19] => op_1.IN30
dataa[20] => op_1.IN28
dataa[21] => op_1.IN26
dataa[22] => op_1.IN24
dataa[23] => op_1.IN22
dataa[24] => op_1.IN20
dataa[25] => op_1.IN18
dataa[26] => op_1.IN16
dataa[27] => op_1.IN14
dataa[28] => op_1.IN12
dataa[29] => op_1.IN10
dataa[30] => op_1.IN8
dataa[31] => op_1.IN6
dataa[32] => op_1.IN4
dataa[33] => op_1.IN2
dataa[34] => op_1.IN0
datab[0] => op_1.IN69
datab[1] => op_1.IN67
datab[2] => op_1.IN65
datab[3] => op_1.IN63
datab[4] => op_1.IN61
datab[5] => op_1.IN59
datab[6] => op_1.IN57
datab[7] => op_1.IN55
datab[8] => op_1.IN53
datab[9] => op_1.IN51
datab[10] => op_1.IN49
datab[11] => op_1.IN47
datab[12] => op_1.IN45
datab[13] => op_1.IN43
datab[14] => op_1.IN41
datab[15] => op_1.IN39
datab[16] => op_1.IN37
datab[17] => op_1.IN35
datab[18] => op_1.IN33
datab[19] => op_1.IN31
datab[20] => op_1.IN29
datab[21] => op_1.IN27
datab[22] => op_1.IN25
datab[23] => op_1.IN23
datab[24] => op_1.IN21
datab[25] => op_1.IN19
datab[26] => op_1.IN17
datab[27] => op_1.IN15
datab[28] => op_1.IN13
datab[29] => op_1.IN11
datab[30] => op_1.IN9
datab[31] => op_1.IN7
datab[32] => op_1.IN5
datab[33] => op_1.IN3
datab[34] => op_1.IN1
result[0] <= pipeline_dffe[35].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= pipeline_dffe[36].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= pipeline_dffe[37].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= pipeline_dffe[38].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= pipeline_dffe[39].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= pipeline_dffe[40].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= pipeline_dffe[41].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= pipeline_dffe[42].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= pipeline_dffe[43].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= pipeline_dffe[44].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= pipeline_dffe[45].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= pipeline_dffe[46].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= pipeline_dffe[47].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= pipeline_dffe[48].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= pipeline_dffe[49].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= pipeline_dffe[50].DB_MAX_OUTPUT_PORT_TYPE
result[16] <= pipeline_dffe[51].DB_MAX_OUTPUT_PORT_TYPE
result[17] <= pipeline_dffe[52].DB_MAX_OUTPUT_PORT_TYPE
result[18] <= pipeline_dffe[53].DB_MAX_OUTPUT_PORT_TYPE
result[19] <= pipeline_dffe[54].DB_MAX_OUTPUT_PORT_TYPE
result[20] <= pipeline_dffe[55].DB_MAX_OUTPUT_PORT_TYPE
result[21] <= pipeline_dffe[56].DB_MAX_OUTPUT_PORT_TYPE
result[22] <= pipeline_dffe[57].DB_MAX_OUTPUT_PORT_TYPE
result[23] <= pipeline_dffe[58].DB_MAX_OUTPUT_PORT_TYPE
result[24] <= pipeline_dffe[59].DB_MAX_OUTPUT_PORT_TYPE
result[25] <= pipeline_dffe[60].DB_MAX_OUTPUT_PORT_TYPE
result[26] <= pipeline_dffe[61].DB_MAX_OUTPUT_PORT_TYPE
result[27] <= pipeline_dffe[62].DB_MAX_OUTPUT_PORT_TYPE
result[28] <= pipeline_dffe[63].DB_MAX_OUTPUT_PORT_TYPE
result[29] <= pipeline_dffe[64].DB_MAX_OUTPUT_PORT_TYPE
result[30] <= pipeline_dffe[65].DB_MAX_OUTPUT_PORT_TYPE
result[31] <= pipeline_dffe[66].DB_MAX_OUTPUT_PORT_TYPE
result[32] <= pipeline_dffe[67].DB_MAX_OUTPUT_PORT_TYPE
result[33] <= pipeline_dffe[68].DB_MAX_OUTPUT_PORT_TYPE
result[34] <= pipeline_dffe[69].DB_MAX_OUTPUT_PORT_TYPE


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1
dataa[0] => add_sub_6ji:auto_generated.dataa[0]
dataa[1] => add_sub_6ji:auto_generated.dataa[1]
dataa[2] => add_sub_6ji:auto_generated.dataa[2]
dataa[3] => add_sub_6ji:auto_generated.dataa[3]
dataa[4] => add_sub_6ji:auto_generated.dataa[4]
dataa[5] => add_sub_6ji:auto_generated.dataa[5]
dataa[6] => add_sub_6ji:auto_generated.dataa[6]
dataa[7] => add_sub_6ji:auto_generated.dataa[7]
dataa[8] => add_sub_6ji:auto_generated.dataa[8]
dataa[9] => add_sub_6ji:auto_generated.dataa[9]
dataa[10] => add_sub_6ji:auto_generated.dataa[10]
dataa[11] => add_sub_6ji:auto_generated.dataa[11]
dataa[12] => add_sub_6ji:auto_generated.dataa[12]
dataa[13] => add_sub_6ji:auto_generated.dataa[13]
dataa[14] => add_sub_6ji:auto_generated.dataa[14]
dataa[15] => add_sub_6ji:auto_generated.dataa[15]
dataa[16] => add_sub_6ji:auto_generated.dataa[16]
dataa[17] => add_sub_6ji:auto_generated.dataa[17]
datab[0] => add_sub_6ji:auto_generated.datab[0]
datab[1] => add_sub_6ji:auto_generated.datab[1]
datab[2] => add_sub_6ji:auto_generated.datab[2]
datab[3] => add_sub_6ji:auto_generated.datab[3]
datab[4] => add_sub_6ji:auto_generated.datab[4]
datab[5] => add_sub_6ji:auto_generated.datab[5]
datab[6] => add_sub_6ji:auto_generated.datab[6]
datab[7] => add_sub_6ji:auto_generated.datab[7]
datab[8] => add_sub_6ji:auto_generated.datab[8]
datab[9] => add_sub_6ji:auto_generated.datab[9]
datab[10] => add_sub_6ji:auto_generated.datab[10]
datab[11] => add_sub_6ji:auto_generated.datab[11]
datab[12] => add_sub_6ji:auto_generated.datab[12]
datab[13] => add_sub_6ji:auto_generated.datab[13]
datab[14] => add_sub_6ji:auto_generated.datab[14]
datab[15] => add_sub_6ji:auto_generated.datab[15]
datab[16] => add_sub_6ji:auto_generated.datab[16]
datab[17] => add_sub_6ji:auto_generated.datab[17]
cin => ~NO_FANOUT~
add_sub => ~NO_FANOUT~
clock => add_sub_6ji:auto_generated.clock
aclr => add_sub_6ji:auto_generated.aclr
clken => add_sub_6ji:auto_generated.clken
result[0] <= add_sub_6ji:auto_generated.result[0]
result[1] <= add_sub_6ji:auto_generated.result[1]
result[2] <= add_sub_6ji:auto_generated.result[2]
result[3] <= add_sub_6ji:auto_generated.result[3]
result[4] <= add_sub_6ji:auto_generated.result[4]
result[5] <= add_sub_6ji:auto_generated.result[5]
result[6] <= add_sub_6ji:auto_generated.result[6]
result[7] <= add_sub_6ji:auto_generated.result[7]
result[8] <= add_sub_6ji:auto_generated.result[8]
result[9] <= add_sub_6ji:auto_generated.result[9]
result[10] <= add_sub_6ji:auto_generated.result[10]
result[11] <= add_sub_6ji:auto_generated.result[11]
result[12] <= add_sub_6ji:auto_generated.result[12]
result[13] <= add_sub_6ji:auto_generated.result[13]
result[14] <= add_sub_6ji:auto_generated.result[14]
result[15] <= add_sub_6ji:auto_generated.result[15]
result[16] <= add_sub_6ji:auto_generated.result[16]
result[17] <= add_sub_6ji:auto_generated.result[17]
cout <= <GND>
overflow <= <GND>


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
clock => pipeline_dffe[17].CLK
clock => pipeline_dffe[16].CLK
clock => pipeline_dffe[15].CLK
clock => pipeline_dffe[14].CLK
clock => pipeline_dffe[13].CLK
clock => pipeline_dffe[12].CLK
clock => pipeline_dffe[11].CLK
clock => pipeline_dffe[10].CLK
clock => pipeline_dffe[9].CLK
clock => pipeline_dffe[8].CLK
clock => pipeline_dffe[7].CLK
clock => pipeline_dffe[6].CLK
clock => pipeline_dffe[5].CLK
clock => pipeline_dffe[4].CLK
clock => pipeline_dffe[3].CLK
clock => pipeline_dffe[2].CLK
clock => pipeline_dffe[1].CLK
clock => pipeline_dffe[0].CLK
dataa[0] => op_1.IN35
dataa[1] => op_1.IN33
dataa[2] => op_1.IN31
dataa[3] => op_1.IN29
dataa[4] => op_1.IN27
dataa[5] => op_1.IN25
dataa[6] => op_1.IN23
dataa[7] => op_1.IN21
dataa[8] => op_1.IN19
dataa[9] => op_1.IN17
dataa[10] => op_1.IN15
dataa[11] => op_1.IN13
dataa[12] => op_1.IN11
dataa[13] => op_1.IN9
dataa[14] => op_1.IN7
dataa[15] => op_1.IN5
dataa[16] => op_1.IN3
dataa[17] => op_1.IN1
datab[0] => op_1.IN36
datab[1] => op_1.IN34
datab[2] => op_1.IN32
datab[3] => op_1.IN30
datab[4] => op_1.IN28
datab[5] => op_1.IN26
datab[6] => op_1.IN24
datab[7] => op_1.IN22
datab[8] => op_1.IN20
datab[9] => op_1.IN18
datab[10] => op_1.IN16
datab[11] => op_1.IN14
datab[12] => op_1.IN12
datab[13] => op_1.IN10
datab[14] => op_1.IN8
datab[15] => op_1.IN6
datab[16] => op_1.IN4
datab[17] => op_1.IN2
result[0] <= pipeline_dffe[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= pipeline_dffe[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= pipeline_dffe[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= pipeline_dffe[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= pipeline_dffe[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= pipeline_dffe[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= pipeline_dffe[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= pipeline_dffe[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= pipeline_dffe[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= pipeline_dffe[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= pipeline_dffe[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= pipeline_dffe[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= pipeline_dffe[12].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= pipeline_dffe[13].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= pipeline_dffe[14].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= pipeline_dffe[15].DB_MAX_OUTPUT_PORT_TYPE
result[16] <= pipeline_dffe[16].DB_MAX_OUTPUT_PORT_TYPE
result[17] <= pipeline_dffe[17].DB_MAX_OUTPUT_PORT_TYPE


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor2
dataa[0] => add_sub_5ji:auto_generated.dataa[0]
dataa[1] => add_sub_5ji:auto_generated.dataa[1]
dataa[2] => add_sub_5ji:auto_generated.dataa[2]
dataa[3] => add_sub_5ji:auto_generated.dataa[3]
dataa[4] => add_sub_5ji:auto_generated.dataa[4]
dataa[5] => add_sub_5ji:auto_generated.dataa[5]
dataa[6] => add_sub_5ji:auto_generated.dataa[6]
dataa[7] => add_sub_5ji:auto_generated.dataa[7]
dataa[8] => add_sub_5ji:auto_generated.dataa[8]
dataa[9] => add_sub_5ji:auto_generated.dataa[9]
dataa[10] => add_sub_5ji:auto_generated.dataa[10]
dataa[11] => add_sub_5ji:auto_generated.dataa[11]
dataa[12] => add_sub_5ji:auto_generated.dataa[12]
dataa[13] => add_sub_5ji:auto_generated.dataa[13]
dataa[14] => add_sub_5ji:auto_generated.dataa[14]
dataa[15] => add_sub_5ji:auto_generated.dataa[15]
dataa[16] => add_sub_5ji:auto_generated.dataa[16]
dataa[17] => add_sub_5ji:auto_generated.dataa[17]
dataa[18] => add_sub_5ji:auto_generated.dataa[18]
dataa[19] => add_sub_5ji:auto_generated.dataa[19]
dataa[20] => add_sub_5ji:auto_generated.dataa[20]
dataa[21] => add_sub_5ji:auto_generated.dataa[21]
dataa[22] => add_sub_5ji:auto_generated.dataa[22]
dataa[23] => add_sub_5ji:auto_generated.dataa[23]
dataa[24] => add_sub_5ji:auto_generated.dataa[24]
dataa[25] => add_sub_5ji:auto_generated.dataa[25]
dataa[26] => add_sub_5ji:auto_generated.dataa[26]
dataa[27] => add_sub_5ji:auto_generated.dataa[27]
dataa[28] => add_sub_5ji:auto_generated.dataa[28]
dataa[29] => add_sub_5ji:auto_generated.dataa[29]
dataa[30] => add_sub_5ji:auto_generated.dataa[30]
dataa[31] => add_sub_5ji:auto_generated.dataa[31]
dataa[32] => add_sub_5ji:auto_generated.dataa[32]
dataa[33] => add_sub_5ji:auto_generated.dataa[33]
dataa[34] => add_sub_5ji:auto_generated.dataa[34]
datab[0] => add_sub_5ji:auto_generated.datab[0]
datab[1] => add_sub_5ji:auto_generated.datab[1]
datab[2] => add_sub_5ji:auto_generated.datab[2]
datab[3] => add_sub_5ji:auto_generated.datab[3]
datab[4] => add_sub_5ji:auto_generated.datab[4]
datab[5] => add_sub_5ji:auto_generated.datab[5]
datab[6] => add_sub_5ji:auto_generated.datab[6]
datab[7] => add_sub_5ji:auto_generated.datab[7]
datab[8] => add_sub_5ji:auto_generated.datab[8]
datab[9] => add_sub_5ji:auto_generated.datab[9]
datab[10] => add_sub_5ji:auto_generated.datab[10]
datab[11] => add_sub_5ji:auto_generated.datab[11]
datab[12] => add_sub_5ji:auto_generated.datab[12]
datab[13] => add_sub_5ji:auto_generated.datab[13]
datab[14] => add_sub_5ji:auto_generated.datab[14]
datab[15] => add_sub_5ji:auto_generated.datab[15]
datab[16] => add_sub_5ji:auto_generated.datab[16]
datab[17] => add_sub_5ji:auto_generated.datab[17]
datab[18] => add_sub_5ji:auto_generated.datab[18]
datab[19] => add_sub_5ji:auto_generated.datab[19]
datab[20] => add_sub_5ji:auto_generated.datab[20]
datab[21] => add_sub_5ji:auto_generated.datab[21]
datab[22] => add_sub_5ji:auto_generated.datab[22]
datab[23] => add_sub_5ji:auto_generated.datab[23]
datab[24] => add_sub_5ji:auto_generated.datab[24]
datab[25] => add_sub_5ji:auto_generated.datab[25]
datab[26] => add_sub_5ji:auto_generated.datab[26]
datab[27] => add_sub_5ji:auto_generated.datab[27]
datab[28] => add_sub_5ji:auto_generated.datab[28]
datab[29] => add_sub_5ji:auto_generated.datab[29]
datab[30] => add_sub_5ji:auto_generated.datab[30]
datab[31] => add_sub_5ji:auto_generated.datab[31]
datab[32] => add_sub_5ji:auto_generated.datab[32]
datab[33] => add_sub_5ji:auto_generated.datab[33]
datab[34] => add_sub_5ji:auto_generated.datab[34]
cin => ~NO_FANOUT~
add_sub => ~NO_FANOUT~
clock => add_sub_5ji:auto_generated.clock
aclr => add_sub_5ji:auto_generated.aclr
clken => add_sub_5ji:auto_generated.clken
result[0] <= add_sub_5ji:auto_generated.result[0]
result[1] <= add_sub_5ji:auto_generated.result[1]
result[2] <= add_sub_5ji:auto_generated.result[2]
result[3] <= add_sub_5ji:auto_generated.result[3]
result[4] <= add_sub_5ji:auto_generated.result[4]
result[5] <= add_sub_5ji:auto_generated.result[5]
result[6] <= add_sub_5ji:auto_generated.result[6]
result[7] <= add_sub_5ji:auto_generated.result[7]
result[8] <= add_sub_5ji:auto_generated.result[8]
result[9] <= add_sub_5ji:auto_generated.result[9]
result[10] <= add_sub_5ji:auto_generated.result[10]
result[11] <= add_sub_5ji:auto_generated.result[11]
result[12] <= add_sub_5ji:auto_generated.result[12]
result[13] <= add_sub_5ji:auto_generated.result[13]
result[14] <= add_sub_5ji:auto_generated.result[14]
result[15] <= add_sub_5ji:auto_generated.result[15]
result[16] <= add_sub_5ji:auto_generated.result[16]
result[17] <= add_sub_5ji:auto_generated.result[17]
result[18] <= add_sub_5ji:auto_generated.result[18]
result[19] <= add_sub_5ji:auto_generated.result[19]
result[20] <= add_sub_5ji:auto_generated.result[20]
result[21] <= add_sub_5ji:auto_generated.result[21]
result[22] <= add_sub_5ji:auto_generated.result[22]
result[23] <= add_sub_5ji:auto_generated.result[23]
result[24] <= add_sub_5ji:auto_generated.result[24]
result[25] <= add_sub_5ji:auto_generated.result[25]
result[26] <= add_sub_5ji:auto_generated.result[26]
result[27] <= add_sub_5ji:auto_generated.result[27]
result[28] <= add_sub_5ji:auto_generated.result[28]
result[29] <= add_sub_5ji:auto_generated.result[29]
result[30] <= add_sub_5ji:auto_generated.result[30]
result[31] <= add_sub_5ji:auto_generated.result[31]
result[32] <= add_sub_5ji:auto_generated.result[32]
result[33] <= add_sub_5ji:auto_generated.result[33]
result[34] <= add_sub_5ji:auto_generated.result[34]
cout <= <GND>
overflow <= <GND>


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor2|add_sub_5ji:auto_generated
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
clock => pipeline_dffe[34].CLK
clock => pipeline_dffe[33].CLK
clock => pipeline_dffe[32].CLK
clock => pipeline_dffe[31].CLK
clock => pipeline_dffe[30].CLK
clock => pipeline_dffe[29].CLK
clock => pipeline_dffe[28].CLK
clock => pipeline_dffe[27].CLK
clock => pipeline_dffe[26].CLK
clock => pipeline_dffe[25].CLK
clock => pipeline_dffe[24].CLK
clock => pipeline_dffe[23].CLK
clock => pipeline_dffe[22].CLK
clock => pipeline_dffe[21].CLK
clock => pipeline_dffe[20].CLK
clock => pipeline_dffe[19].CLK
clock => pipeline_dffe[18].CLK
clock => pipeline_dffe[17].CLK
clock => pipeline_dffe[16].CLK
clock => pipeline_dffe[15].CLK
clock => pipeline_dffe[14].CLK
clock => pipeline_dffe[13].CLK
clock => pipeline_dffe[12].CLK
clock => pipeline_dffe[11].CLK
clock => pipeline_dffe[10].CLK
clock => pipeline_dffe[9].CLK
clock => pipeline_dffe[8].CLK
clock => pipeline_dffe[7].CLK
clock => pipeline_dffe[6].CLK
clock => pipeline_dffe[5].CLK
clock => pipeline_dffe[4].CLK
clock => pipeline_dffe[3].CLK
clock => pipeline_dffe[2].CLK
clock => pipeline_dffe[1].CLK
clock => pipeline_dffe[0].CLK
dataa[0] => op_1.IN69
dataa[1] => op_1.IN67
dataa[2] => op_1.IN65
dataa[3] => op_1.IN63
dataa[4] => op_1.IN61
dataa[5] => op_1.IN59
dataa[6] => op_1.IN57
dataa[7] => op_1.IN55
dataa[8] => op_1.IN53
dataa[9] => op_1.IN51
dataa[10] => op_1.IN49
dataa[11] => op_1.IN47
dataa[12] => op_1.IN45
dataa[13] => op_1.IN43
dataa[14] => op_1.IN41
dataa[15] => op_1.IN39
dataa[16] => op_1.IN37
dataa[17] => op_1.IN35
dataa[18] => op_1.IN33
dataa[19] => op_1.IN31
dataa[20] => op_1.IN29
dataa[21] => op_1.IN27
dataa[22] => op_1.IN25
dataa[23] => op_1.IN23
dataa[24] => op_1.IN21
dataa[25] => op_1.IN19
dataa[26] => op_1.IN17
dataa[27] => op_1.IN15
dataa[28] => op_1.IN13
dataa[29] => op_1.IN11
dataa[30] => op_1.IN9
dataa[31] => op_1.IN7
dataa[32] => op_1.IN5
dataa[33] => op_1.IN3
dataa[34] => op_1.IN1
datab[0] => op_1.IN70
datab[1] => op_1.IN68
datab[2] => op_1.IN66
datab[3] => op_1.IN64
datab[4] => op_1.IN62
datab[5] => op_1.IN60
datab[6] => op_1.IN58
datab[7] => op_1.IN56
datab[8] => op_1.IN54
datab[9] => op_1.IN52
datab[10] => op_1.IN50
datab[11] => op_1.IN48
datab[12] => op_1.IN46
datab[13] => op_1.IN44
datab[14] => op_1.IN42
datab[15] => op_1.IN40
datab[16] => op_1.IN38
datab[17] => op_1.IN36
datab[18] => op_1.IN34
datab[19] => op_1.IN32
datab[20] => op_1.IN30
datab[21] => op_1.IN28
datab[22] => op_1.IN26
datab[23] => op_1.IN24
datab[24] => op_1.IN22
datab[25] => op_1.IN20
datab[26] => op_1.IN18
datab[27] => op_1.IN16
datab[28] => op_1.IN14
datab[29] => op_1.IN12
datab[30] => op_1.IN10
datab[31] => op_1.IN8
datab[32] => op_1.IN6
datab[33] => op_1.IN4
datab[34] => op_1.IN2
result[0] <= pipeline_dffe[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= pipeline_dffe[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= pipeline_dffe[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= pipeline_dffe[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= pipeline_dffe[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= pipeline_dffe[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= pipeline_dffe[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= pipeline_dffe[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= pipeline_dffe[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= pipeline_dffe[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= pipeline_dffe[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= pipeline_dffe[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= pipeline_dffe[12].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= pipeline_dffe[13].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= pipeline_dffe[14].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= pipeline_dffe[15].DB_MAX_OUTPUT_PORT_TYPE
result[16] <= pipeline_dffe[16].DB_MAX_OUTPUT_PORT_TYPE
result[17] <= pipeline_dffe[17].DB_MAX_OUTPUT_PORT_TYPE
result[18] <= pipeline_dffe[18].DB_MAX_OUTPUT_PORT_TYPE
result[19] <= pipeline_dffe[19].DB_MAX_OUTPUT_PORT_TYPE
result[20] <= pipeline_dffe[20].DB_MAX_OUTPUT_PORT_TYPE
result[21] <= pipeline_dffe[21].DB_MAX_OUTPUT_PORT_TYPE
result[22] <= pipeline_dffe[22].DB_MAX_OUTPUT_PORT_TYPE
result[23] <= pipeline_dffe[23].DB_MAX_OUTPUT_PORT_TYPE
result[24] <= pipeline_dffe[24].DB_MAX_OUTPUT_PORT_TYPE
result[25] <= pipeline_dffe[25].DB_MAX_OUTPUT_PORT_TYPE
result[26] <= pipeline_dffe[26].DB_MAX_OUTPUT_PORT_TYPE
result[27] <= pipeline_dffe[27].DB_MAX_OUTPUT_PORT_TYPE
result[28] <= pipeline_dffe[28].DB_MAX_OUTPUT_PORT_TYPE
result[29] <= pipeline_dffe[29].DB_MAX_OUTPUT_PORT_TYPE
result[30] <= pipeline_dffe[30].DB_MAX_OUTPUT_PORT_TYPE
result[31] <= pipeline_dffe[31].DB_MAX_OUTPUT_PORT_TYPE
result[32] <= pipeline_dffe[32].DB_MAX_OUTPUT_PORT_TYPE
result[33] <= pipeline_dffe[33].DB_MAX_OUTPUT_PORT_TYPE
result[34] <= pipeline_dffe[34].DB_MAX_OUTPUT_PORT_TYPE


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor3
dataa[0] => add_sub_i5j:auto_generated.dataa[0]
dataa[1] => add_sub_i5j:auto_generated.dataa[1]
dataa[2] => add_sub_i5j:auto_generated.dataa[2]
dataa[3] => add_sub_i5j:auto_generated.dataa[3]
dataa[4] => add_sub_i5j:auto_generated.dataa[4]
dataa[5] => add_sub_i5j:auto_generated.dataa[5]
dataa[6] => add_sub_i5j:auto_generated.dataa[6]
dataa[7] => add_sub_i5j:auto_generated.dataa[7]
dataa[8] => add_sub_i5j:auto_generated.dataa[8]
dataa[9] => add_sub_i5j:auto_generated.dataa[9]
dataa[10] => add_sub_i5j:auto_generated.dataa[10]
dataa[11] => add_sub_i5j:auto_generated.dataa[11]
dataa[12] => add_sub_i5j:auto_generated.dataa[12]
dataa[13] => add_sub_i5j:auto_generated.dataa[13]
dataa[14] => add_sub_i5j:auto_generated.dataa[14]
dataa[15] => add_sub_i5j:auto_generated.dataa[15]
dataa[16] => add_sub_i5j:auto_generated.dataa[16]
dataa[17] => add_sub_i5j:auto_generated.dataa[17]
dataa[18] => add_sub_i5j:auto_generated.dataa[18]
dataa[19] => add_sub_i5j:auto_generated.dataa[19]
dataa[20] => add_sub_i5j:auto_generated.dataa[20]
dataa[21] => add_sub_i5j:auto_generated.dataa[21]
dataa[22] => add_sub_i5j:auto_generated.dataa[22]
dataa[23] => add_sub_i5j:auto_generated.dataa[23]
dataa[24] => add_sub_i5j:auto_generated.dataa[24]
dataa[25] => add_sub_i5j:auto_generated.dataa[25]
dataa[26] => add_sub_i5j:auto_generated.dataa[26]
dataa[27] => add_sub_i5j:auto_generated.dataa[27]
dataa[28] => add_sub_i5j:auto_generated.dataa[28]
dataa[29] => add_sub_i5j:auto_generated.dataa[29]
dataa[30] => add_sub_i5j:auto_generated.dataa[30]
dataa[31] => add_sub_i5j:auto_generated.dataa[31]
dataa[32] => add_sub_i5j:auto_generated.dataa[32]
dataa[33] => add_sub_i5j:auto_generated.dataa[33]
dataa[34] => add_sub_i5j:auto_generated.dataa[34]
dataa[35] => add_sub_i5j:auto_generated.dataa[35]
datab[0] => add_sub_i5j:auto_generated.datab[0]
datab[1] => add_sub_i5j:auto_generated.datab[1]
datab[2] => add_sub_i5j:auto_generated.datab[2]
datab[3] => add_sub_i5j:auto_generated.datab[3]
datab[4] => add_sub_i5j:auto_generated.datab[4]
datab[5] => add_sub_i5j:auto_generated.datab[5]
datab[6] => add_sub_i5j:auto_generated.datab[6]
datab[7] => add_sub_i5j:auto_generated.datab[7]
datab[8] => add_sub_i5j:auto_generated.datab[8]
datab[9] => add_sub_i5j:auto_generated.datab[9]
datab[10] => add_sub_i5j:auto_generated.datab[10]
datab[11] => add_sub_i5j:auto_generated.datab[11]
datab[12] => add_sub_i5j:auto_generated.datab[12]
datab[13] => add_sub_i5j:auto_generated.datab[13]
datab[14] => add_sub_i5j:auto_generated.datab[14]
datab[15] => add_sub_i5j:auto_generated.datab[15]
datab[16] => add_sub_i5j:auto_generated.datab[16]
datab[17] => add_sub_i5j:auto_generated.datab[17]
datab[18] => add_sub_i5j:auto_generated.datab[18]
datab[19] => add_sub_i5j:auto_generated.datab[19]
datab[20] => add_sub_i5j:auto_generated.datab[20]
datab[21] => add_sub_i5j:auto_generated.datab[21]
datab[22] => add_sub_i5j:auto_generated.datab[22]
datab[23] => add_sub_i5j:auto_generated.datab[23]
datab[24] => add_sub_i5j:auto_generated.datab[24]
datab[25] => add_sub_i5j:auto_generated.datab[25]
datab[26] => add_sub_i5j:auto_generated.datab[26]
datab[27] => add_sub_i5j:auto_generated.datab[27]
datab[28] => add_sub_i5j:auto_generated.datab[28]
datab[29] => add_sub_i5j:auto_generated.datab[29]
datab[30] => add_sub_i5j:auto_generated.datab[30]
datab[31] => add_sub_i5j:auto_generated.datab[31]
datab[32] => add_sub_i5j:auto_generated.datab[32]
datab[33] => add_sub_i5j:auto_generated.datab[33]
datab[34] => add_sub_i5j:auto_generated.datab[34]
datab[35] => add_sub_i5j:auto_generated.datab[35]
cin => ~NO_FANOUT~
add_sub => ~NO_FANOUT~
clock => add_sub_i5j:auto_generated.clock
aclr => add_sub_i5j:auto_generated.aclr
clken => add_sub_i5j:auto_generated.clken
result[0] <= add_sub_i5j:auto_generated.result[0]
result[1] <= add_sub_i5j:auto_generated.result[1]
result[2] <= add_sub_i5j:auto_generated.result[2]
result[3] <= add_sub_i5j:auto_generated.result[3]
result[4] <= add_sub_i5j:auto_generated.result[4]
result[5] <= add_sub_i5j:auto_generated.result[5]
result[6] <= add_sub_i5j:auto_generated.result[6]
result[7] <= add_sub_i5j:auto_generated.result[7]
result[8] <= add_sub_i5j:auto_generated.result[8]
result[9] <= add_sub_i5j:auto_generated.result[9]
result[10] <= add_sub_i5j:auto_generated.result[10]
result[11] <= add_sub_i5j:auto_generated.result[11]
result[12] <= add_sub_i5j:auto_generated.result[12]
result[13] <= add_sub_i5j:auto_generated.result[13]
result[14] <= add_sub_i5j:auto_generated.result[14]
result[15] <= add_sub_i5j:auto_generated.result[15]
result[16] <= add_sub_i5j:auto_generated.result[16]
result[17] <= add_sub_i5j:auto_generated.result[17]
result[18] <= add_sub_i5j:auto_generated.result[18]
result[19] <= add_sub_i5j:auto_generated.result[19]
result[20] <= add_sub_i5j:auto_generated.result[20]
result[21] <= add_sub_i5j:auto_generated.result[21]
result[22] <= add_sub_i5j:auto_generated.result[22]
result[23] <= add_sub_i5j:auto_generated.result[23]
result[24] <= add_sub_i5j:auto_generated.result[24]
result[25] <= add_sub_i5j:auto_generated.result[25]
result[26] <= add_sub_i5j:auto_generated.result[26]
result[27] <= add_sub_i5j:auto_generated.result[27]
result[28] <= add_sub_i5j:auto_generated.result[28]
result[29] <= add_sub_i5j:auto_generated.result[29]
result[30] <= add_sub_i5j:auto_generated.result[30]
result[31] <= add_sub_i5j:auto_generated.result[31]
result[32] <= add_sub_i5j:auto_generated.result[32]
result[33] <= add_sub_i5j:auto_generated.result[33]
result[34] <= add_sub_i5j:auto_generated.result[34]
result[35] <= add_sub_i5j:auto_generated.result[35]
cout <= <GND>
overflow <= <GND>


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor3|add_sub_i5j:auto_generated
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
clock => pipeline_dffe[35].CLK
clock => pipeline_dffe[34].CLK
clock => pipeline_dffe[33].CLK
clock => pipeline_dffe[32].CLK
clock => pipeline_dffe[31].CLK
clock => pipeline_dffe[30].CLK
clock => pipeline_dffe[29].CLK
clock => pipeline_dffe[28].CLK
clock => pipeline_dffe[27].CLK
clock => pipeline_dffe[26].CLK
clock => pipeline_dffe[25].CLK
clock => pipeline_dffe[24].CLK
clock => pipeline_dffe[23].CLK
clock => pipeline_dffe[22].CLK
clock => pipeline_dffe[21].CLK
clock => pipeline_dffe[20].CLK
clock => pipeline_dffe[19].CLK
clock => pipeline_dffe[18].CLK
clock => pipeline_dffe[17].CLK
clock => pipeline_dffe[16].CLK
clock => pipeline_dffe[15].CLK
clock => pipeline_dffe[14].CLK
clock => pipeline_dffe[13].CLK
clock => pipeline_dffe[12].CLK
clock => pipeline_dffe[11].CLK
clock => pipeline_dffe[10].CLK
clock => pipeline_dffe[9].CLK
clock => pipeline_dffe[8].CLK
clock => pipeline_dffe[7].CLK
clock => pipeline_dffe[6].CLK
clock => pipeline_dffe[5].CLK
clock => pipeline_dffe[4].CLK
clock => pipeline_dffe[3].CLK
clock => pipeline_dffe[2].CLK
clock => pipeline_dffe[1].CLK
clock => pipeline_dffe[0].CLK
dataa[0] => ~NO_FANOUT~
dataa[1] => ~NO_FANOUT~
dataa[2] => ~NO_FANOUT~
dataa[3] => ~NO_FANOUT~
dataa[4] => ~NO_FANOUT~
dataa[5] => ~NO_FANOUT~
dataa[6] => ~NO_FANOUT~
dataa[7] => ~NO_FANOUT~
dataa[8] => ~NO_FANOUT~
dataa[9] => ~NO_FANOUT~
dataa[10] => ~NO_FANOUT~
dataa[11] => ~NO_FANOUT~
dataa[12] => ~NO_FANOUT~
dataa[13] => ~NO_FANOUT~
dataa[14] => ~NO_FANOUT~
dataa[15] => ~NO_FANOUT~
dataa[16] => ~NO_FANOUT~
dataa[17] => ~NO_FANOUT~
dataa[18] => ~NO_FANOUT~
dataa[19] => ~NO_FANOUT~
dataa[20] => ~NO_FANOUT~
dataa[21] => ~NO_FANOUT~
dataa[22] => ~NO_FANOUT~
dataa[23] => ~NO_FANOUT~
dataa[24] => ~NO_FANOUT~
dataa[25] => ~NO_FANOUT~
dataa[26] => ~NO_FANOUT~
dataa[27] => ~NO_FANOUT~
dataa[28] => ~NO_FANOUT~
dataa[29] => ~NO_FANOUT~
dataa[30] => ~NO_FANOUT~
dataa[31] => ~NO_FANOUT~
dataa[32] => ~NO_FANOUT~
dataa[33] => ~NO_FANOUT~
dataa[34] => ~NO_FANOUT~
dataa[35] => ~NO_FANOUT~
datab[0] => op_1.IN71
datab[1] => op_1.IN69
datab[2] => op_1.IN67
datab[3] => op_1.IN65
datab[4] => op_1.IN63
datab[5] => op_1.IN61
datab[6] => op_1.IN59
datab[7] => op_1.IN57
datab[8] => op_1.IN55
datab[9] => op_1.IN53
datab[10] => op_1.IN51
datab[11] => op_1.IN49
datab[12] => op_1.IN47
datab[13] => op_1.IN45
datab[14] => op_1.IN43
datab[15] => op_1.IN41
datab[16] => op_1.IN39
datab[17] => op_1.IN37
datab[18] => op_1.IN35
datab[19] => op_1.IN33
datab[20] => op_1.IN31
datab[21] => op_1.IN29
datab[22] => op_1.IN27
datab[23] => op_1.IN25
datab[24] => op_1.IN23
datab[25] => op_1.IN21
datab[26] => op_1.IN19
datab[27] => op_1.IN17
datab[28] => op_1.IN15
datab[29] => op_1.IN13
datab[30] => op_1.IN11
datab[31] => op_1.IN9
datab[32] => op_1.IN7
datab[33] => op_1.IN5
datab[34] => op_1.IN3
datab[35] => op_1.IN1
result[0] <= pipeline_dffe[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= pipeline_dffe[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= pipeline_dffe[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= pipeline_dffe[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= pipeline_dffe[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= pipeline_dffe[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= pipeline_dffe[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= pipeline_dffe[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= pipeline_dffe[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= pipeline_dffe[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= pipeline_dffe[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= pipeline_dffe[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= pipeline_dffe[12].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= pipeline_dffe[13].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= pipeline_dffe[14].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= pipeline_dffe[15].DB_MAX_OUTPUT_PORT_TYPE
result[16] <= pipeline_dffe[16].DB_MAX_OUTPUT_PORT_TYPE
result[17] <= pipeline_dffe[17].DB_MAX_OUTPUT_PORT_TYPE
result[18] <= pipeline_dffe[18].DB_MAX_OUTPUT_PORT_TYPE
result[19] <= pipeline_dffe[19].DB_MAX_OUTPUT_PORT_TYPE
result[20] <= pipeline_dffe[20].DB_MAX_OUTPUT_PORT_TYPE
result[21] <= pipeline_dffe[21].DB_MAX_OUTPUT_PORT_TYPE
result[22] <= pipeline_dffe[22].DB_MAX_OUTPUT_PORT_TYPE
result[23] <= pipeline_dffe[23].DB_MAX_OUTPUT_PORT_TYPE
result[24] <= pipeline_dffe[24].DB_MAX_OUTPUT_PORT_TYPE
result[25] <= pipeline_dffe[25].DB_MAX_OUTPUT_PORT_TYPE
result[26] <= pipeline_dffe[26].DB_MAX_OUTPUT_PORT_TYPE
result[27] <= pipeline_dffe[27].DB_MAX_OUTPUT_PORT_TYPE
result[28] <= pipeline_dffe[28].DB_MAX_OUTPUT_PORT_TYPE
result[29] <= pipeline_dffe[29].DB_MAX_OUTPUT_PORT_TYPE
result[30] <= pipeline_dffe[30].DB_MAX_OUTPUT_PORT_TYPE
result[31] <= pipeline_dffe[31].DB_MAX_OUTPUT_PORT_TYPE
result[32] <= pipeline_dffe[32].DB_MAX_OUTPUT_PORT_TYPE
result[33] <= pipeline_dffe[33].DB_MAX_OUTPUT_PORT_TYPE
result[34] <= pipeline_dffe[34].DB_MAX_OUTPUT_PORT_TYPE
result[35] <= pipeline_dffe[35].DB_MAX_OUTPUT_PORT_TYPE


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_compare:comparator1
dataa[0] => cmpr_1cg:auto_generated.dataa[0]
dataa[1] => cmpr_1cg:auto_generated.dataa[1]
dataa[2] => cmpr_1cg:auto_generated.dataa[2]
dataa[3] => cmpr_1cg:auto_generated.dataa[3]
dataa[4] => cmpr_1cg:auto_generated.dataa[4]
dataa[5] => cmpr_1cg:auto_generated.dataa[5]
dataa[6] => cmpr_1cg:auto_generated.dataa[6]
dataa[7] => cmpr_1cg:auto_generated.dataa[7]
dataa[8] => cmpr_1cg:auto_generated.dataa[8]
dataa[9] => cmpr_1cg:auto_generated.dataa[9]
dataa[10] => cmpr_1cg:auto_generated.dataa[10]
dataa[11] => cmpr_1cg:auto_generated.dataa[11]
dataa[12] => cmpr_1cg:auto_generated.dataa[12]
dataa[13] => cmpr_1cg:auto_generated.dataa[13]
dataa[14] => cmpr_1cg:auto_generated.dataa[14]
dataa[15] => cmpr_1cg:auto_generated.dataa[15]
dataa[16] => cmpr_1cg:auto_generated.dataa[16]
datab[0] => cmpr_1cg:auto_generated.datab[0]
datab[1] => cmpr_1cg:auto_generated.datab[1]
datab[2] => cmpr_1cg:auto_generated.datab[2]
datab[3] => cmpr_1cg:auto_generated.datab[3]
datab[4] => cmpr_1cg:auto_generated.datab[4]
datab[5] => cmpr_1cg:auto_generated.datab[5]
datab[6] => cmpr_1cg:auto_generated.datab[6]
datab[7] => cmpr_1cg:auto_generated.datab[7]
datab[8] => cmpr_1cg:auto_generated.datab[8]
datab[9] => cmpr_1cg:auto_generated.datab[9]
datab[10] => cmpr_1cg:auto_generated.datab[10]
datab[11] => cmpr_1cg:auto_generated.datab[11]
datab[12] => cmpr_1cg:auto_generated.datab[12]
datab[13] => cmpr_1cg:auto_generated.datab[13]
datab[14] => cmpr_1cg:auto_generated.datab[14]
datab[15] => cmpr_1cg:auto_generated.datab[15]
datab[16] => cmpr_1cg:auto_generated.datab[16]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
alb <= cmpr_1cg:auto_generated.alb
aeb <= <GND>
agb <= <GND>
aleb <= <GND>
aneb <= <GND>
ageb <= <GND>


|block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_compare:comparator1|cmpr_1cg:auto_generated
alb <= alb_int.DB_MAX_OUTPUT_PORT_TYPE
dataa[0] => op_1.IN33
dataa[1] => op_1.IN31
dataa[2] => op_1.IN29
dataa[3] => op_1.IN27
dataa[4] => op_1.IN25
dataa[5] => op_1.IN23
dataa[6] => op_1.IN21
dataa[7] => op_1.IN19
dataa[8] => op_1.IN17
dataa[9] => op_1.IN15
dataa[10] => op_1.IN13
dataa[11] => op_1.IN11
dataa[12] => op_1.IN9
dataa[13] => op_1.IN7
dataa[14] => op_1.IN5
dataa[15] => op_1.IN3
dataa[16] => dataa_int[16].IN0
datab[0] => op_1.IN34
datab[1] => op_1.IN32
datab[2] => op_1.IN30
datab[3] => op_1.IN28
datab[4] => op_1.IN26
datab[5] => op_1.IN24
datab[6] => op_1.IN22
datab[7] => op_1.IN20
datab[8] => op_1.IN18
datab[9] => op_1.IN16
datab[10] => op_1.IN14
datab[11] => op_1.IN12
datab[12] => op_1.IN10
datab[13] => op_1.IN8
datab[14] => op_1.IN6
datab[15] => op_1.IN4
datab[16] => datab_int[16].IN0


|block|s2p:inst6
clk => count[6].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => cnt.CLK
clk => data_temp[1][15].CLK
clk => data_temp[1][14].CLK
clk => data_temp[1][13].CLK
clk => data_temp[1][12].CLK
clk => data_temp[1][11].CLK
clk => data_temp[1][10].CLK
clk => data_temp[1][9].CLK
clk => data_temp[1][8].CLK
clk => data_temp[1][7].CLK
clk => data_temp[1][6].CLK
clk => data_temp[1][5].CLK
clk => data_temp[1][4].CLK
clk => data_temp[1][3].CLK
clk => data_temp[1][2].CLK
clk => data_temp[1][1].CLK
clk => data_temp[1][0].CLK
clk => data_temp[0][15].CLK
clk => data_temp[0][14].CLK
clk => data_temp[0][13].CLK
clk => data_temp[0][12].CLK
clk => data_temp[0][11].CLK
clk => data_temp[0][10].CLK
clk => data_temp[0][9].CLK
clk => data_temp[0][8].CLK
clk => data_temp[0][7].CLK
clk => data_temp[0][6].CLK
clk => data_temp[0][5].CLK
clk => data_temp[0][4].CLK
clk => data_temp[0][3].CLK
clk => data_temp[0][2].CLK
clk => data_temp[0][1].CLK
clk => data_temp[0][0].CLK
reset => source_valid~0.IN0
reset => count[6].ACLR
reset => count[5].ACLR
reset => count[4].ACLR
reset => count[3].ACLR
reset => count[2].ACLR
reset => count[1].ACLR
reset => count[0].ACLR
reset => cnt.ACLR
reset => data_temp[1][15].ACLR
reset => data_temp[1][14].ACLR
reset => data_temp[1][13].ACLR
reset => data_temp[1][12].ACLR
reset => data_temp[1][11].ACLR
reset => data_temp[1][10].ACLR
reset => data_temp[1][9].ACLR
reset => data_temp[1][8].ACLR
reset => data_temp[1][7].ACLR
reset => data_temp[1][6].ACLR
reset => data_temp[1][5].ACLR
reset => data_temp[1][4].ACLR
reset => data_temp[1][3].ACLR
reset => data_temp[1][2].ACLR
reset => data_temp[1][1].ACLR
reset => data_temp[1][0].ACLR
reset => data_temp[0][15].ACLR
reset => data_temp[0][14].ACLR
reset => data_temp[0][13].ACLR
reset => data_temp[0][12].ACLR
reset => data_temp[0][11].ACLR
reset => data_temp[0][10].ACLR
reset => data_temp[0][9].ACLR
reset => data_temp[0][8].ACLR
reset => data_temp[0][7].ACLR
reset => data_temp[0][6].ACLR
reset => data_temp[0][5].ACLR
reset => data_temp[0][4].ACLR
reset => data_temp[0][3].ACLR
reset => data_temp[0][2].ACLR
reset => data_temp[0][1].ACLR
reset => data_temp[0][0].ACLR
sink_valid => data_temp~63.OUTPUTSELECT
sink_valid => data_temp~62.OUTPUTSELECT
sink_valid => data_temp~61.OUTPUTSELECT
sink_valid => data_temp~60.OUTPUTSELECT
sink_valid => data_temp~59.OUTPUTSELECT
sink_valid => data_temp~58.OUTPUTSELECT
sink_valid => data_temp~57.OUTPUTSELECT
sink_valid => data_temp~56.OUTPUTSELECT
sink_valid => data_temp~55.OUTPUTSELECT
sink_valid => data_temp~54.OUTPUTSELECT
sink_valid => data_temp~53.OUTPUTSELECT
sink_valid => data_temp~52.OUTPUTSELECT
sink_valid => data_temp~51.OUTPUTSELECT
sink_valid => data_temp~50.OUTPUTSELECT
sink_valid => data_temp~49.OUTPUTSELECT
sink_valid => data_temp~48.OUTPUTSELECT
sink_valid => data_temp~47.OUTPUTSELECT
sink_valid => data_temp~46.OUTPUTSELECT
sink_valid => data_temp~45.OUTPUTSELECT
sink_valid => data_temp~44.OUTPUTSELECT
sink_valid => data_temp~43.OUTPUTSELECT
sink_valid => data_temp~42.OUTPUTSELECT
sink_valid => data_temp~41.OUTPUTSELECT
sink_valid => data_temp~40.OUTPUTSELECT
sink_valid => data_temp~39.OUTPUTSELECT
sink_valid => data_temp~38.OUTPUTSELECT
sink_valid => data_temp~37.OUTPUTSELECT
sink_valid => data_temp~36.OUTPUTSELECT
sink_valid => data_temp~35.OUTPUTSELECT
sink_valid => data_temp~34.OUTPUTSELECT
sink_valid => data_temp~33.OUTPUTSELECT
sink_valid => data_temp~32.OUTPUTSELECT
sink_valid => count~13.OUTPUTSELECT
sink_valid => count~12.OUTPUTSELECT
sink_valid => count~11.OUTPUTSELECT
sink_valid => count~10.OUTPUTSELECT
sink_valid => count~9.OUTPUTSELECT
sink_valid => count~8.OUTPUTSELECT
sink_valid => count~7.OUTPUTSELECT
sink_valid => cnt~0.OUTPUTSELECT
data_in[0] => data_temp~31.DATAB
data_in[0] => data_temp~15.DATAB
data_in[1] => data_temp~30.DATAB
data_in[1] => data_temp~14.DATAB
data_in[2] => data_temp~29.DATAB
data_in[2] => data_temp~13.DATAB
data_in[3] => data_temp~28.DATAB
data_in[3] => data_temp~12.DATAB
data_in[4] => data_temp~27.DATAB
data_in[4] => data_temp~11.DATAB
data_in[5] => data_temp~26.DATAB
data_in[5] => data_temp~10.DATAB
data_in[6] => data_temp~25.DATAB
data_in[6] => data_temp~9.DATAB
data_in[7] => data_temp~24.DATAB
data_in[7] => data_temp~8.DATAB
data_in[8] => data_temp~23.DATAB
data_in[8] => data_temp~7.DATAB
data_in[9] => data_temp~22.DATAB
data_in[9] => data_temp~6.DATAB
data_in[10] => data_temp~21.DATAB
data_in[10] => data_temp~5.DATAB
data_in[11] => data_temp~20.DATAB
data_in[11] => data_temp~4.DATAB
data_in[12] => data_temp~19.DATAB
data_in[12] => data_temp~3.DATAB
data_in[13] => data_temp~18.DATAB
data_in[13] => data_temp~2.DATAB
data_in[14] => data_temp~17.DATAB
data_in[14] => data_temp~1.DATAB
data_in[15] => data_temp~16.DATAB
data_in[15] => data_temp~0.DATAB
data_out0[0] <= data_out0~16.DB_MAX_OUTPUT_PORT_TYPE
data_out0[1] <= data_out0~15.DB_MAX_OUTPUT_PORT_TYPE
data_out0[2] <= data_out0~14.DB_MAX_OUTPUT_PORT_TYPE
data_out0[3] <= data_out0~13.DB_MAX_OUTPUT_PORT_TYPE
data_out0[4] <= data_out0~12.DB_MAX_OUTPUT_PORT_TYPE
data_out0[5] <= data_out0~11.DB_MAX_OUTPUT_PORT_TYPE
data_out0[6] <= data_out0~10.DB_MAX_OUTPUT_PORT_TYPE
data_out0[7] <= data_out0~9.DB_MAX_OUTPUT_PORT_TYPE
data_out0[8] <= data_out0~8.DB_MAX_OUTPUT_PORT_TYPE
data_out0[9] <= data_out0~7.DB_MAX_OUTPUT_PORT_TYPE
data_out0[10] <= data_out0~6.DB_MAX_OUTPUT_PORT_TYPE
data_out0[11] <= data_out0~5.DB_MAX_OUTPUT_PORT_TYPE
data_out0[12] <= data_out0~4.DB_MAX_OUTPUT_PORT_TYPE
data_out0[13] <= data_out0~3.DB_MAX_OUTPUT_PORT_TYPE
data_out0[14] <= data_out0~2.DB_MAX_OUTPUT_PORT_TYPE
data_out0[15] <= data_out0~1.DB_MAX_OUTPUT_PORT_TYPE
data_out1[0] <= data_out1~15.DB_MAX_OUTPUT_PORT_TYPE
data_out1[1] <= data_out1~14.DB_MAX_OUTPUT_PORT_TYPE
data_out1[2] <= data_out1~13.DB_MAX_OUTPUT_PORT_TYPE
data_out1[3] <= data_out1~12.DB_MAX_OUTPUT_PORT_TYPE
data_out1[4] <= data_out1~11.DB_MAX_OUTPUT_PORT_TYPE
data_out1[5] <= data_out1~10.DB_MAX_OUTPUT_PORT_TYPE
data_out1[6] <= data_out1~9.DB_MAX_OUTPUT_PORT_TYPE
data_out1[7] <= data_out1~8.DB_MAX_OUTPUT_PORT_TYPE
data_out1[8] <= data_out1~7.DB_MAX_OUTPUT_PORT_TYPE
data_out1[9] <= data_out1~6.DB_MAX_OUTPUT_PORT_TYPE
data_out1[10] <= data_out1~5.DB_MAX_OUTPUT_PORT_TYPE
data_out1[11] <= data_out1~4.DB_MAX_OUTPUT_PORT_TYPE
data_out1[12] <= data_out1~3.DB_MAX_OUTPUT_PORT_TYPE
data_out1[13] <= data_out1~2.DB_MAX_OUTPUT_PORT_TYPE
data_out1[14] <= data_out1~1.DB_MAX_OUTPUT_PORT_TYPE
data_out1[15] <= data_out1~0.DB_MAX_OUTPUT_PORT_TYPE
source_valid <= source_valid~1.DB_MAX_OUTPUT_PORT_TYPE


|block|s2p:inst7
clk => count[6].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => cnt.CLK
clk => data_temp[1][15].CLK
clk => data_temp[1][14].CLK
clk => data_temp[1][13].CLK
clk => data_temp[1][12].CLK
clk => data_temp[1][11].CLK
clk => data_temp[1][10].CLK
clk => data_temp[1][9].CLK
clk => data_temp[1][8].CLK
clk => data_temp[1][7].CLK
clk => data_temp[1][6].CLK
clk => data_temp[1][5].CLK
clk => data_temp[1][4].CLK
clk => data_temp[1][3].CLK
clk => data_temp[1][2].CLK
clk => data_temp[1][1].CLK
clk => data_temp[1][0].CLK
clk => data_temp[0][15].CLK
clk => data_temp[0][14].CLK
clk => data_temp[0][13].CLK
clk => data_temp[0][12].CLK
clk => data_temp[0][11].CLK
clk => data_temp[0][10].CLK
clk => data_temp[0][9].CLK
clk => data_temp[0][8].CLK
clk => data_temp[0][7].CLK
clk => data_temp[0][6].CLK
clk => data_temp[0][5].CLK
clk => data_temp[0][4].CLK
clk => data_temp[0][3].CLK
clk => data_temp[0][2].CLK
clk => data_temp[0][1].CLK
clk => data_temp[0][0].CLK
reset => source_valid~0.IN0
reset => count[6].ACLR
reset => count[5].ACLR
reset => count[4].ACLR
reset => count[3].ACLR
reset => count[2].ACLR
reset => count[1].ACLR
reset => count[0].ACLR
reset => cnt.ACLR
reset => data_temp[1][15].ACLR
reset => data_temp[1][14].ACLR
reset => data_temp[1][13].ACLR
reset => data_temp[1][12].ACLR
reset => data_temp[1][11].ACLR
reset => data_temp[1][10].ACLR
reset => data_temp[1][9].ACLR
reset => data_temp[1][8].ACLR
reset => data_temp[1][7].ACLR
reset => data_temp[1][6].ACLR
reset => data_temp[1][5].ACLR
reset => data_temp[1][4].ACLR
reset => data_temp[1][3].ACLR
reset => data_temp[1][2].ACLR
reset => data_temp[1][1].ACLR
reset => data_temp[1][0].ACLR
reset => data_temp[0][15].ACLR
reset => data_temp[0][14].ACLR
reset => data_temp[0][13].ACLR
reset => data_temp[0][12].ACLR
reset => data_temp[0][11].ACLR
reset => data_temp[0][10].ACLR
reset => data_temp[0][9].ACLR
reset => data_temp[0][8].ACLR
reset => data_temp[0][7].ACLR
reset => data_temp[0][6].ACLR
reset => data_temp[0][5].ACLR
reset => data_temp[0][4].ACLR
reset => data_temp[0][3].ACLR
reset => data_temp[0][2].ACLR
reset => data_temp[0][1].ACLR
reset => data_temp[0][0].ACLR
sink_valid => data_temp~63.OUTPUTSELECT
sink_valid => data_temp~62.OUTPUTSELECT
sink_valid => data_temp~61.OUTPUTSELECT
sink_valid => data_temp~60.OUTPUTSELECT
sink_valid => data_temp~59.OUTPUTSELECT
sink_valid => data_temp~58.OUTPUTSELECT
sink_valid => data_temp~57.OUTPUTSELECT
sink_valid => data_temp~56.OUTPUTSELECT
sink_valid => data_temp~55.OUTPUTSELECT
sink_valid => data_temp~54.OUTPUTSELECT
sink_valid => data_temp~53.OUTPUTSELECT
sink_valid => data_temp~52.OUTPUTSELECT
sink_valid => data_temp~51.OUTPUTSELECT
sink_valid => data_temp~50.OUTPUTSELECT
sink_valid => data_temp~49.OUTPUTSELECT
sink_valid => data_temp~48.OUTPUTSELECT
sink_valid => data_temp~47.OUTPUTSELECT
sink_valid => data_temp~46.OUTPUTSELECT
sink_valid => data_temp~45.OUTPUTSELECT
sink_valid => data_temp~44.OUTPUTSELECT
sink_valid => data_temp~43.OUTPUTSELECT
sink_valid => data_temp~42.OUTPUTSELECT
sink_valid => data_temp~41.OUTPUTSELECT
sink_valid => data_temp~40.OUTPUTSELECT
sink_valid => data_temp~39.OUTPUTSELECT
sink_valid => data_temp~38.OUTPUTSELECT
sink_valid => data_temp~37.OUTPUTSELECT
sink_valid => data_temp~36.OUTPUTSELECT
sink_valid => data_temp~35.OUTPUTSELECT
sink_valid => data_temp~34.OUTPUTSELECT
sink_valid => data_temp~33.OUTPUTSELECT
sink_valid => data_temp~32.OUTPUTSELECT
sink_valid => count~13.OUTPUTSELECT
sink_valid => count~12.OUTPUTSELECT
sink_valid => count~11.OUTPUTSELECT
sink_valid => count~10.OUTPUTSELECT
sink_valid => count~9.OUTPUTSELECT
sink_valid => count~8.OUTPUTSELECT
sink_valid => count~7.OUTPUTSELECT
sink_valid => cnt~0.OUTPUTSELECT
data_in[0] => data_temp~31.DATAB
data_in[0] => data_temp~15.DATAB
data_in[1] => data_temp~30.DATAB
data_in[1] => data_temp~14.DATAB
data_in[2] => data_temp~29.DATAB
data_in[2] => data_temp~13.DATAB
data_in[3] => data_temp~28.DATAB
data_in[3] => data_temp~12.DATAB
data_in[4] => data_temp~27.DATAB
data_in[4] => data_temp~11.DATAB
data_in[5] => data_temp~26.DATAB
data_in[5] => data_temp~10.DATAB
data_in[6] => data_temp~25.DATAB
data_in[6] => data_temp~9.DATAB
data_in[7] => data_temp~24.DATAB
data_in[7] => data_temp~8.DATAB
data_in[8] => data_temp~23.DATAB
data_in[8] => data_temp~7.DATAB
data_in[9] => data_temp~22.DATAB
data_in[9] => data_temp~6.DATAB
data_in[10] => data_temp~21.DATAB
data_in[10] => data_temp~5.DATAB
data_in[11] => data_temp~20.DATAB
data_in[11] => data_temp~4.DATAB
data_in[12] => data_temp~19.DATAB
data_in[12] => data_temp~3.DATAB
data_in[13] => data_temp~18.DATAB
data_in[13] => data_temp~2.DATAB
data_in[14] => data_temp~17.DATAB
data_in[14] => data_temp~1.DATAB
data_in[15] => data_temp~16.DATAB
data_in[15] => data_temp~0.DATAB
data_out0[0] <= data_out0~16.DB_MAX_OUTPUT_PORT_TYPE
data_out0[1] <= data_out0~15.DB_MAX_OUTPUT_PORT_TYPE
data_out0[2] <= data_out0~14.DB_MAX_OUTPUT_PORT_TYPE
data_out0[3] <= data_out0~13.DB_MAX_OUTPUT_PORT_TYPE
data_out0[4] <= data_out0~12.DB_MAX_OUTPUT_PORT_TYPE
data_out0[5] <= data_out0~11.DB_MAX_OUTPUT_PORT_TYPE
data_out0[6] <= data_out0~10.DB_MAX_OUTPUT_PORT_TYPE
data_out0[7] <= data_out0~9.DB_MAX_OUTPUT_PORT_TYPE
data_out0[8] <= data_out0~8.DB_MAX_OUTPUT_PORT_TYPE
data_out0[9] <= data_out0~7.DB_MAX_OUTPUT_PORT_TYPE
data_out0[10] <= data_out0~6.DB_MAX_OUTPUT_PORT_TYPE
data_out0[11] <= data_out0~5.DB_MAX_OUTPUT_PORT_TYPE
data_out0[12] <= data_out0~4.DB_MAX_OUTPUT_PORT_TYPE
data_out0[13] <= data_out0~3.DB_MAX_OUTPUT_PORT_TYPE
data_out0[14] <= data_out0~2.DB_MAX_OUTPUT_PORT_TYPE
data_out0[15] <= data_out0~1.DB_MAX_OUTPUT_PORT_TYPE
data_out1[0] <= data_out1~15.DB_MAX_OUTPUT_PORT_TYPE
data_out1[1] <= data_out1~14.DB_MAX_OUTPUT_PORT_TYPE
data_out1[2] <= data_out1~13.DB_MAX_OUTPUT_PORT_TYPE
data_out1[3] <= data_out1~12.DB_MAX_OUTPUT_PORT_TYPE
data_out1[4] <= data_out1~11.DB_MAX_OUTPUT_PORT_TYPE
data_out1[5] <= data_out1~10.DB_MAX_OUTPUT_PORT_TYPE
data_out1[6] <= data_out1~9.DB_MAX_OUTPUT_PORT_TYPE
data_out1[7] <= data_out1~8.DB_MAX_OUTPUT_PORT_TYPE
data_out1[8] <= data_out1~7.DB_MAX_OUTPUT_PORT_TYPE
data_out1[9] <= data_out1~6.DB_MAX_OUTPUT_PORT_TYPE
data_out1[10] <= data_out1~5.DB_MAX_OUTPUT_PORT_TYPE
data_out1[11] <= data_out1~4.DB_MAX_OUTPUT_PORT_TYPE
data_out1[12] <= data_out1~3.DB_MAX_OUTPUT_PORT_TYPE
data_out1[13] <= data_out1~2.DB_MAX_OUTPUT_PORT_TYPE
data_out1[14] <= data_out1~1.DB_MAX_OUTPUT_PORT_TYPE
data_out1[15] <= data_out1~0.DB_MAX_OUTPUT_PORT_TYPE
source_valid <= source_valid~1.DB_MAX_OUTPUT_PORT_TYPE


|block|D:inst16
reset => temp[15].ACLR
reset => temp[14].ACLR
reset => temp[13].ACLR
reset => temp[12].ACLR
reset => temp[11].ACLR
reset => temp[10].ACLR
reset => temp[9].ACLR
reset => temp[8].ACLR
reset => temp[7].ACLR
reset => temp[6].ACLR
reset => temp[5].ACLR
reset => temp[4].ACLR
reset => temp[3].ACLR
reset => temp[2].ACLR
reset => temp[1].ACLR
reset => temp[0].ACLR
clk => temp[15].CLK
clk => temp[14].CLK
clk => temp[13].CLK
clk => temp[12].CLK
clk => temp[11].CLK
clk => temp[10].CLK
clk => temp[9].CLK
clk => temp[8].CLK
clk => temp[7].CLK
clk => temp[6].CLK
clk => temp[5].CLK
clk => temp[4].CLK
clk => temp[3].CLK
clk => temp[2].CLK
clk => temp[1].CLK
clk => temp[0].CLK
data_in[0] => temp[0].DATAIN
data_in[1] => temp[1].DATAIN
data_in[2] => temp[2].DATAIN
data_in[3] => temp[3].DATAIN
data_in[4] => temp[4].DATAIN
data_in[5] => temp[5].DATAIN
data_in[6] => temp[6].DATAIN
data_in[7] => temp[7].DATAIN
data_in[8] => temp[8].DATAIN
data_in[9] => temp[9].DATAIN
data_in[10] => temp[10].DATAIN
data_in[11] => temp[11].DATAIN
data_in[12] => temp[12].DATAIN
data_in[13] => temp[13].DATAIN
data_in[14] => temp[14].DATAIN
data_in[15] => temp[15].DATAIN
data_out[0] <= temp[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= temp[1].DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= temp[2].DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= temp[3].DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= temp[4].DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= temp[5].DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= temp[6].DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= temp[7].DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= temp[8].DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= temp[9].DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= temp[10].DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= temp[11].DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= temp[12].DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= temp[13].DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= temp[14].DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= temp[15].DB_MAX_OUTPUT_PORT_TYPE


|block|D:inst15
reset => temp[15].ACLR
reset => temp[14].ACLR
reset => temp[13].ACLR
reset => temp[12].ACLR
reset => temp[11].ACLR
reset => temp[10].ACLR
reset => temp[9].ACLR
reset => temp[8].ACLR
reset => temp[7].ACLR
reset => temp[6].ACLR
reset => temp[5].ACLR
reset => temp[4].ACLR
reset => temp[3].ACLR
reset => temp[2].ACLR
reset => temp[1].ACLR
reset => temp[0].ACLR
clk => temp[15].CLK
clk => temp[14].CLK
clk => temp[13].CLK
clk => temp[12].CLK
clk => temp[11].CLK
clk => temp[10].CLK
clk => temp[9].CLK
clk => temp[8].CLK
clk => temp[7].CLK
clk => temp[6].CLK
clk => temp[5].CLK
clk => temp[4].CLK
clk => temp[3].CLK
clk => temp[2].CLK
clk => temp[1].CLK
clk => temp[0].CLK
data_in[0] => temp[0].DATAIN
data_in[1] => temp[1].DATAIN
data_in[2] => temp[2].DATAIN
data_in[3] => temp[3].DATAIN
data_in[4] => temp[4].DATAIN
data_in[5] => temp[5].DATAIN
data_in[6] => temp[6].DATAIN
data_in[7] => temp[7].DATAIN
data_in[8] => temp[8].DATAIN
data_in[9] => temp[9].DATAIN
data_in[10] => temp[10].DATAIN
data_in[11] => temp[11].DATAIN
data_in[12] => temp[12].DATAIN
data_in[13] => temp[13].DATAIN
data_in[14] => temp[14].DATAIN
data_in[15] => temp[15].DATAIN
data_out[0] <= temp[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= temp[1].DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= temp[2].DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= temp[3].DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= temp[4].DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= temp[5].DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= temp[6].DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= temp[7].DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= temp[8].DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= temp[9].DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= temp[10].DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= temp[11].DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= temp[12].DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= temp[13].DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= temp[14].DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= temp[15].DB_MAX_OUTPUT_PORT_TYPE


|block|lpm_rom1:inst2
aclr => aclr~0.IN1
address[0] => address[0]~4.IN1
address[1] => address[1]~3.IN1
address[2] => address[2]~2.IN1
address[3] => address[3]~1.IN1
address[4] => address[4]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
q[8] <= altsyncram:altsyncram_component.q_a
q[9] <= altsyncram:altsyncram_component.q_a
q[10] <= altsyncram:altsyncram_component.q_a
q[11] <= altsyncram:altsyncram_component.q_a
q[12] <= altsyncram:altsyncram_component.q_a
q[13] <= altsyncram:altsyncram_component.q_a
q[14] <= altsyncram:altsyncram_component.q_a
q[15] <= altsyncram:altsyncram_component.q_a


|block|lpm_rom1:inst2|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_a[13] => ~NO_FANOUT~
data_a[14] => ~NO_FANOUT~
data_a[15] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_qq71:auto_generated.address_a[0]
address_a[1] => altsyncram_qq71:auto_generated.address_a[1]
address_a[2] => altsyncram_qq71:auto_generated.address_a[2]
address_a[3] => altsyncram_qq71:auto_generated.address_a[3]
address_a[4] => altsyncram_qq71:auto_generated.address_a[4]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_qq71:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => altsyncram_qq71:auto_generated.aclr0
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_qq71:auto_generated.q_a[0]
q_a[1] <= altsyncram_qq71:auto_generated.q_a[1]
q_a[2] <= altsyncram_qq71:auto_generated.q_a[2]
q_a[3] <= altsyncram_qq71:auto_generated.q_a[3]
q_a[4] <= altsyncram_qq71:auto_generated.q_a[4]
q_a[5] <= altsyncram_qq71:auto_generated.q_a[5]
q_a[6] <= altsyncram_qq71:auto_generated.q_a[6]
q_a[7] <= altsyncram_qq71:auto_generated.q_a[7]
q_a[8] <= altsyncram_qq71:auto_generated.q_a[8]
q_a[9] <= altsyncram_qq71:auto_generated.q_a[9]
q_a[10] <= altsyncram_qq71:auto_generated.q_a[10]
q_a[11] <= altsyncram_qq71:auto_generated.q_a[11]
q_a[12] <= altsyncram_qq71:auto_generated.q_a[12]
q_a[13] <= altsyncram_qq71:auto_generated.q_a[13]
q_a[14] <= altsyncram_qq71:auto_generated.q_a[14]
q_a[15] <= altsyncram_qq71:auto_generated.q_a[15]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|block|lpm_rom1:inst2|altsyncram:altsyncram_component|altsyncram_qq71:auto_generated
aclr0 => ram_block1a0.CLR0
aclr0 => ram_block1a1.CLR0
aclr0 => ram_block1a2.CLR0
aclr0 => ram_block1a3.CLR0
aclr0 => ram_block1a4.CLR0
aclr0 => ram_block1a5.CLR0
aclr0 => ram_block1a6.CLR0
aclr0 => ram_block1a7.CLR0
aclr0 => ram_block1a8.CLR0
aclr0 => ram_block1a9.CLR0
aclr0 => ram_block1a10.CLR0
aclr0 => ram_block1a11.CLR0
aclr0 => ram_block1a12.CLR0
aclr0 => ram_block1a13.CLR0
aclr0 => ram_block1a14.CLR0
aclr0 => ram_block1a15.CLR0
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT
q_a[10] <= ram_block1a10.PORTADATAOUT
q_a[11] <= ram_block1a11.PORTADATAOUT
q_a[12] <= ram_block1a12.PORTADATAOUT
q_a[13] <= ram_block1a13.PORTADATAOUT
q_a[14] <= ram_block1a14.PORTADATAOUT
q_a[15] <= ram_block1a15.PORTADATAOUT


|block|D:inst14
reset => temp[15].ACLR
reset => temp[14].ACLR
reset => temp[13].ACLR
reset => temp[12].ACLR
reset => temp[11].ACLR
reset => temp[10].ACLR
reset => temp[9].ACLR
reset => temp[8].ACLR
reset => temp[7].ACLR
reset => temp[6].ACLR
reset => temp[5].ACLR
reset => temp[4].ACLR
reset => temp[3].ACLR
reset => temp[2].ACLR
reset => temp[1].ACLR
reset => temp[0].ACLR
clk => temp[15].CLK
clk => temp[14].CLK
clk => temp[13].CLK
clk => temp[12].CLK
clk => temp[11].CLK
clk => temp[10].CLK
clk => temp[9].CLK
clk => temp[8].CLK
clk => temp[7].CLK
clk => temp[6].CLK
clk => temp[5].CLK
clk => temp[4].CLK
clk => temp[3].CLK
clk => temp[2].CLK
clk => temp[1].CLK
clk => temp[0].CLK
data_in[0] => temp[0].DATAIN
data_in[1] => temp[1].DATAIN
data_in[2] => temp[2].DATAIN
data_in[3] => temp[3].DATAIN
data_in[4] => temp[4].DATAIN
data_in[5] => temp[5].DATAIN
data_in[6] => temp[6].DATAIN
data_in[7] => temp[7].DATAIN
data_in[8] => temp[8].DATAIN
data_in[9] => temp[9].DATAIN
data_in[10] => temp[10].DATAIN
data_in[11] => temp[11].DATAIN
data_in[12] => temp[12].DATAIN
data_in[13] => temp[13].DATAIN
data_in[14] => temp[14].DATAIN
data_in[15] => temp[15].DATAIN
data_out[0] <= temp[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= temp[1].DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= temp[2].DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= temp[3].DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= temp[4].DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= temp[5].DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= temp[6].DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= temp[7].DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= temp[8].DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= temp[9].DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= temp[10].DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= temp[11].DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= temp[12].DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= temp[13].DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= temp[14].DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= temp[15].DB_MAX_OUTPUT_PORT_TYPE


|block|D:inst11
reset => temp[15].ACLR
reset => temp[14].ACLR
reset => temp[13].ACLR
reset => temp[12].ACLR
reset => temp[11].ACLR
reset => temp[10].ACLR
reset => temp[9].ACLR
reset => temp[8].ACLR
reset => temp[7].ACLR
reset => temp[6].ACLR
reset => temp[5].ACLR
reset => temp[4].ACLR
reset => temp[3].ACLR
reset => temp[2].ACLR
reset => temp[1].ACLR
reset => temp[0].ACLR
clk => temp[15].CLK
clk => temp[14].CLK
clk => temp[13].CLK
clk => temp[12].CLK
clk => temp[11].CLK
clk => temp[10].CLK
clk => temp[9].CLK
clk => temp[8].CLK
clk => temp[7].CLK
clk => temp[6].CLK
clk => temp[5].CLK
clk => temp[4].CLK
clk => temp[3].CLK
clk => temp[2].CLK
clk => temp[1].CLK
clk => temp[0].CLK
data_in[0] => temp[0].DATAIN
data_in[1] => temp[1].DATAIN
data_in[2] => temp[2].DATAIN
data_in[3] => temp[3].DATAIN
data_in[4] => temp[4].DATAIN
data_in[5] => temp[5].DATAIN
data_in[6] => temp[6].DATAIN
data_in[7] => temp[7].DATAIN
data_in[8] => temp[8].DATAIN
data_in[9] => temp[9].DATAIN
data_in[10] => temp[10].DATAIN
data_in[11] => temp[11].DATAIN
data_in[12] => temp[12].DATAIN
data_in[13] => temp[13].DATAIN
data_in[14] => temp[14].DATAIN
data_in[15] => temp[15].DATAIN
data_out[0] <= temp[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= temp[1].DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= temp[2].DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= temp[3].DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= temp[4].DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= temp[5].DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= temp[6].DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= temp[7].DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= temp[8].DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= temp[9].DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= temp[10].DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= temp[11].DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= temp[12].DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= temp[13].DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= temp[14].DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= temp[15].DB_MAX_OUTPUT_PORT_TYPE


|block|lpm_rom0:inst1
aclr => aclr~0.IN1
address[0] => address[0]~4.IN1
address[1] => address[1]~3.IN1
address[2] => address[2]~2.IN1
address[3] => address[3]~1.IN1
address[4] => address[4]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
q[8] <= altsyncram:altsyncram_component.q_a
q[9] <= altsyncram:altsyncram_component.q_a
q[10] <= altsyncram:altsyncram_component.q_a
q[11] <= altsyncram:altsyncram_component.q_a
q[12] <= altsyncram:altsyncram_component.q_a
q[13] <= altsyncram:altsyncram_component.q_a
q[14] <= altsyncram:altsyncram_component.q_a
q[15] <= altsyncram:altsyncram_component.q_a


|block|lpm_rom0:inst1|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_a[13] => ~NO_FANOUT~
data_a[14] => ~NO_FANOUT~
data_a[15] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_oh91:auto_generated.address_a[0]
address_a[1] => altsyncram_oh91:auto_generated.address_a[1]
address_a[2] => altsyncram_oh91:auto_generated.address_a[2]
address_a[3] => altsyncram_oh91:auto_generated.address_a[3]
address_a[4] => altsyncram_oh91:auto_generated.address_a[4]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_oh91:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => altsyncram_oh91:auto_generated.aclr0
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_oh91:auto_generated.q_a[0]
q_a[1] <= altsyncram_oh91:auto_generated.q_a[1]
q_a[2] <= altsyncram_oh91:auto_generated.q_a[2]
q_a[3] <= altsyncram_oh91:auto_generated.q_a[3]
q_a[4] <= altsyncram_oh91:auto_generated.q_a[4]
q_a[5] <= altsyncram_oh91:auto_generated.q_a[5]
q_a[6] <= altsyncram_oh91:auto_generated.q_a[6]
q_a[7] <= altsyncram_oh91:auto_generated.q_a[7]
q_a[8] <= altsyncram_oh91:auto_generated.q_a[8]
q_a[9] <= altsyncram_oh91:auto_generated.q_a[9]
q_a[10] <= altsyncram_oh91:auto_generated.q_a[10]
q_a[11] <= altsyncram_oh91:auto_generated.q_a[11]
q_a[12] <= altsyncram_oh91:auto_generated.q_a[12]
q_a[13] <= altsyncram_oh91:auto_generated.q_a[13]
q_a[14] <= altsyncram_oh91:auto_generated.q_a[14]
q_a[15] <= altsyncram_oh91:auto_generated.q_a[15]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|block|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_oh91:auto_generated
aclr0 => ram_block1a0.CLR0
aclr0 => ram_block1a1.CLR0
aclr0 => ram_block1a2.CLR0
aclr0 => ram_block1a3.CLR0
aclr0 => ram_block1a4.CLR0
aclr0 => ram_block1a5.CLR0
aclr0 => ram_block1a6.CLR0
aclr0 => ram_block1a7.CLR0
aclr0 => ram_block1a8.CLR0
aclr0 => ram_block1a9.CLR0
aclr0 => ram_block1a10.CLR0
aclr0 => ram_block1a11.CLR0
aclr0 => ram_block1a12.CLR0
aclr0 => ram_block1a13.CLR0
aclr0 => ram_block1a14.CLR0
aclr0 => ram_block1a15.CLR0
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT
q_a[10] <= ram_block1a10.PORTADATAOUT
q_a[11] <= ram_block1a11.PORTADATAOUT
q_a[12] <= ram_block1a12.PORTADATAOUT
q_a[13] <= ram_block1a13.PORTADATAOUT
q_a[14] <= ram_block1a14.PORTADATAOUT
q_a[15] <= ram_block1a15.PORTADATAOUT


|block|lpm_fifo0:inst
aclr => aclr~0.IN1
clock => clock~0.IN1
data[0] => data[0]~17.IN1
data[1] => data[1]~16.IN1
data[2] => data[2]~15.IN1
data[3] => data[3]~14.IN1
data[4] => data[4]~13.IN1
data[5] => data[5]~12.IN1
data[6] => data[6]~11.IN1
data[7] => data[7]~10.IN1
data[8] => data[8]~9.IN1
data[9] => data[9]~8.IN1
data[10] => data[10]~7.IN1
data[11] => data[11]~6.IN1
data[12] => data[12]~5.IN1
data[13] => data[13]~4.IN1
data[14] => data[14]~3.IN1
data[15] => data[15]~2.IN1
data[16] => data[16]~1.IN1
data[17] => data[17]~0.IN1
rdreq => rdreq~0.IN1
wrreq => wrreq~0.IN1
empty <= scfifo:scfifo_component.empty
full <= scfifo:scfifo_component.full
q[0] <= scfifo:scfifo_component.q
q[1] <= scfifo:scfifo_component.q
q[2] <= scfifo:scfifo_component.q
q[3] <= scfifo:scfifo_component.q
q[4] <= scfifo:scfifo_component.q
q[5] <= scfifo:scfifo_component.q
q[6] <= scfifo:scfifo_component.q
q[7] <= scfifo:scfifo_component.q
q[8] <= scfifo:scfifo_component.q
q[9] <= scfifo:scfifo_component.q
q[10] <= scfifo:scfifo_component.q
q[11] <= scfifo:scfifo_component.q
q[12] <= scfifo:scfifo_component.q
q[13] <= scfifo:scfifo_component.q
q[14] <= scfifo:scfifo_component.q
q[15] <= scfifo:scfifo_component.q
q[16] <= scfifo:scfifo_component.q
q[17] <= scfifo:scfifo_component.q
usedw[0] <= scfifo:scfifo_component.usedw
usedw[1] <= scfifo:scfifo_component.usedw
usedw[2] <= scfifo:scfifo_component.usedw
usedw[3] <= scfifo:scfifo_component.usedw
usedw[4] <= scfifo:scfifo_component.usedw
usedw[5] <= scfifo:scfifo_component.usedw


|block|lpm_fifo0:inst|scfifo:scfifo_component
data[0] => scfifo_7r31:auto_generated.data[0]
data[1] => scfifo_7r31:auto_generated.data[1]
data[2] => scfifo_7r31:auto_generated.data[2]
data[3] => scfifo_7r31:auto_generated.data[3]
data[4] => scfifo_7r31:auto_generated.data[4]
data[5] => scfifo_7r31:auto_generated.data[5]
data[6] => scfifo_7r31:auto_generated.data[6]
data[7] => scfifo_7r31:auto_generated.data[7]
data[8] => scfifo_7r31:auto_generated.data[8]
data[9] => scfifo_7r31:auto_generated.data[9]
data[10] => scfifo_7r31:auto_generated.data[10]
data[11] => scfifo_7r31:auto_generated.data[11]
data[12] => scfifo_7r31:auto_generated.data[12]
data[13] => scfifo_7r31:auto_generated.data[13]
data[14] => scfifo_7r31:auto_generated.data[14]
data[15] => scfifo_7r31:auto_generated.data[15]
data[16] => scfifo_7r31:auto_generated.data[16]
data[17] => scfifo_7r31:auto_generated.data[17]
q[0] <= scfifo_7r31:auto_generated.q[0]
q[1] <= scfifo_7r31:auto_generated.q[1]
q[2] <= scfifo_7r31:auto_generated.q[2]
q[3] <= scfifo_7r31:auto_generated.q[3]
q[4] <= scfifo_7r31:auto_generated.q[4]
q[5] <= scfifo_7r31:auto_generated.q[5]
q[6] <= scfifo_7r31:auto_generated.q[6]
q[7] <= scfifo_7r31:auto_generated.q[7]
q[8] <= scfifo_7r31:auto_generated.q[8]
q[9] <= scfifo_7r31:auto_generated.q[9]
q[10] <= scfifo_7r31:auto_generated.q[10]
q[11] <= scfifo_7r31:auto_generated.q[11]
q[12] <= scfifo_7r31:auto_generated.q[12]
q[13] <= scfifo_7r31:auto_generated.q[13]
q[14] <= scfifo_7r31:auto_generated.q[14]
q[15] <= scfifo_7r31:auto_generated.q[15]
q[16] <= scfifo_7r31:auto_generated.q[16]
q[17] <= scfifo_7r31:auto_generated.q[17]
wrreq => scfifo_7r31:auto_generated.wrreq
rdreq => scfifo_7r31:auto_generated.rdreq
clock => scfifo_7r31:auto_generated.clock
aclr => scfifo_7r31:auto_generated.aclr
sclr => ~NO_FANOUT~
empty <= scfifo_7r31:auto_generated.empty
full <= scfifo_7r31:auto_generated.full
almost_full <= <GND>
almost_empty <= <GND>
usedw[0] <= scfifo_7r31:auto_generated.usedw[0]
usedw[1] <= scfifo_7r31:auto_generated.usedw[1]
usedw[2] <= scfifo_7r31:auto_generated.usedw[2]
usedw[3] <= scfifo_7r31:auto_generated.usedw[3]
usedw[4] <= scfifo_7r31:auto_generated.usedw[4]
usedw[5] <= scfifo_7r31:auto_generated.usedw[5]


|block|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated
aclr => a_dpfifo_e141:dpfifo.aclr
clock => a_dpfifo_e141:dpfifo.clock
data[0] => a_dpfifo_e141:dpfifo.data[0]
data[1] => a_dpfifo_e141:dpfifo.data[1]
data[2] => a_dpfifo_e141:dpfifo.data[2]
data[3] => a_dpfifo_e141:dpfifo.data[3]
data[4] => a_dpfifo_e141:dpfifo.data[4]
data[5] => a_dpfifo_e141:dpfifo.data[5]
data[6] => a_dpfifo_e141:dpfifo.data[6]
data[7] => a_dpfifo_e141:dpfifo.data[7]
data[8] => a_dpfifo_e141:dpfifo.data[8]
data[9] => a_dpfifo_e141:dpfifo.data[9]
data[10] => a_dpfifo_e141:dpfifo.data[10]
data[11] => a_dpfifo_e141:dpfifo.data[11]
data[12] => a_dpfifo_e141:dpfifo.data[12]
data[13] => a_dpfifo_e141:dpfifo.data[13]
data[14] => a_dpfifo_e141:dpfifo.data[14]
data[15] => a_dpfifo_e141:dpfifo.data[15]
data[16] => a_dpfifo_e141:dpfifo.data[16]
data[17] => a_dpfifo_e141:dpfifo.data[17]
empty <= a_dpfifo_e141:dpfifo.empty
full <= a_dpfifo_e141:dpfifo.full
q[0] <= a_dpfifo_e141:dpfifo.q[0]
q[1] <= a_dpfifo_e141:dpfifo.q[1]
q[2] <= a_dpfifo_e141:dpfifo.q[2]
q[3] <= a_dpfifo_e141:dpfifo.q[3]
q[4] <= a_dpfifo_e141:dpfifo.q[4]
q[5] <= a_dpfifo_e141:dpfifo.q[5]
q[6] <= a_dpfifo_e141:dpfifo.q[6]
q[7] <= a_dpfifo_e141:dpfifo.q[7]
q[8] <= a_dpfifo_e141:dpfifo.q[8]
q[9] <= a_dpfifo_e141:dpfifo.q[9]
q[10] <= a_dpfifo_e141:dpfifo.q[10]
q[11] <= a_dpfifo_e141:dpfifo.q[11]
q[12] <= a_dpfifo_e141:dpfifo.q[12]
q[13] <= a_dpfifo_e141:dpfifo.q[13]
q[14] <= a_dpfifo_e141:dpfifo.q[14]
q[15] <= a_dpfifo_e141:dpfifo.q[15]
q[16] <= a_dpfifo_e141:dpfifo.q[16]
q[17] <= a_dpfifo_e141:dpfifo.q[17]
rdreq => a_dpfifo_e141:dpfifo.rreq
usedw[0] <= a_dpfifo_e141:dpfifo.usedw[0]
usedw[1] <= a_dpfifo_e141:dpfifo.usedw[1]
usedw[2] <= a_dpfifo_e141:dpfifo.usedw[2]
usedw[3] <= a_dpfifo_e141:dpfifo.usedw[3]
usedw[4] <= a_dpfifo_e141:dpfifo.usedw[4]
usedw[5] <= a_dpfifo_e141:dpfifo.usedw[5]
wrreq => a_dpfifo_e141:dpfifo.wreq


|block|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo
aclr => a_fefifo_b6f:fifo_state.aclr
aclr => cntr_fjb:rd_ptr_count.aclr
aclr => cntr_fjb:wr_ptr.aclr
clock => a_fefifo_b6f:fifo_state.clock
clock => dpram_fv01:FIFOram.inclock
clock => dpram_fv01:FIFOram.outclock
clock => cntr_fjb:rd_ptr_count.clock
clock => cntr_fjb:wr_ptr.clock
data[0] => dpram_fv01:FIFOram.data[0]
data[1] => dpram_fv01:FIFOram.data[1]
data[2] => dpram_fv01:FIFOram.data[2]
data[3] => dpram_fv01:FIFOram.data[3]
data[4] => dpram_fv01:FIFOram.data[4]
data[5] => dpram_fv01:FIFOram.data[5]
data[6] => dpram_fv01:FIFOram.data[6]
data[7] => dpram_fv01:FIFOram.data[7]
data[8] => dpram_fv01:FIFOram.data[8]
data[9] => dpram_fv01:FIFOram.data[9]
data[10] => dpram_fv01:FIFOram.data[10]
data[11] => dpram_fv01:FIFOram.data[11]
data[12] => dpram_fv01:FIFOram.data[12]
data[13] => dpram_fv01:FIFOram.data[13]
data[14] => dpram_fv01:FIFOram.data[14]
data[15] => dpram_fv01:FIFOram.data[15]
data[16] => dpram_fv01:FIFOram.data[16]
data[17] => dpram_fv01:FIFOram.data[17]
empty <= a_fefifo_b6f:fifo_state.empty
full <= a_fefifo_b6f:fifo_state.full
q[0] <= dpram_fv01:FIFOram.q[0]
q[1] <= dpram_fv01:FIFOram.q[1]
q[2] <= dpram_fv01:FIFOram.q[2]
q[3] <= dpram_fv01:FIFOram.q[3]
q[4] <= dpram_fv01:FIFOram.q[4]
q[5] <= dpram_fv01:FIFOram.q[5]
q[6] <= dpram_fv01:FIFOram.q[6]
q[7] <= dpram_fv01:FIFOram.q[7]
q[8] <= dpram_fv01:FIFOram.q[8]
q[9] <= dpram_fv01:FIFOram.q[9]
q[10] <= dpram_fv01:FIFOram.q[10]
q[11] <= dpram_fv01:FIFOram.q[11]
q[12] <= dpram_fv01:FIFOram.q[12]
q[13] <= dpram_fv01:FIFOram.q[13]
q[14] <= dpram_fv01:FIFOram.q[14]
q[15] <= dpram_fv01:FIFOram.q[15]
q[16] <= dpram_fv01:FIFOram.q[16]
q[17] <= dpram_fv01:FIFOram.q[17]
rreq => a_fefifo_b6f:fifo_state.rreq
rreq => valid_rreq.IN0
sclr => a_fefifo_b6f:fifo_state.sclr
sclr => cntr_fjb:rd_ptr_count.sclr
sclr => cntr_fjb:wr_ptr.sclr
usedw[0] <= a_fefifo_b6f:fifo_state.usedw_out[0]
usedw[1] <= a_fefifo_b6f:fifo_state.usedw_out[1]
usedw[2] <= a_fefifo_b6f:fifo_state.usedw_out[2]
usedw[3] <= a_fefifo_b6f:fifo_state.usedw_out[3]
usedw[4] <= a_fefifo_b6f:fifo_state.usedw_out[4]
usedw[5] <= a_fefifo_b6f:fifo_state.usedw_out[5]
wreq => a_fefifo_b6f:fifo_state.wreq
wreq => valid_wreq.IN0


|block|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|a_fefifo_b6f:fifo_state
aclr => cntr_tk7:count_usedw.aclr
clock => cntr_tk7:count_usedw.clock
clock => b_full.CLK
clock => b_non_empty.CLK
full <= b_full.DB_MAX_OUTPUT_PORT_TYPE
rreq => valid_rreq.IN0
sclr => cntr_tk7:count_usedw.sclr
usedw_out[0] <= usedw[0].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[1] <= usedw[1].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[2] <= usedw[2].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[3] <= usedw[3].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[4] <= usedw[4].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[5] <= usedw[5].DB_MAX_OUTPUT_PORT_TYPE
wreq => valid_wreq.IN0


|block|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|a_fefifo_b6f:fifo_state|cntr_tk7:count_usedw
aclr => counter_reg_bit1a[5].ACLR
aclr => counter_reg_bit1a[4].ACLR
aclr => counter_reg_bit1a[3].ACLR
aclr => counter_reg_bit1a[2].ACLR
aclr => counter_reg_bit1a[1].ACLR
aclr => counter_reg_bit1a[0].ACLR
clock => counter_reg_bit1a[5].CLK
clock => counter_reg_bit1a[4].CLK
clock => counter_reg_bit1a[3].CLK
clock => counter_reg_bit1a[2].CLK
clock => counter_reg_bit1a[1].CLK
clock => counter_reg_bit1a[0].CLK
q[0] <= counter_reg_bit1a[0].REGOUT
q[1] <= counter_reg_bit1a[1].REGOUT
q[2] <= counter_reg_bit1a[2].REGOUT
q[3] <= counter_reg_bit1a[3].REGOUT
q[4] <= counter_reg_bit1a[4].REGOUT
q[5] <= counter_reg_bit1a[5].REGOUT
updown => counter_comb_bita0.DATAB
updown => counter_comb_bita1.DATAB
updown => counter_comb_bita2.DATAB
updown => counter_comb_bita3.DATAB
updown => counter_comb_bita4.DATAB
updown => counter_comb_bita5.DATAB


|block|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|dpram_fv01:FIFOram
data[0] => altsyncram_avj1:altsyncram1.data_a[0]
data[1] => altsyncram_avj1:altsyncram1.data_a[1]
data[2] => altsyncram_avj1:altsyncram1.data_a[2]
data[3] => altsyncram_avj1:altsyncram1.data_a[3]
data[4] => altsyncram_avj1:altsyncram1.data_a[4]
data[5] => altsyncram_avj1:altsyncram1.data_a[5]
data[6] => altsyncram_avj1:altsyncram1.data_a[6]
data[7] => altsyncram_avj1:altsyncram1.data_a[7]
data[8] => altsyncram_avj1:altsyncram1.data_a[8]
data[9] => altsyncram_avj1:altsyncram1.data_a[9]
data[10] => altsyncram_avj1:altsyncram1.data_a[10]
data[11] => altsyncram_avj1:altsyncram1.data_a[11]
data[12] => altsyncram_avj1:altsyncram1.data_a[12]
data[13] => altsyncram_avj1:altsyncram1.data_a[13]
data[14] => altsyncram_avj1:altsyncram1.data_a[14]
data[15] => altsyncram_avj1:altsyncram1.data_a[15]
data[16] => altsyncram_avj1:altsyncram1.data_a[16]
data[17] => altsyncram_avj1:altsyncram1.data_a[17]
inclock => altsyncram_avj1:altsyncram1.clock0
outclock => altsyncram_avj1:altsyncram1.clock1
outclocken => altsyncram_avj1:altsyncram1.clocken1
q[0] <= altsyncram_avj1:altsyncram1.q_b[0]
q[1] <= altsyncram_avj1:altsyncram1.q_b[1]
q[2] <= altsyncram_avj1:altsyncram1.q_b[2]
q[3] <= altsyncram_avj1:altsyncram1.q_b[3]
q[4] <= altsyncram_avj1:altsyncram1.q_b[4]
q[5] <= altsyncram_avj1:altsyncram1.q_b[5]
q[6] <= altsyncram_avj1:altsyncram1.q_b[6]
q[7] <= altsyncram_avj1:altsyncram1.q_b[7]
q[8] <= altsyncram_avj1:altsyncram1.q_b[8]
q[9] <= altsyncram_avj1:altsyncram1.q_b[9]
q[10] <= altsyncram_avj1:altsyncram1.q_b[10]
q[11] <= altsyncram_avj1:altsyncram1.q_b[11]
q[12] <= altsyncram_avj1:altsyncram1.q_b[12]
q[13] <= altsyncram_avj1:altsyncram1.q_b[13]
q[14] <= altsyncram_avj1:altsyncram1.q_b[14]
q[15] <= altsyncram_avj1:altsyncram1.q_b[15]
q[16] <= altsyncram_avj1:altsyncram1.q_b[16]
q[17] <= altsyncram_avj1:altsyncram1.q_b[17]
rdaddress[0] => altsyncram_avj1:altsyncram1.address_b[0]
rdaddress[1] => altsyncram_avj1:altsyncram1.address_b[1]
rdaddress[2] => altsyncram_avj1:altsyncram1.address_b[2]
rdaddress[3] => altsyncram_avj1:altsyncram1.address_b[3]
rdaddress[4] => altsyncram_avj1:altsyncram1.address_b[4]
rdaddress[5] => altsyncram_avj1:altsyncram1.address_b[5]
wraddress[0] => altsyncram_avj1:altsyncram1.address_a[0]
wraddress[1] => altsyncram_avj1:altsyncram1.address_a[1]
wraddress[2] => altsyncram_avj1:altsyncram1.address_a[2]
wraddress[3] => altsyncram_avj1:altsyncram1.address_a[3]
wraddress[4] => altsyncram_avj1:altsyncram1.address_a[4]
wraddress[5] => altsyncram_avj1:altsyncram1.address_a[5]
wren => altsyncram_avj1:altsyncram1.wren_a


|block|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|dpram_fv01:FIFOram|altsyncram_avj1:altsyncram1
address_a[0] => ram_block2a0.PORTAADDR
address_a[0] => ram_block2a1.PORTAADDR
address_a[0] => ram_block2a2.PORTAADDR
address_a[0] => ram_block2a3.PORTAADDR
address_a[0] => ram_block2a4.PORTAADDR
address_a[0] => ram_block2a5.PORTAADDR
address_a[0] => ram_block2a6.PORTAADDR
address_a[0] => ram_block2a7.PORTAADDR
address_a[0] => ram_block2a8.PORTAADDR
address_a[0] => ram_block2a9.PORTAADDR
address_a[0] => ram_block2a10.PORTAADDR
address_a[0] => ram_block2a11.PORTAADDR
address_a[0] => ram_block2a12.PORTAADDR
address_a[0] => ram_block2a13.PORTAADDR
address_a[0] => ram_block2a14.PORTAADDR
address_a[0] => ram_block2a15.PORTAADDR
address_a[0] => ram_block2a16.PORTAADDR
address_a[0] => ram_block2a17.PORTAADDR
address_a[1] => ram_block2a0.PORTAADDR1
address_a[1] => ram_block2a1.PORTAADDR1
address_a[1] => ram_block2a2.PORTAADDR1
address_a[1] => ram_block2a3.PORTAADDR1
address_a[1] => ram_block2a4.PORTAADDR1
address_a[1] => ram_block2a5.PORTAADDR1
address_a[1] => ram_block2a6.PORTAADDR1
address_a[1] => ram_block2a7.PORTAADDR1
address_a[1] => ram_block2a8.PORTAADDR1
address_a[1] => ram_block2a9.PORTAADDR1
address_a[1] => ram_block2a10.PORTAADDR1
address_a[1] => ram_block2a11.PORTAADDR1
address_a[1] => ram_block2a12.PORTAADDR1
address_a[1] => ram_block2a13.PORTAADDR1
address_a[1] => ram_block2a14.PORTAADDR1
address_a[1] => ram_block2a15.PORTAADDR1
address_a[1] => ram_block2a16.PORTAADDR1
address_a[1] => ram_block2a17.PORTAADDR1
address_a[2] => ram_block2a0.PORTAADDR2
address_a[2] => ram_block2a1.PORTAADDR2
address_a[2] => ram_block2a2.PORTAADDR2
address_a[2] => ram_block2a3.PORTAADDR2
address_a[2] => ram_block2a4.PORTAADDR2
address_a[2] => ram_block2a5.PORTAADDR2
address_a[2] => ram_block2a6.PORTAADDR2
address_a[2] => ram_block2a7.PORTAADDR2
address_a[2] => ram_block2a8.PORTAADDR2
address_a[2] => ram_block2a9.PORTAADDR2
address_a[2] => ram_block2a10.PORTAADDR2
address_a[2] => ram_block2a11.PORTAADDR2
address_a[2] => ram_block2a12.PORTAADDR2
address_a[2] => ram_block2a13.PORTAADDR2
address_a[2] => ram_block2a14.PORTAADDR2
address_a[2] => ram_block2a15.PORTAADDR2
address_a[2] => ram_block2a16.PORTAADDR2
address_a[2] => ram_block2a17.PORTAADDR2
address_a[3] => ram_block2a0.PORTAADDR3
address_a[3] => ram_block2a1.PORTAADDR3
address_a[3] => ram_block2a2.PORTAADDR3
address_a[3] => ram_block2a3.PORTAADDR3
address_a[3] => ram_block2a4.PORTAADDR3
address_a[3] => ram_block2a5.PORTAADDR3
address_a[3] => ram_block2a6.PORTAADDR3
address_a[3] => ram_block2a7.PORTAADDR3
address_a[3] => ram_block2a8.PORTAADDR3
address_a[3] => ram_block2a9.PORTAADDR3
address_a[3] => ram_block2a10.PORTAADDR3
address_a[3] => ram_block2a11.PORTAADDR3
address_a[3] => ram_block2a12.PORTAADDR3
address_a[3] => ram_block2a13.PORTAADDR3
address_a[3] => ram_block2a14.PORTAADDR3
address_a[3] => ram_block2a15.PORTAADDR3
address_a[3] => ram_block2a16.PORTAADDR3
address_a[3] => ram_block2a17.PORTAADDR3
address_a[4] => ram_block2a0.PORTAADDR4
address_a[4] => ram_block2a1.PORTAADDR4
address_a[4] => ram_block2a2.PORTAADDR4
address_a[4] => ram_block2a3.PORTAADDR4
address_a[4] => ram_block2a4.PORTAADDR4
address_a[4] => ram_block2a5.PORTAADDR4
address_a[4] => ram_block2a6.PORTAADDR4
address_a[4] => ram_block2a7.PORTAADDR4
address_a[4] => ram_block2a8.PORTAADDR4
address_a[4] => ram_block2a9.PORTAADDR4
address_a[4] => ram_block2a10.PORTAADDR4
address_a[4] => ram_block2a11.PORTAADDR4
address_a[4] => ram_block2a12.PORTAADDR4
address_a[4] => ram_block2a13.PORTAADDR4
address_a[4] => ram_block2a14.PORTAADDR4
address_a[4] => ram_block2a15.PORTAADDR4
address_a[4] => ram_block2a16.PORTAADDR4
address_a[4] => ram_block2a17.PORTAADDR4
address_a[5] => ram_block2a0.PORTAADDR5
address_a[5] => ram_block2a1.PORTAADDR5
address_a[5] => ram_block2a2.PORTAADDR5
address_a[5] => ram_block2a3.PORTAADDR5
address_a[5] => ram_block2a4.PORTAADDR5
address_a[5] => ram_block2a5.PORTAADDR5
address_a[5] => ram_block2a6.PORTAADDR5
address_a[5] => ram_block2a7.PORTAADDR5
address_a[5] => ram_block2a8.PORTAADDR5
address_a[5] => ram_block2a9.PORTAADDR5
address_a[5] => ram_block2a10.PORTAADDR5
address_a[5] => ram_block2a11.PORTAADDR5
address_a[5] => ram_block2a12.PORTAADDR5
address_a[5] => ram_block2a13.PORTAADDR5
address_a[5] => ram_block2a14.PORTAADDR5
address_a[5] => ram_block2a15.PORTAADDR5
address_a[5] => ram_block2a16.PORTAADDR5
address_a[5] => ram_block2a17.PORTAADDR5
address_b[0] => ram_block2a0.PORTBADDR
address_b[0] => ram_block2a1.PORTBADDR
address_b[0] => ram_block2a2.PORTBADDR
address_b[0] => ram_block2a3.PORTBADDR
address_b[0] => ram_block2a4.PORTBADDR
address_b[0] => ram_block2a5.PORTBADDR
address_b[0] => ram_block2a6.PORTBADDR
address_b[0] => ram_block2a7.PORTBADDR
address_b[0] => ram_block2a8.PORTBADDR
address_b[0] => ram_block2a9.PORTBADDR
address_b[0] => ram_block2a10.PORTBADDR
address_b[0] => ram_block2a11.PORTBADDR
address_b[0] => ram_block2a12.PORTBADDR
address_b[0] => ram_block2a13.PORTBADDR
address_b[0] => ram_block2a14.PORTBADDR
address_b[0] => ram_block2a15.PORTBADDR
address_b[0] => ram_block2a16.PORTBADDR
address_b[0] => ram_block2a17.PORTBADDR
address_b[1] => ram_block2a0.PORTBADDR1
address_b[1] => ram_block2a1.PORTBADDR1
address_b[1] => ram_block2a2.PORTBADDR1
address_b[1] => ram_block2a3.PORTBADDR1
address_b[1] => ram_block2a4.PORTBADDR1
address_b[1] => ram_block2a5.PORTBADDR1
address_b[1] => ram_block2a6.PORTBADDR1
address_b[1] => ram_block2a7.PORTBADDR1
address_b[1] => ram_block2a8.PORTBADDR1
address_b[1] => ram_block2a9.PORTBADDR1
address_b[1] => ram_block2a10.PORTBADDR1
address_b[1] => ram_block2a11.PORTBADDR1
address_b[1] => ram_block2a12.PORTBADDR1
address_b[1] => ram_block2a13.PORTBADDR1
address_b[1] => ram_block2a14.PORTBADDR1
address_b[1] => ram_block2a15.PORTBADDR1
address_b[1] => ram_block2a16.PORTBADDR1
address_b[1] => ram_block2a17.PORTBADDR1
address_b[2] => ram_block2a0.PORTBADDR2
address_b[2] => ram_block2a1.PORTBADDR2
address_b[2] => ram_block2a2.PORTBADDR2
address_b[2] => ram_block2a3.PORTBADDR2
address_b[2] => ram_block2a4.PORTBADDR2
address_b[2] => ram_block2a5.PORTBADDR2
address_b[2] => ram_block2a6.PORTBADDR2
address_b[2] => ram_block2a7.PORTBADDR2
address_b[2] => ram_block2a8.PORTBADDR2
address_b[2] => ram_block2a9.PORTBADDR2
address_b[2] => ram_block2a10.PORTBADDR2
address_b[2] => ram_block2a11.PORTBADDR2
address_b[2] => ram_block2a12.PORTBADDR2
address_b[2] => ram_block2a13.PORTBADDR2
address_b[2] => ram_block2a14.PORTBADDR2
address_b[2] => ram_block2a15.PORTBADDR2
address_b[2] => ram_block2a16.PORTBADDR2
address_b[2] => ram_block2a17.PORTBADDR2
address_b[3] => ram_block2a0.PORTBADDR3
address_b[3] => ram_block2a1.PORTBADDR3
address_b[3] => ram_block2a2.PORTBADDR3
address_b[3] => ram_block2a3.PORTBADDR3
address_b[3] => ram_block2a4.PORTBADDR3
address_b[3] => ram_block2a5.PORTBADDR3
address_b[3] => ram_block2a6.PORTBADDR3
address_b[3] => ram_block2a7.PORTBADDR3
address_b[3] => ram_block2a8.PORTBADDR3
address_b[3] => ram_block2a9.PORTBADDR3
address_b[3] => ram_block2a10.PORTBADDR3
address_b[3] => ram_block2a11.PORTBADDR3
address_b[3] => ram_block2a12.PORTBADDR3
address_b[3] => ram_block2a13.PORTBADDR3
address_b[3] => ram_block2a14.PORTBADDR3
address_b[3] => ram_block2a15.PORTBADDR3
address_b[3] => ram_block2a16.PORTBADDR3
address_b[3] => ram_block2a17.PORTBADDR3
address_b[4] => ram_block2a0.PORTBADDR4
address_b[4] => ram_block2a1.PORTBADDR4
address_b[4] => ram_block2a2.PORTBADDR4
address_b[4] => ram_block2a3.PORTBADDR4
address_b[4] => ram_block2a4.PORTBADDR4
address_b[4] => ram_block2a5.PORTBADDR4
address_b[4] => ram_block2a6.PORTBADDR4
address_b[4] => ram_block2a7.PORTBADDR4
address_b[4] => ram_block2a8.PORTBADDR4
address_b[4] => ram_block2a9.PORTBADDR4
address_b[4] => ram_block2a10.PORTBADDR4
address_b[4] => ram_block2a11.PORTBADDR4
address_b[4] => ram_block2a12.PORTBADDR4
address_b[4] => ram_block2a13.PORTBADDR4
address_b[4] => ram_block2a14.PORTBADDR4
address_b[4] => ram_block2a15.PORTBADDR4
address_b[4] => ram_block2a16.PORTBADDR4
address_b[4] => ram_block2a17.PORTBADDR4
address_b[5] => ram_block2a0.PORTBADDR5
address_b[5] => ram_block2a1.PORTBADDR5
address_b[5] => ram_block2a2.PORTBADDR5
address_b[5] => ram_block2a3.PORTBADDR5
address_b[5] => ram_block2a4.PORTBADDR5
address_b[5] => ram_block2a5.PORTBADDR5
address_b[5] => ram_block2a6.PORTBADDR5
address_b[5] => ram_block2a7.PORTBADDR5
address_b[5] => ram_block2a8.PORTBADDR5
address_b[5] => ram_block2a9.PORTBADDR5
address_b[5] => ram_block2a10.PORTBADDR5
address_b[5] => ram_block2a11.PORTBADDR5
address_b[5] => ram_block2a12.PORTBADDR5
address_b[5] => ram_block2a13.PORTBADDR5
address_b[5] => ram_block2a14.PORTBADDR5
address_b[5] => ram_block2a15.PORTBADDR5
address_b[5] => ram_block2a16.PORTBADDR5
address_b[5] => ram_block2a17.PORTBADDR5
clock0 => ram_block2a0.CLK0
clock0 => ram_block2a1.CLK0
clock0 => ram_block2a2.CLK0
clock0 => ram_block2a3.CLK0
clock0 => ram_block2a4.CLK0
clock0 => ram_block2a5.CLK0
clock0 => ram_block2a6.CLK0
clock0 => ram_block2a7.CLK0
clock0 => ram_block2a8.CLK0
clock0 => ram_block2a9.CLK0
clock0 => ram_block2a10.CLK0
clock0 => ram_block2a11.CLK0
clock0 => ram_block2a12.CLK0
clock0 => ram_block2a13.CLK0
clock0 => ram_block2a14.CLK0
clock0 => ram_block2a15.CLK0
clock0 => ram_block2a16.CLK0
clock0 => ram_block2a17.CLK0
clock1 => ram_block2a0.CLK1
clock1 => ram_block2a1.CLK1
clock1 => ram_block2a2.CLK1
clock1 => ram_block2a3.CLK1
clock1 => ram_block2a4.CLK1
clock1 => ram_block2a5.CLK1
clock1 => ram_block2a6.CLK1
clock1 => ram_block2a7.CLK1
clock1 => ram_block2a8.CLK1
clock1 => ram_block2a9.CLK1
clock1 => ram_block2a10.CLK1
clock1 => ram_block2a11.CLK1
clock1 => ram_block2a12.CLK1
clock1 => ram_block2a13.CLK1
clock1 => ram_block2a14.CLK1
clock1 => ram_block2a15.CLK1
clock1 => ram_block2a16.CLK1
clock1 => ram_block2a17.CLK1
clocken1 => ram_block2a0.ENA1
clocken1 => ram_block2a1.ENA1
clocken1 => ram_block2a2.ENA1
clocken1 => ram_block2a3.ENA1
clocken1 => ram_block2a4.ENA1
clocken1 => ram_block2a5.ENA1
clocken1 => ram_block2a6.ENA1
clocken1 => ram_block2a7.ENA1
clocken1 => ram_block2a8.ENA1
clocken1 => ram_block2a9.ENA1
clocken1 => ram_block2a10.ENA1
clocken1 => ram_block2a11.ENA1
clocken1 => ram_block2a12.ENA1
clocken1 => ram_block2a13.ENA1
clocken1 => ram_block2a14.ENA1
clocken1 => ram_block2a15.ENA1
clocken1 => ram_block2a16.ENA1
clocken1 => ram_block2a17.ENA1
data_a[0] => ram_block2a0.PORTADATAIN
data_a[1] => ram_block2a1.PORTADATAIN
data_a[2] => ram_block2a2.PORTADATAIN
data_a[3] => ram_block2a3.PORTADATAIN
data_a[4] => ram_block2a4.PORTADATAIN
data_a[5] => ram_block2a5.PORTADATAIN
data_a[6] => ram_block2a6.PORTADATAIN
data_a[7] => ram_block2a7.PORTADATAIN
data_a[8] => ram_block2a8.PORTADATAIN
data_a[9] => ram_block2a9.PORTADATAIN
data_a[10] => ram_block2a10.PORTADATAIN
data_a[11] => ram_block2a11.PORTADATAIN
data_a[12] => ram_block2a12.PORTADATAIN
data_a[13] => ram_block2a13.PORTADATAIN
data_a[14] => ram_block2a14.PORTADATAIN
data_a[15] => ram_block2a15.PORTADATAIN
data_a[16] => ram_block2a16.PORTADATAIN
data_a[17] => ram_block2a17.PORTADATAIN
q_b[0] <= ram_block2a0.PORTBDATAOUT
q_b[1] <= ram_block2a1.PORTBDATAOUT
q_b[2] <= ram_block2a2.PORTBDATAOUT
q_b[3] <= ram_block2a3.PORTBDATAOUT
q_b[4] <= ram_block2a4.PORTBDATAOUT
q_b[5] <= ram_block2a5.PORTBDATAOUT
q_b[6] <= ram_block2a6.PORTBDATAOUT
q_b[7] <= ram_block2a7.PORTBDATAOUT
q_b[8] <= ram_block2a8.PORTBDATAOUT
q_b[9] <= ram_block2a9.PORTBDATAOUT
q_b[10] <= ram_block2a10.PORTBDATAOUT
q_b[11] <= ram_block2a11.PORTBDATAOUT
q_b[12] <= ram_block2a12.PORTBDATAOUT
q_b[13] <= ram_block2a13.PORTBDATAOUT
q_b[14] <= ram_block2a14.PORTBDATAOUT
q_b[15] <= ram_block2a15.PORTBDATAOUT
q_b[16] <= ram_block2a16.PORTBDATAOUT
q_b[17] <= ram_block2a17.PORTBDATAOUT
wren_a => ram_block2a0.PORTAWE
wren_a => ram_block2a0.ENA0
wren_a => ram_block2a1.PORTAWE
wren_a => ram_block2a1.ENA0
wren_a => ram_block2a2.PORTAWE
wren_a => ram_block2a2.ENA0
wren_a => ram_block2a3.PORTAWE
wren_a => ram_block2a3.ENA0
wren_a => ram_block2a4.PORTAWE
wren_a => ram_block2a4.ENA0
wren_a => ram_block2a5.PORTAWE
wren_a => ram_block2a5.ENA0
wren_a => ram_block2a6.PORTAWE
wren_a => ram_block2a6.ENA0
wren_a => ram_block2a7.PORTAWE
wren_a => ram_block2a7.ENA0
wren_a => ram_block2a8.PORTAWE
wren_a => ram_block2a8.ENA0
wren_a => ram_block2a9.PORTAWE
wren_a => ram_block2a9.ENA0
wren_a => ram_block2a10.PORTAWE
wren_a => ram_block2a10.ENA0
wren_a => ram_block2a11.PORTAWE
wren_a => ram_block2a11.ENA0
wren_a => ram_block2a12.PORTAWE
wren_a => ram_block2a12.ENA0
wren_a => ram_block2a13.PORTAWE
wren_a => ram_block2a13.ENA0
wren_a => ram_block2a14.PORTAWE
wren_a => ram_block2a14.ENA0
wren_a => ram_block2a15.PORTAWE
wren_a => ram_block2a15.ENA0
wren_a => ram_block2a16.PORTAWE
wren_a => ram_block2a16.ENA0
wren_a => ram_block2a17.PORTAWE
wren_a => ram_block2a17.ENA0


|block|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|cntr_fjb:rd_ptr_count
aclr => counter_reg_bit3a[5].ACLR
aclr => counter_reg_bit3a[4].ACLR
aclr => counter_reg_bit3a[3].ACLR
aclr => counter_reg_bit3a[2].ACLR
aclr => counter_reg_bit3a[1].ACLR
aclr => counter_reg_bit3a[0].ACLR
clock => counter_reg_bit3a[5].CLK
clock => counter_reg_bit3a[4].CLK
clock => counter_reg_bit3a[3].CLK
clock => counter_reg_bit3a[2].CLK
clock => counter_reg_bit3a[1].CLK
clock => counter_reg_bit3a[0].CLK
q[0] <= counter_reg_bit3a[0].REGOUT
q[1] <= counter_reg_bit3a[1].REGOUT
q[2] <= counter_reg_bit3a[2].REGOUT
q[3] <= counter_reg_bit3a[3].REGOUT
q[4] <= counter_reg_bit3a[4].REGOUT
q[5] <= counter_reg_bit3a[5].REGOUT


|block|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|cntr_fjb:wr_ptr
aclr => counter_reg_bit3a[5].ACLR
aclr => counter_reg_bit3a[4].ACLR
aclr => counter_reg_bit3a[3].ACLR
aclr => counter_reg_bit3a[2].ACLR
aclr => counter_reg_bit3a[1].ACLR
aclr => counter_reg_bit3a[0].ACLR
clock => counter_reg_bit3a[5].CLK
clock => counter_reg_bit3a[4].CLK
clock => counter_reg_bit3a[3].CLK
clock => counter_reg_bit3a[2].CLK
clock => counter_reg_bit3a[1].CLK
clock => counter_reg_bit3a[0].CLK
q[0] <= counter_reg_bit3a[0].REGOUT
q[1] <= counter_reg_bit3a[1].REGOUT
q[2] <= counter_reg_bit3a[2].REGOUT
q[3] <= counter_reg_bit3a[3].REGOUT
q[4] <= counter_reg_bit3a[4].REGOUT
q[5] <= counter_reg_bit3a[5].REGOUT


|block|p2s:inst13
clk => count[6].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => cnt.CLK
clk => data_temp[1][17].CLK
clk => data_temp[1][16].CLK
clk => data_temp[1][15].CLK
clk => data_temp[1][14].CLK
clk => data_temp[1][13].CLK
clk => data_temp[1][12].CLK
clk => data_temp[1][11].CLK
clk => data_temp[1][10].CLK
clk => data_temp[1][9].CLK
clk => data_temp[1][8].CLK
clk => data_temp[1][7].CLK
clk => data_temp[1][6].CLK
clk => data_temp[1][5].CLK
clk => data_temp[1][4].CLK
clk => data_temp[1][3].CLK
clk => data_temp[1][2].CLK
clk => data_temp[1][1].CLK
clk => data_temp[1][0].CLK
clk => data_temp[0][17].CLK
clk => data_temp[0][16].CLK
clk => data_temp[0][15].CLK
clk => data_temp[0][14].CLK
clk => data_temp[0][13].CLK
clk => data_temp[0][12].CLK
clk => data_temp[0][11].CLK
clk => data_temp[0][10].CLK
clk => data_temp[0][9].CLK
clk => data_temp[0][8].CLK
clk => data_temp[0][7].CLK
clk => data_temp[0][6].CLK
clk => data_temp[0][5].CLK
clk => data_temp[0][4].CLK
clk => data_temp[0][3].CLK
clk => data_temp[0][2].CLK
clk => data_temp[0][1].CLK
clk => data_temp[0][0].CLK
reset => source_valid~0.IN0
reset => count[6].ACLR
reset => count[5].ACLR
reset => count[4].ACLR
reset => count[3].ACLR
reset => count[2].ACLR
reset => count[1].ACLR
reset => count[0].ACLR
reset => cnt.ACLR
reset => data_temp[1][17].ACLR
reset => data_temp[1][16].ACLR
reset => data_temp[1][15].ACLR
reset => data_temp[1][14].ACLR
reset => data_temp[1][13].ACLR
reset => data_temp[1][12].ACLR
reset => data_temp[1][11].ACLR
reset => data_temp[1][10].ACLR
reset => data_temp[1][9].ACLR
reset => data_temp[1][8].ACLR
reset => data_temp[1][7].ACLR
reset => data_temp[1][6].ACLR
reset => data_temp[1][5].ACLR
reset => data_temp[1][4].ACLR
reset => data_temp[1][3].ACLR
reset => data_temp[1][2].ACLR
reset => data_temp[1][1].ACLR
reset => data_temp[1][0].ACLR
reset => data_temp[0][17].ACLR
reset => data_temp[0][16].ACLR
reset => data_temp[0][15].ACLR
reset => data_temp[0][14].ACLR
reset => data_temp[0][13].ACLR
reset => data_temp[0][12].ACLR
reset => data_temp[0][11].ACLR
reset => data_temp[0][10].ACLR
reset => data_temp[0][9].ACLR
reset => data_temp[0][8].ACLR
reset => data_temp[0][7].ACLR
reset => data_temp[0][6].ACLR
reset => data_temp[0][5].ACLR
reset => data_temp[0][4].ACLR
reset => data_temp[0][3].ACLR
reset => data_temp[0][2].ACLR
reset => data_temp[0][1].ACLR
reset => data_temp[0][0].ACLR
sink_valid => data_temp~35.OUTPUTSELECT
sink_valid => data_temp~34.OUTPUTSELECT
sink_valid => data_temp~33.OUTPUTSELECT
sink_valid => data_temp~32.OUTPUTSELECT
sink_valid => data_temp~31.OUTPUTSELECT
sink_valid => data_temp~30.OUTPUTSELECT
sink_valid => data_temp~29.OUTPUTSELECT
sink_valid => data_temp~28.OUTPUTSELECT
sink_valid => data_temp~27.OUTPUTSELECT
sink_valid => data_temp~26.OUTPUTSELECT
sink_valid => data_temp~25.OUTPUTSELECT
sink_valid => data_temp~24.OUTPUTSELECT
sink_valid => data_temp~23.OUTPUTSELECT
sink_valid => data_temp~22.OUTPUTSELECT
sink_valid => data_temp~21.OUTPUTSELECT
sink_valid => data_temp~20.OUTPUTSELECT
sink_valid => data_temp~19.OUTPUTSELECT
sink_valid => data_temp~18.OUTPUTSELECT
sink_valid => data_temp~17.OUTPUTSELECT
sink_valid => data_temp~16.OUTPUTSELECT
sink_valid => data_temp~15.OUTPUTSELECT
sink_valid => data_temp~14.OUTPUTSELECT
sink_valid => data_temp~13.OUTPUTSELECT
sink_valid => data_temp~12.OUTPUTSELECT
sink_valid => data_temp~11.OUTPUTSELECT
sink_valid => data_temp~10.OUTPUTSELECT
sink_valid => data_temp~9.OUTPUTSELECT
sink_valid => data_temp~8.OUTPUTSELECT
sink_valid => data_temp~7.OUTPUTSELECT
sink_valid => data_temp~6.OUTPUTSELECT
sink_valid => data_temp~5.OUTPUTSELECT
sink_valid => data_temp~4.OUTPUTSELECT
sink_valid => data_temp~3.OUTPUTSELECT
sink_valid => data_temp~2.OUTPUTSELECT
sink_valid => data_temp~1.OUTPUTSELECT
sink_valid => data_temp~0.OUTPUTSELECT
sink_valid => count~13.OUTPUTSELECT
sink_valid => count~12.OUTPUTSELECT
sink_valid => count~11.OUTPUTSELECT
sink_valid => count~10.OUTPUTSELECT
sink_valid => count~9.OUTPUTSELECT
sink_valid => count~8.OUTPUTSELECT
sink_valid => count~7.OUTPUTSELECT
sink_valid => cnt~0.OUTPUTSELECT
data_in0[0] => data_temp~35.DATAB
data_in0[1] => data_temp~34.DATAB
data_in0[2] => data_temp~33.DATAB
data_in0[3] => data_temp~32.DATAB
data_in0[4] => data_temp~31.DATAB
data_in0[5] => data_temp~30.DATAB
data_in0[6] => data_temp~29.DATAB
data_in0[7] => data_temp~28.DATAB
data_in0[8] => data_temp~27.DATAB
data_in0[9] => data_temp~26.DATAB
data_in0[10] => data_temp~25.DATAB
data_in0[11] => data_temp~24.DATAB
data_in0[12] => data_temp~23.DATAB
data_in0[13] => data_temp~22.DATAB
data_in0[14] => data_temp~21.DATAB
data_in0[15] => data_temp~20.DATAB
data_in0[16] => data_temp~19.DATAB
data_in0[17] => data_temp~18.DATAB
data_in1[0] => data_temp~17.DATAB
data_in1[1] => data_temp~16.DATAB
data_in1[2] => data_temp~15.DATAB
data_in1[3] => data_temp~14.DATAB
data_in1[4] => data_temp~13.DATAB
data_in1[5] => data_temp~12.DATAB
data_in1[6] => data_temp~11.DATAB
data_in1[7] => data_temp~10.DATAB
data_in1[8] => data_temp~9.DATAB
data_in1[9] => data_temp~8.DATAB
data_in1[10] => data_temp~7.DATAB
data_in1[11] => data_temp~6.DATAB
data_in1[12] => data_temp~5.DATAB
data_in1[13] => data_temp~4.DATAB
data_in1[14] => data_temp~3.DATAB
data_in1[15] => data_temp~2.DATAB
data_in1[16] => data_temp~1.DATAB
data_in1[17] => data_temp~0.DATAB
data_out[0] <= data_out~37.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out~36.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out~35.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out~34.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out~33.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out~32.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out~31.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out~30.DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= data_out~29.DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= data_out~28.DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= data_out~27.DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= data_out~26.DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= data_out~25.DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= data_out~24.DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= data_out~23.DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= data_out~22.DB_MAX_OUTPUT_PORT_TYPE
data_out[16] <= data_out~21.DB_MAX_OUTPUT_PORT_TYPE
data_out[17] <= data_out~20.DB_MAX_OUTPUT_PORT_TYPE
source_valid <= source_valid~0.DB_MAX_OUTPUT_PORT_TYPE


|block|makeup_sign:inst32
data_in[0] => data_out[0].DATAIN
data_in[1] => data_out[1].DATAIN
data_in[2] => data_out[2].DATAIN
data_in[3] => data_out[3].DATAIN
data_in[4] => data_out[4].DATAIN
data_in[5] => data_out[5].DATAIN
data_in[6] => data_out[6].DATAIN
data_in[7] => data_out[7].DATAIN
data_in[8] => data_out[8].DATAIN
data_in[9] => data_out[9].DATAIN
data_in[10] => data_out[10].DATAIN
data_in[11] => data_out[11].DATAIN
data_in[12] => data_out[12].DATAIN
data_in[13] => data_out[13].DATAIN
data_in[14] => data_out[14].DATAIN
data_in[15] => data_out[15].DATAIN
data_in[15] => data_out[17].DATAIN
data_in[15] => data_out[16].DATAIN
data_out[0] <= data_in[0].DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_in[1].DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_in[2].DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_in[3].DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_in[4].DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_in[5].DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_in[6].DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_in[7].DB_MAX_OUTPUT_PORT_TYPE
data_out[8] <= data_in[8].DB_MAX_OUTPUT_PORT_TYPE
data_out[9] <= data_in[9].DB_MAX_OUTPUT_PORT_TYPE
data_out[10] <= data_in[10].DB_MAX_OUTPUT_PORT_TYPE
data_out[11] <= data_in[11].DB_MAX_OUTPUT_PORT_TYPE
data_out[12] <= data_in[12].DB_MAX_OUTPUT_PORT_TYPE
data_out[13] <= data_in[13].DB_MAX_OUTPUT_PORT_TYPE
data_out[14] <= data_in[14].DB_MAX_OUTPUT_PORT_TYPE
data_out[15] <= data_in[15].DB_MAX_OUTPUT_PORT_TYPE
data_out[16] <= data_in[15].DB_MAX_OUTPUT_PORT_TYPE
data_out[17] <= data_in[15].DB_MAX_OUTPUT_PORT_TYPE


|block|lpm_rom2:inst19
aclr => aclr~0.IN1
address[0] => address[0]~5.IN1
address[1] => address[1]~4.IN1
address[2] => address[2]~3.IN1
address[3] => address[3]~2.IN1
address[4] => address[4]~1.IN1
address[5] => address[5]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
q[8] <= altsyncram:altsyncram_component.q_a
q[9] <= altsyncram:altsyncram_component.q_a
q[10] <= altsyncram:altsyncram_component.q_a
q[11] <= altsyncram:altsyncram_component.q_a
q[12] <= altsyncram:altsyncram_component.q_a
q[13] <= altsyncram:altsyncram_component.q_a
q[14] <= altsyncram:altsyncram_component.q_a
q[15] <= altsyncram:altsyncram_component.q_a


|block|lpm_rom2:inst19|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_a[13] => ~NO_FANOUT~
data_a[14] => ~NO_FANOUT~
data_a[15] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_kfa1:auto_generated.address_a[0]
address_a[1] => altsyncram_kfa1:auto_generated.address_a[1]
address_a[2] => altsyncram_kfa1:auto_generated.address_a[2]
address_a[3] => altsyncram_kfa1:auto_generated.address_a[3]
address_a[4] => altsyncram_kfa1:auto_generated.address_a[4]
address_a[5] => altsyncram_kfa1:auto_generated.address_a[5]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_kfa1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => altsyncram_kfa1:auto_generated.aclr0
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_kfa1:auto_generated.q_a[0]
q_a[1] <= altsyncram_kfa1:auto_generated.q_a[1]
q_a[2] <= altsyncram_kfa1:auto_generated.q_a[2]
q_a[3] <= altsyncram_kfa1:auto_generated.q_a[3]
q_a[4] <= altsyncram_kfa1:auto_generated.q_a[4]
q_a[5] <= altsyncram_kfa1:auto_generated.q_a[5]
q_a[6] <= altsyncram_kfa1:auto_generated.q_a[6]
q_a[7] <= altsyncram_kfa1:auto_generated.q_a[7]
q_a[8] <= altsyncram_kfa1:auto_generated.q_a[8]
q_a[9] <= altsyncram_kfa1:auto_generated.q_a[9]
q_a[10] <= altsyncram_kfa1:auto_generated.q_a[10]
q_a[11] <= altsyncram_kfa1:auto_generated.q_a[11]
q_a[12] <= altsyncram_kfa1:auto_generated.q_a[12]
q_a[13] <= altsyncram_kfa1:auto_generated.q_a[13]
q_a[14] <= altsyncram_kfa1:auto_generated.q_a[14]
q_a[15] <= altsyncram_kfa1:auto_generated.q_a[15]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|block|lpm_rom2:inst19|altsyncram:altsyncram_component|altsyncram_kfa1:auto_generated
aclr0 => ram_block1a0.CLR0
aclr0 => ram_block1a1.CLR0
aclr0 => ram_block1a2.CLR0
aclr0 => ram_block1a3.CLR0
aclr0 => ram_block1a4.CLR0
aclr0 => ram_block1a5.CLR0
aclr0 => ram_block1a6.CLR0
aclr0 => ram_block1a7.CLR0
aclr0 => ram_block1a8.CLR0
aclr0 => ram_block1a9.CLR0
aclr0 => ram_block1a10.CLR0
aclr0 => ram_block1a11.CLR0
aclr0 => ram_block1a12.CLR0
aclr0 => ram_block1a13.CLR0
aclr0 => ram_block1a14.CLR0
aclr0 => ram_block1a15.CLR0
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT
q_a[10] <= ram_block1a10.PORTADATAOUT
q_a[11] <= ram_block1a11.PORTADATAOUT
q_a[12] <= ram_block1a12.PORTADATAOUT
q_a[13] <= ram_block1a13.PORTADATAOUT
q_a[14] <= ram_block1a14.PORTADATAOUT
q_a[15] <= ram_block1a15.PORTADATAOUT


|block|lpm_counter0:inst4
clock => clock~0.IN1
q[0] <= lpm_counter:lpm_counter_component.q
q[1] <= lpm_counter:lpm_counter_component.q
q[2] <= lpm_counter:lpm_counter_component.q
q[3] <= lpm_counter:lpm_counter_component.q
q[4] <= lpm_counter:lpm_counter_component.q
q[5] <= lpm_counter:lpm_counter_component.q


|block|lpm_counter0:inst4|lpm_counter:lpm_counter_component
clock => cntr_qkh:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_qkh:auto_generated.q[0]
q[1] <= cntr_qkh:auto_generated.q[1]
q[2] <= cntr_qkh:auto_generated.q[2]
q[3] <= cntr_qkh:auto_generated.q[3]
q[4] <= cntr_qkh:auto_generated.q[4]
q[5] <= cntr_qkh:auto_generated.q[5]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|block|lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qkh:auto_generated
clock => counter_reg_bit1a[5].CLK
clock => counter_reg_bit1a[4].CLK
clock => counter_reg_bit1a[3].CLK
clock => counter_reg_bit1a[2].CLK
clock => counter_reg_bit1a[1].CLK
clock => counter_reg_bit1a[0].CLK
q[0] <= counter_reg_bit1a[0].REGOUT
q[1] <= counter_reg_bit1a[1].REGOUT
q[2] <= counter_reg_bit1a[2].REGOUT
q[3] <= counter_reg_bit1a[3].REGOUT
q[4] <= counter_reg_bit1a[4].REGOUT
q[5] <= counter_reg_bit1a[5].REGOUT


|block|block_new:inst45
clk => cnt[7].CLK
clk => cnt[6].CLK
clk => cnt[5].CLK
clk => cnt[4].CLK
clk => cnt[3].CLK
clk => cnt[2].CLK
clk => cnt[1].CLK
clk => cnt[0].CLK
clk => final_state[1]~reg0.CLK
clk => final_state[0]~reg0.CLK
clk => current_state~0.IN1
reset => cnt[7].ACLR
reset => cnt[6].ACLR
reset => cnt[5].ACLR
reset => cnt[4].ACLR
reset => cnt[3].ACLR
reset => cnt[2].ACLR
reset => cnt[1].ACLR
reset => cnt[0].ACLR
reset => final_state[1]~reg0.ACLR
reset => final_state[0]~reg0.ACLR
reset => current_state~1.IN1
ar[0] => ~NO_FANOUT~
ar[1] => ~NO_FANOUT~
ar[2] => ~NO_FANOUT~
ar[3] => ~NO_FANOUT~
ar[4] => ~NO_FANOUT~
ar[5] => ~NO_FANOUT~
ar[6] => ~NO_FANOUT~
ar[7] => ~NO_FANOUT~
ar[8] => ~NO_FANOUT~
ar[9] => ~NO_FANOUT~
ar[10] => ~NO_FANOUT~
ar[11] => ~NO_FANOUT~
ar[12] => ~NO_FANOUT~
ar[13] => ~NO_FANOUT~
ar[14] => ~NO_FANOUT~
ar[15] => head0[0].DATAA
ar[15] => head0[0].DATAB
ar[16] => head0[1].DATAA
ar[16] => head0[1].DATAB
ar[17] => head0[0].OUTPUTSELECT
ar[17] => head0[1].OUTPUTSELECT
ai[0] => ~NO_FANOUT~
ai[1] => ~NO_FANOUT~
ai[2] => ~NO_FANOUT~
ai[3] => ~NO_FANOUT~
ai[4] => ~NO_FANOUT~
ai[5] => ~NO_FANOUT~
ai[6] => ~NO_FANOUT~
ai[7] => ~NO_FANOUT~
ai[8] => ~NO_FANOUT~
ai[9] => ~NO_FANOUT~
ai[10] => ~NO_FANOUT~
ai[11] => ~NO_FANOUT~
ai[12] => ~NO_FANOUT~
ai[13] => ~NO_FANOUT~
ai[14] => ~NO_FANOUT~
ai[15] => head1[0].DATAA
ai[15] => head1[0].DATAB
ai[16] => head1[1].DATAA
ai[16] => head1[1].DATAB
ai[17] => head1[0].OUTPUTSELECT
ai[17] => head1[1].OUTPUTSELECT
br[0] => ~NO_FANOUT~
br[1] => ~NO_FANOUT~
br[2] => ~NO_FANOUT~
br[3] => ~NO_FANOUT~
br[4] => ~NO_FANOUT~
br[5] => ~NO_FANOUT~
br[6] => ~NO_FANOUT~
br[7] => ~NO_FANOUT~
br[8] => ~NO_FANOUT~
br[9] => ~NO_FANOUT~
br[10] => ~NO_FANOUT~
br[11] => ~NO_FANOUT~
br[12] => ~NO_FANOUT~
br[13] => ~NO_FANOUT~
br[14] => ~NO_FANOUT~
br[15] => head2[0].DATAA
br[15] => head2[0].DATAB
br[16] => head2[1].DATAA
br[16] => head2[1].DATAB
br[17] => head2[0].OUTPUTSELECT
br[17] => head2[1].OUTPUTSELECT
bi[0] => ~NO_FANOUT~
bi[1] => ~NO_FANOUT~
bi[2] => ~NO_FANOUT~
bi[3] => ~NO_FANOUT~
bi[4] => ~NO_FANOUT~
bi[5] => ~NO_FANOUT~
bi[6] => ~NO_FANOUT~
bi[7] => ~NO_FANOUT~
bi[8] => ~NO_FANOUT~
bi[9] => ~NO_FANOUT~
bi[10] => ~NO_FANOUT~
bi[11] => ~NO_FANOUT~
bi[12] => ~NO_FANOUT~
bi[13] => ~NO_FANOUT~
bi[14] => ~NO_FANOUT~
bi[15] => head3[0].DATAA
bi[15] => head3[0].DATAB
bi[16] => head3[1].DATAA
bi[16] => head3[1].DATAB
bi[17] => head3[0].OUTPUTSELECT
bi[17] => head3[1].OUTPUTSELECT
sink_valid => Selector2.IN1
sink_valid => source_valid~0.IN0
sink_valid => cnt~15.OUTPUTSELECT
sink_valid => cnt~14.OUTPUTSELECT
sink_valid => cnt~13.OUTPUTSELECT
sink_valid => cnt~12.OUTPUTSELECT
sink_valid => cnt~11.OUTPUTSELECT
sink_valid => cnt~10.OUTPUTSELECT
sink_valid => cnt~9.OUTPUTSELECT
sink_valid => cnt~8.OUTPUTSELECT
sink_valid => next_state~6.OUTPUTSELECT
sink_valid => next_state~4.OUTPUTSELECT
sink_valid => next_state~3.OUTPUTSELECT
sink_valid => next_state~2.OUTPUTSELECT
sink_valid => Selector0.IN0
sink_valid => final_state[1]~reg0.ENA
sink_valid => final_state[0]~reg0.ENA
state[0] <= current_state.s1.DB_MAX_OUTPUT_PORT_TYPE
state[1] <= current_state.s2.DB_MAX_OUTPUT_PORT_TYPE
final_state[0] <= final_state[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
final_state[1] <= final_state[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
source_valid <= source_valid~0.DB_MAX_OUTPUT_PORT_TYPE


