library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
entity reset_ctrl is 
generic(const:integer:=2);
port(  
	clk : in std_logic; 
	clk_c : out std_logic 
	); 
end reset_ctrl; 
architecture rtl of  reset_ctrl is 
begin
process(clk)
variable num:integer range 100 downto 0:=0;
	begin
	if clk'event and clk='1' then
		if num<=const then
			num:=num+1;
			clk_c<='0';
		else
			clk_c<='1';
		end if;
	end if;
end process;
end rtl;