{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 06 17:12:35 2010 " "Info: Processing started: Sun Jun 06 17:12:35 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off FFT -c FFT " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off FFT -c FFT" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "FFT EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"FFT\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "high junction temperature 85 " "Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "low junction temperature 0 " "Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "3 0 " "Info: The Fitter has identified 3 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "1752 Top " "Info: Previous placement does not exist for 1752 of 1752 atoms in partition Top" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0} { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "1331 sld_signaltap:auto_signaltap_0 " "Info: Previous placement does not exist for 1331 of 1331 atoms in partition sld_signaltap:auto_signaltap_0" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0} { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "176 sld_hub:sld_hub_inst " "Info: Previous placement does not exist for 176 of 176 atoms in partition sld_hub:sld_hub_inst" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0}  } {  } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" {  } { { "e:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/altera/72/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" {  } { { "e:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/altera/72/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 108 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 108" {  } { { "e:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/altera/72/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN 23 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node clk (placed in PIN 23 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "altera_auto_signaltap_0_clk_signaltap_lcell " "Info: Destination node altera_auto_signaltap_0_clk_signaltap_lcell" {  } { { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "altera_auto_signaltap_0_clk_signaltap_lcell" } } } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_auto_signaltap_0_clk_signaltap_lcell } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_auto_signaltap_0_clk_signaltap_lcell } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/altera/72/quartus/bin/pin_planner.ppl" { clk } } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "block.bdf" "" { Schematic "C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf" { { 328 80 248 344 "clk" "" } { 304 864 936 320 "clk" "" } { 256 1448 1488 272 "clk" "" } { 80 1752 1808 96 "clk" "" } { 88 1280 1352 104 "clk" "" } { -80 1272 1344 -64 "clk" "" } { 624 992 1040 640 "clk" "" } { 736 992 1040 752 "clk" "" } { 448 880 936 464 "clk" "" } { 320 248 368 336 "clk" "" } { 608 1472 1496 624 "clk" "" } { 720 1472 1504 736 "clk" "" } { 720 1224 1256 736 "clk" "" } { 608 1216 1248 624 "clk" "" } { 448 1784 1840 464 "clk" "" } { 224 1808 1848 240 "clk" "" } { 368 -184 -120 384 "clk" "" } { 656 -312 -232 672 "clk" "" } { 352 -408 -344 368 "clk" "" } { 720 0 96 736 "clk" "" } } } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Info: Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset_ctrl:inst5\|clk_c  " "Info: Automatically promoted node reset_ctrl:inst5\|clk_c " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "T_control:inst46\|sink_ready~22 " "Info: Destination node T_control:inst46\|sink_ready~22" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 8 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { T_control:inst46|sink_ready~22 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { T_control:inst46|sink_ready~22 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ctrl_fft:inst3\|Selector0~42 " "Info: Destination node ctrl_fft:inst3\|Selector0~42" {  } { { "ctrl_fft.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd" 23 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ctrl_fft:inst3|Selector0~42 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ctrl_fft:inst3|Selector0~42 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ctrl_fft:inst3\|current_state.idle~77 " "Info: Destination node ctrl_fft:inst3\|current_state.idle~77" {  } { { "ctrl_fft.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd" 17 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ctrl_fft:inst3|current_state.idle~77 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ctrl_fft:inst3|current_state.idle~77 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|valid_wreq~35 " "Info: Destination node lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|valid_wreq~35" {  } { { "db/a_dpfifo_e141.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/a_dpfifo_e141.tdf" 48 2 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|valid_wreq~35 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|valid_wreq~35 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|valid_rreq " "Info: Destination node lpm_fifo0:inst\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|valid_rreq" {  } { { "db/a_dpfifo_e141.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/a_dpfifo_e141.tdf" 47 2 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|valid_rreq } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|valid_rreq } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "s2p:inst6\|source_valid " "Info: Destination node s2p:inst6\|source_valid" {  } { { "s2p.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/s2p.v" 5 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { s2p:inst6|source_valid } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { s2p:inst6|source_valid } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|valid_wreq~33 " "Info: Destination node lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|valid_wreq~33" {  } { { "db/a_dpfifo_e141.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/a_dpfifo_e141.tdf" 48 2 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|valid_wreq~33 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|valid_wreq~33 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|valid_rreq " "Info: Destination node lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|valid_rreq" {  } { { "db/a_dpfifo_e141.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/a_dpfifo_e141.tdf" 47 2 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|valid_rreq } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|valid_rreq } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|a_fefifo_b6f:fifo_state\|b_full~132 " "Info: Destination node lpm_fifo0:inst24\|scfifo:scfifo_component\|scfifo_7r31:auto_generated\|a_dpfifo_e141:dpfifo\|a_fefifo_b6f:fifo_state\|b_full~132" {  } { { "db/a_fefifo_b6f.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/a_fefifo_b6f.tdf" 36 2 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|a_fefifo_b6f:fifo_state|b_full~132 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|a_fefifo_b6f:fifo_state|b_full~132 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "T_control:inst46\|rdreq_fifo~58 " "Info: Destination node T_control:inst46\|rdreq_fifo~58" {  } { { "T_control.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v" 8 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { T_control:inst46|rdreq_fifo~58 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { T_control:inst46|rdreq_fifo~58 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" {  } {  } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "reset_ctrl.vhd" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/reset_ctrl.vhd" 8 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset_ctrl:inst5|clk_c } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset_ctrl:inst5|clk_c } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|reset_all  " "Info: Automatically promoted node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|reset_all " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset " "Info: Destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 385 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 737 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|reset_all } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|reset_all } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|CLR_SIGNAL  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|CLR_SIGNAL " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|CLR_SIGNAL~_wirecell " "Info: Destination node sld_hub:sld_hub_inst\|CLR_SIGNAL~_wirecell" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL~_wirecell } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL~_wirecell } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } } { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|CLR_SIGNAL" } } } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~442 " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~442" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 1148 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~442 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~442 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5 " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 1148 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]~_wirecell " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]~_wirecell" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 1163 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]~_wirecell } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]~_wirecell } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 1163 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset  " "Info: Automatically promoted node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 385 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|offload_shift_ena  " "Info: Automatically promoted node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|offload_shift_ena " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|ram_shift_load " "Info: Destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|ram_shift_load" {  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 370 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|ram_shift_load } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|ram_shift_load } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 364 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|offload_shift_ena } "NODE_NAME" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|offload_shift_ena } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:02 " "Info: Finished register packing: elapsed time is 00:00:02" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "36 Embedded multiplier block " "Extra Info: Packed 36 registers into blocks of type Embedded multiplier block" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "99 Embedded multiplier output " "Extra Info: Packed 99 registers into blocks of type Embedded multiplier output" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "1 " "Extra Info: Created 1 register duplicates" {  } {  } 1 0 "Created %1!d! register duplicates" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Warning: Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "sin\[16\] " "Warning: Ignored I/O standard assignment to node \"sin\[16\]\"" {  } { { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sin\[16\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "sin\[17\] " "Warning: Ignored I/O standard assignment to node \"sin\[17\]\"" {  } { { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sin\[17\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Ignored I/O standard assignments to the following nodes" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "sin\[16\] " "Warning: Node \"sin\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sin\[16\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "sin\[17\] " "Warning: Node \"sin\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "e:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sin\[17\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0}  } {  } 0 0 "Ignored locations or region assignments to the following nodes" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:09 " "Info: Fitter placement operations ending: elapsed time is 00:00:09" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.261 ns register register " "Info: Estimated most critical path is register to register delay of 8.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns butterfly:inst48\|real_a\[0\] 1 REG LAB_X16_Y11 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X16_Y11; Fanout = 4; REG Node = 'butterfly:inst48\|real_a\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { butterfly:inst48|real_a[0] } "NODE_NAME" } } { "butterfly.v" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.596 ns) 1.271 ns butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[0\]~35 2 COMB LAB_X16_Y11 2 " "Info: 2: + IC(0.675 ns) + CELL(0.596 ns) = 1.271 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[0\]~35'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.271 ns" { butterfly:inst48|real_a[0] butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[0]~35 } "NODE_NAME" } } { "db/add_sub_4qe.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_4qe.tdf" 26 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.357 ns butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[1\]~37 3 COMB LAB_X16_Y11 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.357 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[1\]~37'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[0]~35 butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[1]~37 } "NODE_NAME" } } { "db/add_sub_4qe.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_4qe.tdf" 26 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.443 ns butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[2\]~39 4 COMB LAB_X16_Y11 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.443 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[2\]~39'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[1]~37 butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[2]~39 } "NODE_NAME" } } { "db/add_sub_4qe.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_4qe.tdf" 26 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.529 ns butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[3\]~41 5 COMB LAB_X16_Y11 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.529 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[3\]~41'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[2]~39 butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[3]~41 } "NODE_NAME" } } { "db/add_sub_4qe.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_4qe.tdf" 26 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.615 ns butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[4\]~43 6 COMB LAB_X16_Y11 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.615 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[4\]~43'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[3]~41 butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[4]~43 } "NODE_NAME" } } { "db/add_sub_4qe.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_4qe.tdf" 26 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.701 ns butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[5\]~45 7 COMB LAB_X16_Y11 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.701 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[5\]~45'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[4]~43 butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[5]~45 } "NODE_NAME" } } { "db/add_sub_4qe.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_4qe.tdf" 26 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.787 ns butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[6\]~47 8 COMB LAB_X16_Y11 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.787 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[6\]~47'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[5]~45 butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[6]~47 } "NODE_NAME" } } { "db/add_sub_4qe.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_4qe.tdf" 26 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.873 ns butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[7\]~49 9 COMB LAB_X16_Y11 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 1.873 ns; Loc. = LAB_X16_Y11; Fanout = 2; COMB Node = 'butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[7\]~49'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[6]~47 butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[7]~49 } "NODE_NAME" } } { "db/add_sub_4qe.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_4qe.tdf" 26 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.107 ns) + CELL(0.506 ns) 2.486 ns butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[8\]~50 10 COMB LAB_X16_Y10 3 " "Info: 10: + IC(0.107 ns) + CELL(0.506 ns) = 2.486 ns; Loc. = LAB_X16_Y10; Fanout = 3; COMB Node = 'butterfly:inst48\|SUB_17:sub_real\|lpm_add_sub:lpm_add_sub_component\|add_sub_4qe:auto_generated\|result\[8\]~50'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.613 ns" { butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[7]~49 butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[8]~50 } "NODE_NAME" } } { "db/add_sub_4qe.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_4qe.tdf" 26 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.695 ns) + CELL(0.596 ns) 4.777 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[8\]~129 11 COMB LAB_X19_Y11 2 " "Info: 11: + IC(1.695 ns) + CELL(0.596 ns) = 4.777 ns; Loc. = LAB_X19_Y11; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[8\]~129'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.291 ns" { butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[8]~50 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[8]~129 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.107 ns) + CELL(0.086 ns) 4.970 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[9\]~131 12 COMB LAB_X19_Y10 2 " "Info: 12: + IC(0.107 ns) + CELL(0.086 ns) = 4.970 ns; Loc. = LAB_X19_Y10; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[9\]~131'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.193 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[8]~129 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[9]~131 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.056 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[10\]~133 13 COMB LAB_X19_Y10 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 5.056 ns; Loc. = LAB_X19_Y10; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[10\]~133'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[9]~131 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[10]~133 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.142 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[11\]~135 14 COMB LAB_X19_Y10 2 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 5.142 ns; Loc. = LAB_X19_Y10; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[11\]~135'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[10]~133 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[11]~135 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.228 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[12\]~137 15 COMB LAB_X19_Y10 2 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 5.228 ns; Loc. = LAB_X19_Y10; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[12\]~137'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[11]~135 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[12]~137 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.314 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[13\]~139 16 COMB LAB_X19_Y10 2 " "Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 5.314 ns; Loc. = LAB_X19_Y10; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[13\]~139'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[12]~137 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[13]~139 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.400 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[14\]~141 17 COMB LAB_X19_Y10 2 " "Info: 17: + IC(0.000 ns) + CELL(0.086 ns) = 5.400 ns; Loc. = LAB_X19_Y10; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[14\]~141'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[13]~139 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[14]~141 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.486 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[15\]~143 18 COMB LAB_X19_Y10 2 " "Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 5.486 ns; Loc. = LAB_X19_Y10; Fanout = 2; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[15\]~143'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[14]~141 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15]~143 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 5.572 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[16\]~145 19 COMB LAB_X19_Y10 1 " "Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 5.572 ns; Loc. = LAB_X19_Y10; Fanout = 1; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[16\]~145'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15]~143 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[16]~145 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 6.078 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[17\]~146 20 COMB LAB_X19_Y10 1 " "Info: 20: + IC(0.000 ns) + CELL(0.506 ns) = 6.078 ns; Loc. = LAB_X19_Y10; Fanout = 1; COMB Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[17\]~146'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[16]~145 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[17]~146 } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.638 ns) + CELL(1.545 ns) 8.261 ns butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[17\] 21 REG DSPMULT_X20_Y10_N0 19 " "Info: 21: + IC(0.638 ns) + CELL(1.545 ns) = 8.261 ns; Loc. = DSPMULT_X20_Y10_N0; Fanout = 19; REG Node = 'butterfly:inst48\|complex_mult:mult\|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component\|lpm_add_sub:subtractor1\|add_sub_6ji:auto_generated\|pipeline_dffe\[17\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.183 ns" { butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[17]~146 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[17] } "NODE_NAME" } } { "db/add_sub_6ji.tdf" "" { Text "C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.039 ns ( 61.00 % ) " "Info: Total cell delay = 5.039 ns ( 61.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.222 ns ( 39.00 % ) " "Info: Total interconnect delay = 3.222 ns ( 39.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.261 ns" { butterfly:inst48|real_a[0] butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[0]~35 butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[1]~37 butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[2]~39 butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[3]~41 butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[4]~43 butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[5]~45 butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[6]~47 butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[7]~49 butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated|result[8]~50 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[8]~129 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[9]~131 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[10]~133 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[11]~135 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[12]~137 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[13]~139 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[14]~141 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[15]~143 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[16]~145 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[17]~146 butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated|pipeline_dffe[17] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "8 " "Info: Average interconnect usage is 8% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "17 X11_Y0 X22_Y9 " "Info: Peak interconnect usage is 17% of the available device resources in the region that extends from location X11_Y0 to location X22_Y9" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:11 " "Info: Fitter routing operations ending: elapsed time is 00:00:11" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_MAIN_TITLE" "1 " "Info: Fitter merged 1 physical RAM blocks that contain multiple logical RAM slices into a single location" { { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_TITLE" "" "Info: Following physical RAM blocks contain multiple logical RAM slices" { { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_PHYSICAL_LOCATION" "M4K_X11_Y9 " "Info: Physical RAM block M4K_X11_Y9 contains the following logical RAM slices" { { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a0 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a0" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a1 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a1" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a2 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a2" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a3 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a3" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a4 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a4" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a5 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a5" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a6 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a6" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a7 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a7" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a8 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a8" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a9 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a9" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a10 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a10" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a11 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a11" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a12 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a12" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a13 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a13" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a14 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a14" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a15 " "Info: RAM slice: lpm_rom0:inst1\|altsyncram:altsyncram_component\|altsyncram_oh91:auto_generated\|ram_block1a15" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a0 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a0" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a1 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a1" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a2 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a2" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a3 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a3" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a4 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a4" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a5 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a5" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a6 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a6" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a7 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a7" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a8 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a8" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a9 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a9" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a10 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a10" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a11 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a11" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a12 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a12" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a13 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a13" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a14 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a14" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a15 " "Info: RAM slice: lpm_rom1:inst2\|altsyncram:altsyncram_component\|altsyncram_qq71:auto_generated\|ram_block1a15" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0}  } {  } 2 0 "Physical RAM block %1!s! contains the following logical RAM slices" 0 0 "" 0}  } {  } 2 0 "Following physical RAM blocks contain multiple logical RAM slices" 0 0 "" 0}  } {  } 2 0 "Fitter merged %1!llu! physical RAM blocks that contain multiple logical RAM slices into a single location" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "53 " "Warning: Found 53 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "source_eop 0 " "Info: Pin \"source_eop\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "source_sop 0 " "Info: Pin \"source_sop\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "source_valid18 0 " "Info: Pin \"source_valid18\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[15\] 0 " "Info: Pin \"Imagdata_out\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[14\] 0 " "Info: Pin \"Imagdata_out\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[13\] 0 " "Info: Pin \"Imagdata_out\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[12\] 0 " "Info: Pin \"Imagdata_out\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[11\] 0 " "Info: Pin \"Imagdata_out\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[10\] 0 " "Info: Pin \"Imagdata_out\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[9\] 0 " "Info: Pin \"Imagdata_out\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[8\] 0 " "Info: Pin \"Imagdata_out\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[7\] 0 " "Info: Pin \"Imagdata_out\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[6\] 0 " "Info: Pin \"Imagdata_out\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[5\] 0 " "Info: Pin \"Imagdata_out\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[4\] 0 " "Info: Pin \"Imagdata_out\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[3\] 0 " "Info: Pin \"Imagdata_out\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[2\] 0 " "Info: Pin \"Imagdata_out\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[1\] 0 " "Info: Pin \"Imagdata_out\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Imagdata_out\[0\] 0 " "Info: Pin \"Imagdata_out\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[15\] 0 " "Info: Pin \"Realdata_out\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[14\] 0 " "Info: Pin \"Realdata_out\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[13\] 0 " "Info: Pin \"Realdata_out\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[12\] 0 " "Info: Pin \"Realdata_out\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[11\] 0 " "Info: Pin \"Realdata_out\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[10\] 0 " "Info: Pin \"Realdata_out\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[9\] 0 " "Info: Pin \"Realdata_out\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[8\] 0 " "Info: Pin \"Realdata_out\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[7\] 0 " "Info: Pin \"Realdata_out\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[6\] 0 " "Info: Pin \"Realdata_out\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[5\] 0 " "Info: Pin \"Realdata_out\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[4\] 0 " "Info: Pin \"Realdata_out\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[3\] 0 " "Info: Pin \"Realdata_out\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[2\] 0 " "Info: Pin \"Realdata_out\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[1\] 0 " "Info: Pin \"Realdata_out\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Realdata_out\[0\] 0 " "Info: Pin \"Realdata_out\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[15\] 0 " "Info: Pin \"sin\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[14\] 0 " "Info: Pin \"sin\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[13\] 0 " "Info: Pin \"sin\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[12\] 0 " "Info: Pin \"sin\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[11\] 0 " "Info: Pin \"sin\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[10\] 0 " "Info: Pin \"sin\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[9\] 0 " "Info: Pin \"sin\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[8\] 0 " "Info: Pin \"sin\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[7\] 0 " "Info: Pin \"sin\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[6\] 0 " "Info: Pin \"sin\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[5\] 0 " "Info: Pin \"sin\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[4\] 0 " "Info: Pin \"sin\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[3\] 0 " "Info: Pin \"sin\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[2\] 0 " "Info: Pin \"sin\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[1\] 0 " "Info: Pin \"sin\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sin\[0\] 0 " "Info: Pin \"sin\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "state\[1\] 0 " "Info: Pin \"state\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "state\[0\] 0 " "Info: Pin \"state\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|reset_all~clkctrl " "Info: Node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|reset_all~clkctrl uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[1\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[1\] -- routed using non-global resources" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[1] } "NODE_NAME" } } { "LPM_SHIFTREG.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf" 56 7 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[1] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[35\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[35\] -- routed using non-global resources" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[35] } "NODE_NAME" } } { "LPM_SHIFTREG.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf" 56 7 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[35] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[0\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[0\] -- routed using non-global resources" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[0] } "NODE_NAME" } } { "LPM_SHIFTREG.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf" 56 7 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[37\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[37\] -- routed using non-global resources" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[37] } "NODE_NAME" } } { "LPM_SHIFTREG.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf" 56 7 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[37] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[36\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[36\] -- routed using non-global resources" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[36] } "NODE_NAME" } } { "LPM_SHIFTREG.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf" 56 7 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[36] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|reset_all~clkctrl } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 737 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|reset_all~clkctrl } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]~clkctrl " "Info: Node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]~clkctrl uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|jtag_debug_mode " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|jtag_debug_mode -- routed using non-global resources" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 394 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]~clkctrl } "NODE_NAME" } } { "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 1163 -1 0 } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]~clkctrl } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Documents and Settings/wangwei/桌面/FFT last edition/FFT.fit.smsg " "Info: Generated suppressed messages file C:/Documents and Settings/wangwei/桌面/FFT last edition/FFT.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 10 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "195 " "Info: Allocated 195 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 06 17:14:14 2010 " "Info: Processing ended: Sun Jun 06 17:14:14 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:01:39 " "Info: Elapsed time: 00:01:39" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
