--altshift_taps CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" NUMBER_OF_TAPS=1 TAP_DISTANCE=3 WIDTH=34 clock shiftin taps CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" lpm_hint="ONE_INPUT_IS_CONSTANT=NO"
--VERSION_BEGIN 7.2 cbx_altdpram 2007:04:25:14:55:30:SJ cbx_altshift_taps 2007:04:05:16:27:30:SJ cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_counter 2007:08:07:01:40:08:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  without limitation, that your use is for the sole purpose of 
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FUNCTION altsyncram_hg31 (address_a[1..0], address_b[1..0], clock0, clock1, clocken0, clocken1, data_a[33..0], wren_a)
RETURNS ( q_b[33..0]);
FUNCTION add_sub_gvd (dataa[1..0], datab[1..0])
RETURNS ( result[1..0]);
FUNCTION cntr_kkf (clk_en, clock)
RETURNS ( q[1..0]);

--synthesis_resources = lut 3 M4K 1 reg 4 
SUBDESIGN shift_taps_5hp
( 
	clock	:	input;
	shiftin[33..0]	:	input;
	shiftout[33..0]	:	output;
	taps[33..0]	:	output;
) 
VARIABLE 
	altsyncram4 : altsyncram_hg31;
	dffe3a[1..0] : dffe;
	add_sub2 : add_sub_gvd;
	cntr1 : cntr_kkf;
	clken	: NODE;
	rdaddress[1..0]	: WIRE;

BEGIN 
	altsyncram4.address_a[] = cntr1.q[];
	altsyncram4.address_b[] = rdaddress[];
	altsyncram4.clock0 = clock;
	altsyncram4.clock1 = clock;
	altsyncram4.clocken0 = clken;
	altsyncram4.clocken1 = clken;
	altsyncram4.data_a[] = ( shiftin[]);
	altsyncram4.wren_a = B"1";
	dffe3a[].clk = clock;
	dffe3a[].d = ( (! add_sub2.result[1..1]), add_sub2.result[0..0]);
	dffe3a[].ena = clken;
	add_sub2.dataa[] = cntr1.q[];
	add_sub2.datab[] = B"00";
	cntr1.clk_en = clken;
	cntr1.clock = clock;
	clken = VCC;
	rdaddress[] = ( (! dffe3a[1..1].q), dffe3a[0..0].q);
	shiftout[33..0] = altsyncram4.q_b[33..0];
	taps[] = altsyncram4.q_b[];
END;
--VALID FILE
