Analysis & Synthesis report for FFT
Sun Jun 06 17:12:21 2010
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. Analysis & Synthesis DSP Block Usage Summary
  9. State Machine - |block|block_new:inst45|current_state
 10. State Machine - |block|butterfly:inst48|current_state
 11. State Machine - |block|ctrl_fft:inst3|current_state
 12. State Machine - |block|T_control:inst46|current_state
 13. State Machine - |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state
 14. Registers Removed During Synthesis
 15. Removed Registers Triggering Further Register Optimizations
 16. Registers Protected by Synthesis
 17. General Register Statistics
 18. Inverted Register Statistics
 19. Multiplexer Restructuring Statistics (Restructuring Performed)
 20. Source assignments for T_control:inst46|lpm_ram_dq0:ram1|altsyncram:altsyncram_component|altsyncram_n4a1:auto_generated
 21. Source assignments for T_control:inst46|lpm_ram_dq0:ram2|altsyncram:altsyncram_component|altsyncram_n4a1:auto_generated
 22. Source assignments for lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|dpram_fv01:FIFOram|altsyncram_avj1:altsyncram1
 23. Source assignments for butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1|mult_add_dqa1:auto_generated|ded_mult_1t51:ded_mult1|dffpipe_b3c:pre_result
 24. Source assignments for butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add2|mult_add_dqa1:auto_generated|ded_mult_1t51:ded_mult1|dffpipe_b3c:pre_result
 25. Source assignments for butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6|mult_add_ie81:auto_generated|ded_mult_2a21:ded_mult1|dffpipe_d3c:pre_result
 26. Source assignments for lpm_rom1:inst2|altsyncram:altsyncram_component|altsyncram_qq71:auto_generated
 27. Source assignments for lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_oh91:auto_generated
 28. Source assignments for lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|dpram_fv01:FIFOram|altsyncram_avj1:altsyncram1
 29. Source assignments for lpm_rom2:inst19|altsyncram:altsyncram_component|altsyncram_kfa1:auto_generated
 30. Source assignments for lpm_counter0:inst4|lpm_counter:lpm_counter_component
 31. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body
 32. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity
 33. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_i7p3:auto_generated
 34. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_i7p3:auto_generated|altsyncram_ugq1:altsyncram1
 35. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter
 36. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter
 37. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter
 38. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter
 39. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr
 40. Source assignments for sld_hub:sld_hub_inst
 41. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 42. Source assignments for butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component|add_sub_vmg:auto_generated|altshift_taps:pipeline_dffe_rtl_0|shift_taps_5hp:auto_generated|altsyncram_hg31:altsyncram4
 43. Parameter Settings for User Entity Instance: T_control:inst46
 44. Parameter Settings for User Entity Instance: T_control:inst46|lpm_ram_dq0:ram1|altsyncram:altsyncram_component
 45. Parameter Settings for User Entity Instance: T_control:inst46|lpm_ram_dq0:ram2|altsyncram:altsyncram_component
 46. Parameter Settings for User Entity Instance: reset_ctrl:inst5
 47. Parameter Settings for User Entity Instance: lpm_fifo0:inst24|scfifo:scfifo_component
 48. Parameter Settings for User Entity Instance: p2s:inst28
 49. Parameter Settings for User Entity Instance: butterfly:inst48
 50. Parameter Settings for User Entity Instance: butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component
 51. Parameter Settings for User Entity Instance: butterfly:inst48|ADD_17:add_imag|lpm_add_sub:lpm_add_sub_component
 52. Parameter Settings for User Entity Instance: butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component
 53. Parameter Settings for User Entity Instance: butterfly:inst48|SUB_17:sub_imag|lpm_add_sub:lpm_add_sub_component
 54. Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1
 55. Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add2
 56. Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6
 57. Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:add_sub7
 58. Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder1
 59. Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder2
 60. Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1
 61. Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor2
 62. Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor3
 63. Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_compare:comparator1
 64. Parameter Settings for User Entity Instance: s2p:inst6
 65. Parameter Settings for User Entity Instance: s2p:inst7
 66. Parameter Settings for User Entity Instance: lpm_rom1:inst2|altsyncram:altsyncram_component
 67. Parameter Settings for User Entity Instance: lpm_rom0:inst1|altsyncram:altsyncram_component
 68. Parameter Settings for User Entity Instance: lpm_fifo0:inst|scfifo:scfifo_component
 69. Parameter Settings for User Entity Instance: p2s:inst13
 70. Parameter Settings for User Entity Instance: lpm_rom2:inst19|altsyncram:altsyncram_component
 71. Parameter Settings for User Entity Instance: lpm_counter0:inst4|lpm_counter:lpm_counter_component
 72. Parameter Settings for User Entity Instance: block_new:inst45
 73. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 74. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 75. Parameter Settings for Inferred Entity Instance: butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component|add_sub_vmg:auto_generated|altshift_taps:pipeline_dffe_rtl_0
 76. scfifo Parameter Settings by Entity Instance
 77. altmult_add Parameter Settings by Entity Instance
 78. altshift_taps Parameter Settings by Entity Instance
 79. SignalTap II Logic Analyzer Settings
 80. Analysis & Synthesis Messages
 81. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
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+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Sun Jun 06 17:12:20 2010    ;
; Quartus II Version                 ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name                      ; FFT                                      ;
; Top-level Entity Name              ; block                                    ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; 1,655                                    ;
;     Total combinational functions  ; 1,275                                    ;
;     Dedicated logic registers      ; 1,655                                    ;
; Total registers                    ; 1655                                     ;
; Total pins                         ; 59                                       ;
; Total virtual pins                 ; 55                                       ;
; Total memory bits                  ; 117,350                                  ;
; Embedded Multiplier 9-bit elements ; 6                                        ;
; Total PLLs                         ; 0                                        ;
+------------------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                         ; EP2C8Q208C8        ;                    ;
; Top-level entity name                                                          ; block              ; FFT                ;
; Family name                                                                    ; Cyclone II         ; Stratix II         ;
; Use Generated Physical Constraints File                                        ; Off                ;                    ;
; Use smart compilation                                                          ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation                            ; 1                  ; 1                  ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; Parallel Synthesis                                                             ; Off                ; Off                ;
; DSP Block Balancing                                                            ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Optimization Technique -- Cyclone II/Cyclone III                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto ROM Replacement                                                           ; On                 ; On                 ;
; Auto RAM Replacement                                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                              ; Off                ; Off                ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                   ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                   ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+
; T_control.v                      ; yes             ; User Verilog HDL File              ; C:/Documents and Settings/wangwei/桌面/FFT last edition/T_control.v            ;
; block.bdf                        ; yes             ; User Block Diagram/Schematic File  ; C:/Documents and Settings/wangwei/桌面/FFT last edition/block.bdf              ;
; butterfly.v                      ; yes             ; User Verilog HDL File              ; C:/Documents and Settings/wangwei/桌面/FFT last edition/butterfly.v            ;
; s2p.v                            ; yes             ; User Verilog HDL File              ; C:/Documents and Settings/wangwei/桌面/FFT last edition/s2p.v                  ;
; p2s.v                            ; yes             ; User Verilog HDL File              ; C:/Documents and Settings/wangwei/桌面/FFT last edition/p2s.v                  ;
; block_new.v                      ; yes             ; User Verilog HDL File              ; C:/Documents and Settings/wangwei/桌面/FFT last edition/block_new.v            ;
; makeup_sign.v                    ; yes             ; User Verilog HDL File              ; C:/Documents and Settings/wangwei/桌面/FFT last edition/makeup_sign.v          ;
; ctrl_fft.vhd                     ; yes             ; User VHDL File                     ; C:/Documents and Settings/wangwei/桌面/FFT last edition/ctrl_fft.vhd           ;
; reset_ctrl.vhd                   ; yes             ; User VHDL File                     ; C:/Documents and Settings/wangwei/桌面/FFT last edition/reset_ctrl.vhd         ;
; lpm_ram_dq0.v                    ; yes             ; Other                              ; C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_ram_dq0.v          ;
; altsyncram.tdf                   ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf                    ;
; stratix_ram_block.inc            ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/stratix_ram_block.inc             ;
; lpm_mux.inc                      ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/lpm_mux.inc                       ;
; lpm_decode.inc                   ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/lpm_decode.inc                    ;
; aglobal72.inc                    ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/aglobal72.inc                     ;
; a_rdenreg.inc                    ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/a_rdenreg.inc                     ;
; altrom.inc                       ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/altrom.inc                        ;
; altram.inc                       ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/altram.inc                        ;
; altdpram.inc                     ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/altdpram.inc                      ;
; altqpram.inc                     ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/altqpram.inc                      ;
; db/altsyncram_n4a1.tdf           ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/altsyncram_n4a1.tdf ;
; lpm_fifo0.v                      ; yes             ; Other                              ; C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_fifo0.v            ;
; scfifo.tdf                       ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/scfifo.tdf                        ;
; a_regfifo.inc                    ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/a_regfifo.inc                     ;
; a_dpfifo.inc                     ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/a_dpfifo.inc                      ;
; a_i2fifo.inc                     ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/a_i2fifo.inc                      ;
; a_fffifo.inc                     ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/a_fffifo.inc                      ;
; a_f2fifo.inc                     ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/a_f2fifo.inc                      ;
; db/scfifo_7r31.tdf               ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/scfifo_7r31.tdf     ;
; db/a_dpfifo_e141.tdf             ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/a_dpfifo_e141.tdf   ;
; db/a_fefifo_b6f.tdf              ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/a_fefifo_b6f.tdf    ;
; db/cntr_tk7.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cntr_tk7.tdf        ;
; db/dpram_fv01.tdf                ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/dpram_fv01.tdf      ;
; db/altsyncram_avj1.tdf           ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/altsyncram_avj1.tdf ;
; db/cntr_fjb.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cntr_fjb.tdf        ;
; ADD_17.v                         ; yes             ; Other                              ; C:/Documents and Settings/wangwei/桌面/FFT last edition/ADD_17.v               ;
; lpm_add_sub.tdf                  ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf                   ;
; addcore.inc                      ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/addcore.inc                       ;
; look_add.inc                     ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/look_add.inc                      ;
; bypassff.inc                     ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/bypassff.inc                      ;
; altshift.inc                     ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/altshift.inc                      ;
; alt_stratix_add_sub.inc          ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/alt_stratix_add_sub.inc           ;
; alt_mercury_add_sub.inc          ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/alt_mercury_add_sub.inc           ;
; db/add_sub_vmg.tdf               ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_vmg.tdf     ;
; SUB_17.v                         ; yes             ; Other                              ; C:/Documents and Settings/wangwei/桌面/FFT last edition/SUB_17.v               ;
; db/add_sub_4qe.tdf               ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_4qe.tdf     ;
; db/complex_mult.v                ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v      ;
; altmult_add.tdf                  ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/altmult_add.tdf                   ;
; stratix_mac_mult.inc             ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/stratix_mac_mult.inc              ;
; stratix_mac_out.inc              ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/stratix_mac_out.inc               ;
; db/mult_add_dqa1.tdf             ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/mult_add_dqa1.tdf   ;
; db/ded_mult_1t51.tdf             ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/ded_mult_1t51.tdf   ;
; db/dffpipe_b3c.tdf               ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/dffpipe_b3c.tdf     ;
; db/mult_add_ie81.tdf             ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/mult_add_ie81.tdf   ;
; db/ded_mult_2a21.tdf             ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/ded_mult_2a21.tdf   ;
; db/dffpipe_d3c.tdf               ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/dffpipe_d3c.tdf     ;
; db/add_sub_esf.tdf               ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_esf.tdf     ;
; db/add_sub_5ii.tdf               ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_5ii.tdf     ;
; db/add_sub_6ii.tdf               ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ii.tdf     ;
; db/add_sub_6ji.tdf               ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_6ji.tdf     ;
; db/add_sub_5ji.tdf               ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_5ji.tdf     ;
; db/add_sub_i5j.tdf               ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_i5j.tdf     ;
; lpm_compare.tdf                  ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/lpm_compare.tdf                   ;
; comptree.inc                     ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/comptree.inc                      ;
; db/cmpr_1cg.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cmpr_1cg.tdf        ;
; D.v                              ; yes             ; Other                              ; C:/Documents and Settings/wangwei/桌面/FFT last edition/D.v                    ;
; lpm_rom1.v                       ; yes             ; Other                              ; C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_rom1.v             ;
; db/altsyncram_qq71.tdf           ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/altsyncram_qq71.tdf ;
; lpm_rom0.v                       ; yes             ; Other                              ; C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_rom0.v             ;
; db/altsyncram_oh91.tdf           ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/altsyncram_oh91.tdf ;
; lpm_rom2.v                       ; yes             ; Other                              ; C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_rom2.v             ;
; db/altsyncram_kfa1.tdf           ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/altsyncram_kfa1.tdf ;
; lpm_counter0.v                   ; yes             ; Other                              ; C:/Documents and Settings/wangwei/桌面/FFT last edition/lpm_counter0.v         ;
; lpm_counter.tdf                  ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf                   ;
; lpm_constant.inc                 ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/lpm_constant.inc                  ;
; lpm_add_sub.inc                  ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.inc                   ;
; cmpconst.inc                     ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/cmpconst.inc                      ;
; lpm_compare.inc                  ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/lpm_compare.inc                   ;
; lpm_counter.inc                  ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/lpm_counter.inc                   ;
; dffeea.inc                       ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/dffeea.inc                        ;
; alt_synch_counter.inc            ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/alt_synch_counter.inc             ;
; alt_synch_counter_f.inc          ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/alt_synch_counter_f.inc           ;
; alt_counter_f10ke.inc            ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.inc             ;
; alt_counter_stratix.inc          ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/alt_counter_stratix.inc           ;
; db/cntr_qkh.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cntr_qkh.tdf        ;
; sld_signaltap.vhd                ; yes             ; Encrypted Megafunction             ; e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd                 ;
; sld_ela_control.vhd              ; yes             ; Encrypted Megafunction             ; e:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd               ;
; LPM_SHIFTREG.tdf                 ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf                  ;
; sld_mbpmg.vhd                    ; yes             ; Encrypted Megafunction             ; e:/altera/72/quartus/libraries/megafunctions/sld_mbpmg.vhd                     ;
; sld_ela_trigger_flow_mgr.vhd     ; yes             ; Encrypted Megafunction             ; e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd      ;
; sld_buffer_manager.vhd           ; yes             ; Encrypted Megafunction             ; e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd            ;
; db/altsyncram_i7p3.tdf           ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/altsyncram_i7p3.tdf ;
; db/altsyncram_ugq1.tdf           ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/altsyncram_ugq1.tdf ;
; altdpram.tdf                     ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/altdpram.tdf                      ;
; memmodes.inc                     ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/others/maxplus2/memmodes.inc                    ;
; a_hdffe.inc                      ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/a_hdffe.inc                       ;
; alt_le_rden_reg.inc              ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/alt_le_rden_reg.inc               ;
; altsyncram.inc                   ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/altsyncram.inc                    ;
; lpm_mux.tdf                      ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/lpm_mux.tdf                       ;
; muxlut.inc                       ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/muxlut.inc                        ;
; db/mux_9oc.tdf                   ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/mux_9oc.tdf         ;
; lpm_decode.tdf                   ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/lpm_decode.tdf                    ;
; declut.inc                       ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/declut.inc                        ;
; db/decode_rqf.tdf                ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/decode_rqf.tdf      ;
; db/cntr_fbi.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cntr_fbi.tdf        ;
; db/cntr_c4j.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cntr_c4j.tdf        ;
; db/cntr_bbi.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cntr_bbi.tdf        ;
; db/cntr_uti.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cntr_uti.tdf        ;
; sld_rom_sr.vhd                   ; yes             ; Encrypted Megafunction             ; e:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd                    ;
; sld_hub.vhd                      ; yes             ; Encrypted Megafunction             ; e:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd                       ;
; db/decode_aoi.tdf                ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/decode_aoi.tdf      ;
; sld_dffex.vhd                    ; yes             ; Encrypted Megafunction             ; e:/altera/72/quartus/libraries/megafunctions/sld_dffex.vhd                     ;
; altshift_taps.tdf                ; yes             ; Megafunction                       ; e:/altera/72/quartus/libraries/megafunctions/altshift_taps.tdf                 ;
; db/shift_taps_5hp.tdf            ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/shift_taps_5hp.tdf  ;
; db/altsyncram_hg31.tdf           ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/altsyncram_hg31.tdf ;
; db/add_sub_gvd.tdf               ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/add_sub_gvd.tdf     ;
; db/cntr_kkf.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Documents and Settings/wangwei/桌面/FFT last edition/db/cntr_kkf.tdf        ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+


+------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary          ;
+---------------------------------------------+--------+
; Resource                                    ; Usage  ;
+---------------------------------------------+--------+
; Estimated Total logic elements              ; 1,655  ;
;                                             ;        ;
; Total combinational functions               ; 1275   ;
; Logic element usage by number of LUT inputs ;        ;
;     -- 4 input functions                    ; 554    ;
;     -- 3 input functions                    ; 342    ;
;     -- <=2 input functions                  ; 379    ;
;                                             ;        ;
; Logic elements by mode                      ;        ;
;     -- normal mode                          ; 938    ;
;     -- arithmetic mode                      ; 337    ;
;                                             ;        ;
; Total registers                             ; 1655   ;
;     -- Dedicated logic registers            ; 1655   ;
;     -- I/O registers                        ; 0      ;
;                                             ;        ;
; Virtual pins                                ; 55     ;
; I/O pins                                    ; 59     ;
; Total memory bits                           ; 117350 ;
; Embedded Multiplier 9-bit elements          ; 6      ;
; Maximum fan-out node                        ; clk    ;
; Maximum fan-out                             ; 1429   ;
; Total fan-out                               ; 11814  ;
; Average fan-out                             ; 3.63   ;
+---------------------------------------------+--------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                                                                           ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                                                                                                                  ; Library Name ;
+------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |block                                                                                               ; 1275 (56)         ; 1655 (0)     ; 117350      ; 6            ; 0       ; 3         ; 59   ; 55           ; |block                                                                                                                                                                                                                                                                                               ; work         ;
;    |D:inst11|                                                                                        ; 0 (0)             ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|D:inst11                                                                                                                                                                                                                                                                                      ; work         ;
;    |D:inst14|                                                                                        ; 0 (0)             ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|D:inst14                                                                                                                                                                                                                                                                                      ; work         ;
;    |D:inst15|                                                                                        ; 0 (0)             ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|D:inst15                                                                                                                                                                                                                                                                                      ; work         ;
;    |D:inst16|                                                                                        ; 0 (0)             ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|D:inst16                                                                                                                                                                                                                                                                                      ; work         ;
;    |T_control:inst46|                                                                                ; 206 (206)         ; 16 (16)      ; 2304        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|T_control:inst46                                                                                                                                                                                                                                                                              ; work         ;
;       |lpm_ram_dq0:ram1|                                                                             ; 0 (0)             ; 0 (0)        ; 1152        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|T_control:inst46|lpm_ram_dq0:ram1                                                                                                                                                                                                                                                             ; work         ;
;          |altsyncram:altsyncram_component|                                                           ; 0 (0)             ; 0 (0)        ; 1152        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|T_control:inst46|lpm_ram_dq0:ram1|altsyncram:altsyncram_component                                                                                                                                                                                                                             ; work         ;
;             |altsyncram_n4a1:auto_generated|                                                         ; 0 (0)             ; 0 (0)        ; 1152        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|T_control:inst46|lpm_ram_dq0:ram1|altsyncram:altsyncram_component|altsyncram_n4a1:auto_generated                                                                                                                                                                                              ; work         ;
;       |lpm_ram_dq0:ram2|                                                                             ; 0 (0)             ; 0 (0)        ; 1152        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|T_control:inst46|lpm_ram_dq0:ram2                                                                                                                                                                                                                                                             ; work         ;
;          |altsyncram:altsyncram_component|                                                           ; 0 (0)             ; 0 (0)        ; 1152        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|T_control:inst46|lpm_ram_dq0:ram2|altsyncram:altsyncram_component                                                                                                                                                                                                                             ; work         ;
;             |altsyncram_n4a1:auto_generated|                                                         ; 0 (0)             ; 0 (0)        ; 1152        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|T_control:inst46|lpm_ram_dq0:ram2|altsyncram:altsyncram_component|altsyncram_n4a1:auto_generated                                                                                                                                                                                              ; work         ;
;    |block_new:inst45|                                                                                ; 21 (21)           ; 13 (13)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|block_new:inst45                                                                                                                                                                                                                                                                              ; work         ;
;    |butterfly:inst48|                                                                                ; 233 (24)          ; 397 (105)    ; 102         ; 6            ; 0       ; 3         ; 0    ; 0            ; |block|butterfly:inst48                                                                                                                                                                                                                                                                              ; work         ;
;       |ADD_17:add_imag|                                                                              ; 17 (0)            ; 17 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|ADD_17:add_imag                                                                                                                                                                                                                                                              ; work         ;
;          |lpm_add_sub:lpm_add_sub_component|                                                         ; 17 (0)            ; 17 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|ADD_17:add_imag|lpm_add_sub:lpm_add_sub_component                                                                                                                                                                                                                            ; work         ;
;             |add_sub_vmg:auto_generated|                                                             ; 17 (17)           ; 17 (17)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|ADD_17:add_imag|lpm_add_sub:lpm_add_sub_component|add_sub_vmg:auto_generated                                                                                                                                                                                                 ; work         ;
;       |ADD_17:add_real|                                                                              ; 24 (0)            ; 21 (0)       ; 102         ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|ADD_17:add_real                                                                                                                                                                                                                                                              ; work         ;
;          |lpm_add_sub:lpm_add_sub_component|                                                         ; 24 (0)            ; 21 (0)       ; 102         ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component                                                                                                                                                                                                                            ; work         ;
;             |add_sub_vmg:auto_generated|                                                             ; 24 (17)           ; 21 (17)      ; 102         ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component|add_sub_vmg:auto_generated                                                                                                                                                                                                 ; work         ;
;                |altshift_taps:pipeline_dffe_rtl_0|                                                   ; 7 (0)             ; 4 (0)        ; 102         ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component|add_sub_vmg:auto_generated|altshift_taps:pipeline_dffe_rtl_0                                                                                                                                                               ; work         ;
;                   |shift_taps_5hp:auto_generated|                                                    ; 7 (2)             ; 4 (2)        ; 102         ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component|add_sub_vmg:auto_generated|altshift_taps:pipeline_dffe_rtl_0|shift_taps_5hp:auto_generated                                                                                                                                 ; work         ;
;                      |altsyncram_hg31:altsyncram4|                                                   ; 0 (0)             ; 0 (0)        ; 102         ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component|add_sub_vmg:auto_generated|altshift_taps:pipeline_dffe_rtl_0|shift_taps_5hp:auto_generated|altsyncram_hg31:altsyncram4                                                                                                     ; work         ;
;                      |cntr_kkf:cntr1|                                                                ; 5 (5)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component|add_sub_vmg:auto_generated|altshift_taps:pipeline_dffe_rtl_0|shift_taps_5hp:auto_generated|cntr_kkf:cntr1                                                                                                                  ; work         ;
;       |SUB_17:sub_imag|                                                                              ; 17 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|SUB_17:sub_imag                                                                                                                                                                                                                                                              ; work         ;
;          |lpm_add_sub:lpm_add_sub_component|                                                         ; 17 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|SUB_17:sub_imag|lpm_add_sub:lpm_add_sub_component                                                                                                                                                                                                                            ; work         ;
;             |add_sub_4qe:auto_generated|                                                             ; 17 (17)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|SUB_17:sub_imag|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated                                                                                                                                                                                                 ; work         ;
;       |SUB_17:sub_real|                                                                              ; 17 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|SUB_17:sub_real                                                                                                                                                                                                                                                              ; work         ;
;          |lpm_add_sub:lpm_add_sub_component|                                                         ; 17 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component                                                                                                                                                                                                                            ; work         ;
;             |add_sub_4qe:auto_generated|                                                             ; 17 (17)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated                                                                                                                                                                                                 ; work         ;
;       |complex_mult:mult|                                                                            ; 134 (0)           ; 254 (0)      ; 0           ; 6            ; 0       ; 3         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult                                                                                                                                                                                                                                                            ; work         ;
;          |complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|               ; 134 (0)           ; 254 (0)      ; 0           ; 6            ; 0       ; 3         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component                                                                                                                                                                                ; work         ;
;             |altmult_add:mult_add1|                                                                  ; 0 (0)             ; 33 (0)       ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1                                                                                                                                                          ; work         ;
;                |mult_add_dqa1:auto_generated|                                                        ; 0 (0)             ; 33 (33)      ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1|mult_add_dqa1:auto_generated                                                                                                                             ; work         ;
;                   |ded_mult_1t51:ded_mult1|                                                          ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1|mult_add_dqa1:auto_generated|ded_mult_1t51:ded_mult1                                                                                                     ; work         ;
;             |altmult_add:mult_add2|                                                                  ; 0 (0)             ; 33 (0)       ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add2                                                                                                                                                          ; work         ;
;                |mult_add_dqa1:auto_generated|                                                        ; 0 (0)             ; 33 (33)      ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add2|mult_add_dqa1:auto_generated                                                                                                                             ; work         ;
;                   |ded_mult_1t51:ded_mult1|                                                          ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add2|mult_add_dqa1:auto_generated|ded_mult_1t51:ded_mult1                                                                                                     ; work         ;
;             |altmult_add:mult_add6|                                                                  ; 0 (0)             ; 33 (0)       ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6                                                                                                                                                          ; work         ;
;                |mult_add_ie81:auto_generated|                                                        ; 0 (0)             ; 33 (33)      ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6|mult_add_ie81:auto_generated                                                                                                                             ; work         ;
;                   |ded_mult_2a21:ded_mult1|                                                          ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6|mult_add_ie81:auto_generated|ded_mult_2a21:ded_mult1                                                                                                     ; work         ;
;             |lpm_add_sub:add_sub7|                                                                   ; 33 (0)            ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:add_sub7                                                                                                                                                           ; work         ;
;                |add_sub_esf:auto_generated|                                                          ; 33 (33)           ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:add_sub7|add_sub_esf:auto_generated                                                                                                                                ; work         ;
;             |lpm_add_sub:adder1|                                                                     ; 17 (0)            ; 17 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder1                                                                                                                                                             ; work         ;
;                |add_sub_5ii:auto_generated|                                                          ; 17 (17)           ; 17 (17)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder1|add_sub_5ii:auto_generated                                                                                                                                  ; work         ;
;             |lpm_add_sub:adder2|                                                                     ; 33 (0)            ; 36 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder2                                                                                                                                                             ; work         ;
;                |add_sub_6ii:auto_generated|                                                          ; 33 (33)           ; 36 (36)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder2|add_sub_6ii:auto_generated                                                                                                                                  ; work         ;
;             |lpm_add_sub:subtractor1|                                                                ; 18 (0)            ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1                                                                                                                                                        ; work         ;
;                |add_sub_6ji:auto_generated|                                                          ; 18 (18)           ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated                                                                                                                             ; work         ;
;             |lpm_add_sub:subtractor2|                                                                ; 33 (0)            ; 33 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor2                                                                                                                                                        ; work         ;
;                |add_sub_5ji:auto_generated|                                                          ; 33 (33)           ; 33 (33)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor2|add_sub_5ji:auto_generated                                                                                                                             ; work         ;
;             |lpm_add_sub:subtractor3|                                                                ; 0 (0)             ; 33 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor3                                                                                                                                                        ; work         ;
;                |add_sub_i5j:auto_generated|                                                          ; 0 (0)             ; 33 (33)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor3|add_sub_i5j:auto_generated                                                                                                                             ; work         ;
;    |ctrl_fft:inst3|                                                                                  ; 30 (30)           ; 15 (15)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|ctrl_fft:inst3                                                                                                                                                                                                                                                                                ; work         ;
;    |lpm_counter0:inst4|                                                                              ; 6 (0)             ; 6 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_counter0:inst4                                                                                                                                                                                                                                                                            ; work         ;
;       |lpm_counter:lpm_counter_component|                                                            ; 6 (0)             ; 6 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_counter0:inst4|lpm_counter:lpm_counter_component                                                                                                                                                                                                                                          ; work         ;
;          |cntr_qkh:auto_generated|                                                                   ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qkh:auto_generated                                                                                                                                                                                                                  ; work         ;
;    |lpm_fifo0:inst24|                                                                                ; 29 (0)            ; 20 (0)       ; 1152        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst24                                                                                                                                                                                                                                                                              ; work         ;
;       |scfifo:scfifo_component|                                                                      ; 29 (0)            ; 20 (0)       ; 1152        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst24|scfifo:scfifo_component                                                                                                                                                                                                                                                      ; work         ;
;          |scfifo_7r31:auto_generated|                                                                ; 29 (0)            ; 20 (0)       ; 1152        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated                                                                                                                                                                                                                           ; work         ;
;             |a_dpfifo_e141:dpfifo|                                                                   ; 29 (2)            ; 20 (0)       ; 1152        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo                                                                                                                                                                                                      ; work         ;
;                |a_fefifo_b6f:fifo_state|                                                             ; 15 (9)            ; 8 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|a_fefifo_b6f:fifo_state                                                                                                                                                                              ; work         ;
;                   |cntr_tk7:count_usedw|                                                             ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|a_fefifo_b6f:fifo_state|cntr_tk7:count_usedw                                                                                                                                                         ; work         ;
;                |cntr_fjb:rd_ptr_count|                                                               ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|cntr_fjb:rd_ptr_count                                                                                                                                                                                ; work         ;
;                |cntr_fjb:wr_ptr|                                                                     ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|cntr_fjb:wr_ptr                                                                                                                                                                                      ; work         ;
;                |dpram_fv01:FIFOram|                                                                  ; 0 (0)             ; 0 (0)        ; 1152        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|dpram_fv01:FIFOram                                                                                                                                                                                   ; work         ;
;                   |altsyncram_avj1:altsyncram1|                                                      ; 0 (0)             ; 0 (0)        ; 1152        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|dpram_fv01:FIFOram|altsyncram_avj1:altsyncram1                                                                                                                                                       ; work         ;
;    |lpm_fifo0:inst|                                                                                  ; 29 (0)            ; 20 (0)       ; 1152        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst                                                                                                                                                                                                                                                                                ; work         ;
;       |scfifo:scfifo_component|                                                                      ; 29 (0)            ; 20 (0)       ; 1152        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst|scfifo:scfifo_component                                                                                                                                                                                                                                                        ; work         ;
;          |scfifo_7r31:auto_generated|                                                                ; 29 (0)            ; 20 (0)       ; 1152        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated                                                                                                                                                                                                                             ; work         ;
;             |a_dpfifo_e141:dpfifo|                                                                   ; 29 (2)            ; 20 (0)       ; 1152        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo                                                                                                                                                                                                        ; work         ;
;                |a_fefifo_b6f:fifo_state|                                                             ; 15 (9)            ; 8 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|a_fefifo_b6f:fifo_state                                                                                                                                                                                ; work         ;
;                   |cntr_tk7:count_usedw|                                                             ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|a_fefifo_b6f:fifo_state|cntr_tk7:count_usedw                                                                                                                                                           ; work         ;
;                |cntr_fjb:rd_ptr_count|                                                               ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|cntr_fjb:rd_ptr_count                                                                                                                                                                                  ; work         ;
;                |cntr_fjb:wr_ptr|                                                                     ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|cntr_fjb:wr_ptr                                                                                                                                                                                        ; work         ;
;                |dpram_fv01:FIFOram|                                                                  ; 0 (0)             ; 0 (0)        ; 1152        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|dpram_fv01:FIFOram                                                                                                                                                                                     ; work         ;
;                   |altsyncram_avj1:altsyncram1|                                                      ; 0 (0)             ; 0 (0)        ; 1152        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|dpram_fv01:FIFOram|altsyncram_avj1:altsyncram1                                                                                                                                                         ; work         ;
;    |lpm_rom0:inst1|                                                                                  ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_rom0:inst1                                                                                                                                                                                                                                                                                ; work         ;
;       |altsyncram:altsyncram_component|                                                              ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_rom0:inst1|altsyncram:altsyncram_component                                                                                                                                                                                                                                                ; work         ;
;          |altsyncram_oh91:auto_generated|                                                            ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_oh91:auto_generated                                                                                                                                                                                                                 ; work         ;
;    |lpm_rom1:inst2|                                                                                  ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_rom1:inst2                                                                                                                                                                                                                                                                                ; work         ;
;       |altsyncram:altsyncram_component|                                                              ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_rom1:inst2|altsyncram:altsyncram_component                                                                                                                                                                                                                                                ; work         ;
;          |altsyncram_qq71:auto_generated|                                                            ; 0 (0)             ; 0 (0)        ; 512         ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_rom1:inst2|altsyncram:altsyncram_component|altsyncram_qq71:auto_generated                                                                                                                                                                                                                 ; work         ;
;    |lpm_rom2:inst19|                                                                                 ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_rom2:inst19                                                                                                                                                                                                                                                                               ; work         ;
;       |altsyncram:altsyncram_component|                                                              ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_rom2:inst19|altsyncram:altsyncram_component                                                                                                                                                                                                                                               ; work         ;
;          |altsyncram_kfa1:auto_generated|                                                            ; 0 (0)             ; 0 (0)        ; 1024        ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|lpm_rom2:inst19|altsyncram:altsyncram_component|altsyncram_kfa1:auto_generated                                                                                                                                                                                                                ; work         ;
;    |p2s:inst13|                                                                                      ; 63 (63)           ; 43 (43)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|p2s:inst13                                                                                                                                                                                                                                                                                    ; work         ;
;    |p2s:inst28|                                                                                      ; 64 (64)           ; 42 (42)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|p2s:inst28                                                                                                                                                                                                                                                                                    ; work         ;
;    |reset_ctrl:inst5|                                                                                ; 10 (10)           ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|reset_ctrl:inst5                                                                                                                                                                                                                                                                              ; work         ;
;    |s2p:inst6|                                                                                       ; 3 (3)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|s2p:inst6                                                                                                                                                                                                                                                                                     ; work         ;
;    |s2p:inst7|                                                                                       ; 11 (11)           ; 40 (40)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|s2p:inst7                                                                                                                                                                                                                                                                                     ; work         ;
;    |sld_hub:sld_hub_inst|                                                                            ; 97 (42)           ; 79 (7)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_hub:sld_hub_inst                                                                                                                                                                                                                                                                          ; work         ;
;       |lpm_decode:instruction_decoder|                                                               ; 5 (0)             ; 5 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder                                                                                                                                                                                                                                           ; work         ;
;          |decode_aoi:auto_generated|                                                                 ; 5 (5)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated                                                                                                                                                                                                                 ; work         ;
;       |lpm_shiftreg:jtag_ir_register|                                                                ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register                                                                                                                                                                                                                                            ; work         ;
;       |sld_dffex:BROADCAST|                                                                          ; 2 (2)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_hub:sld_hub_inst|sld_dffex:BROADCAST                                                                                                                                                                                                                                                      ; work         ;
;       |sld_dffex:IRF_ENA_0|                                                                          ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0                                                                                                                                                                                                                                                      ; work         ;
;       |sld_dffex:IRF_ENA|                                                                            ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA                                                                                                                                                                                                                                                        ; work         ;
;       |sld_dffex:IRSR|                                                                               ; 4 (4)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_hub:sld_hub_inst|sld_dffex:IRSR                                                                                                                                                                                                                                                           ; work         ;
;       |sld_dffex:RESET|                                                                              ; 2 (2)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_hub:sld_hub_inst|sld_dffex:RESET                                                                                                                                                                                                                                                          ; work         ;
;       |sld_dffex:\GEN_IRF:1:IRF|                                                                     ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF                                                                                                                                                                                                                                                 ; work         ;
;       |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|                                                            ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF                                                                                                                                                                                                                                        ; work         ;
;       |sld_jtag_state_machine:jtag_state_machine|                                                    ; 20 (20)           ; 19 (19)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine                                                                                                                                                                                                                                ; work         ;
;       |sld_rom_sr:HUB_INFO_REG|                                                                      ; 21 (21)           ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG                                                                                                                                                                                                                                                  ; work         ;
;    |sld_signaltap:auto_signaltap_0|                                                                  ; 417 (1)           ; 860 (0)      ; 110592      ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0                                                                                                                                                                                                                                                                ; work         ;
;       |sld_signaltap_impl:sld_signaltap_body|                                                        ; 416 (16)          ; 860 (303)    ; 110592      ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body                                                                                                                                                                                                                          ; work         ;
;          |altdpram:\stp_non_zero_ram_gen:attribute_mem|                                              ; 1 (0)             ; 46 (46)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem                                                                                                                                                                             ; work         ;
;             |lpm_decode:wdecoder|                                                                    ; 1 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|lpm_decode:wdecoder                                                                                                                                                         ; work         ;
;                |decode_rqf:auto_generated|                                                           ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|lpm_decode:wdecoder|decode_rqf:auto_generated                                                                                                                               ; work         ;
;          |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|                                           ; 0 (0)             ; 0 (0)        ; 110592      ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram                                                                                                                                                                          ; work         ;
;             |altsyncram_i7p3:auto_generated|                                                         ; 0 (0)             ; 0 (0)        ; 110592      ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_i7p3:auto_generated                                                                                                                                           ; work         ;
;                |altsyncram_ugq1:altsyncram1|                                                         ; 0 (0)             ; 0 (0)        ; 110592      ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_i7p3:auto_generated|altsyncram_ugq1:altsyncram1                                                                                                               ; work         ;
;          |lpm_shiftreg:segment_offset_config_deserialize|                                            ; 0 (0)             ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize                                                                                                                                                                           ; work         ;
;          |lpm_shiftreg:status_register|                                                              ; 18 (18)           ; 17 (17)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|lpm_shiftreg:status_register                                                                                                                                                                                             ; work         ;
;          |sld_buffer_manager:sld_buffer_manager_inst|                                                ; 98 (98)           ; 64 (64)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst                                                                                                                                                                               ; work         ;
;          |sld_ela_control:ela_control|                                                               ; 131 (0)           ; 289 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control                                                                                                                                                                                              ; work         ;
;             |lpm_shiftreg:trigger_config_deserialize|                                                ; 0 (0)             ; 4 (4)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize                                                                                                                                                      ; work         ;
;             |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm| ; 108 (0)           ; 270 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm                                                                                                       ; work         ;
;                |lpm_shiftreg:trigger_condition_deserialize|                                          ; 0 (0)             ; 162 (162)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize                                                            ; work         ;
;                |sld_mbpmg:\trigger_modules_gen:0:trigger_match|                                      ; 108 (0)           ; 108 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match                                                        ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1  ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1  ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1  ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1  ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1  ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:50:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:50:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:51:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:51:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:52:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:52:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:53:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:53:sm1 ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1  ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1  ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1  ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1  ; work         ;
;                   |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1  ; work         ;
;             |sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|                          ; 21 (21)           ; 13 (3)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity                                                                                                                                ; work         ;
;                |lpm_shiftreg:trigger_config_deserialize|                                             ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|lpm_shiftreg:trigger_config_deserialize                                                                                        ; work         ;
;             |sld_mbpmg:\trigger_in_trigger_module_enabled_gen:trigger_in_match|                      ; 2 (0)             ; 2 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_mbpmg:\trigger_in_trigger_module_enabled_gen:trigger_in_match                                                                                                                            ; work         ;
;                |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|                               ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_mbpmg:\trigger_in_trigger_module_enabled_gen:trigger_in_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1                                                                      ; work         ;
;          |sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|          ; 134 (8)           ; 122 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst                                                                                                                                         ; work         ;
;             |lpm_counter:\adv_point_3_and_more:advance_pointer_counter|                              ; 8 (0)             ; 6 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter                                                                               ; work         ;
;                |cntr_fbi:auto_generated|                                                             ; 8 (8)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_fbi:auto_generated                                                       ; work         ;
;             |lpm_counter:read_pointer_counter|                                                       ; 11 (0)            ; 11 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter                                                                                                        ; work         ;
;                |cntr_c4j:auto_generated|                                                             ; 11 (11)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_c4j:auto_generated                                                                                ; work         ;
;             |lpm_counter:status_advance_pointer_counter|                                             ; 7 (0)             ; 5 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter                                                                                              ; work         ;
;                |cntr_bbi:auto_generated|                                                             ; 7 (7)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_bbi:auto_generated                                                                      ; work         ;
;             |lpm_shiftreg:info_data_shift_out|                                                       ; 23 (23)           ; 23 (23)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out                                                                                                        ; work         ;
;             |lpm_shiftreg:ram_data_shift_out|                                                        ; 54 (54)           ; 54 (54)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out                                                                                                         ; work         ;
;             |lpm_shiftreg:status_data_shift_out|                                                     ; 23 (23)           ; 23 (23)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out                                                                                                      ; work         ;
;          |sld_rom_sr:crc_rom_sr|                                                                     ; 18 (18)           ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr                                                                                                                                                                                                    ; work         ;
+------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                                                                                                     ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------------------------------------------------+
; Name                                                                                                                                                                                                 ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF                                            ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------------------------------------------------+
; T_control:inst46|lpm_ram_dq0:ram1|altsyncram:altsyncram_component|altsyncram_n4a1:auto_generated|ALTSYNCRAM                                                                                          ; AUTO ; Single Port      ; 64           ; 18           ; --           ; --           ; 1152   ; None                                           ;
; T_control:inst46|lpm_ram_dq0:ram2|altsyncram:altsyncram_component|altsyncram_n4a1:auto_generated|ALTSYNCRAM                                                                                          ; AUTO ; Single Port      ; 64           ; 18           ; --           ; --           ; 1152   ; None                                           ;
; butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component|add_sub_vmg:auto_generated|altshift_taps:pipeline_dffe_rtl_0|shift_taps_5hp:auto_generated|altsyncram_hg31:altsyncram4|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 3            ; 34           ; 3            ; 34           ; 102    ; None                                           ;
; lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|dpram_fv01:FIFOram|altsyncram_avj1:altsyncram1|ALTSYNCRAM                                                   ; AUTO ; Simple Dual Port ; 64           ; 18           ; 64           ; 18           ; 1152   ; None                                           ;
; lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|dpram_fv01:FIFOram|altsyncram_avj1:altsyncram1|ALTSYNCRAM                                                     ; AUTO ; Simple Dual Port ; 64           ; 18           ; 64           ; 18           ; 1152   ; None                                           ;
; lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_oh91:auto_generated|ALTSYNCRAM                                                                                                             ; AUTO ; ROM              ; 32           ; 16           ; --           ; --           ; 512    ; ../FFT last edition/WN_rcos.mif                ;
; lpm_rom1:inst2|altsyncram:altsyncram_component|altsyncram_qq71:auto_generated|ALTSYNCRAM                                                                                                             ; AUTO ; ROM              ; 32           ; 16           ; --           ; --           ; 512    ; WN_isin.mif                                    ;
; lpm_rom2:inst19|altsyncram:altsyncram_component|altsyncram_kfa1:auto_generated|ALTSYNCRAM                                                                                                            ; AUTO ; ROM              ; 64           ; 16           ; --           ; --           ; 1024   ; C:/Documents and Settings/wangwei/桌面/sin.mif ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_i7p3:auto_generated|altsyncram_ugq1:altsyncram1|ALTSYNCRAM           ; AUTO ; True Dual Port   ; 2048         ; 54           ; 2048         ; 54           ; 110592 ; None                                           ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary        ;
+---------------------------------------+-------------+
; Statistic                             ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit)            ; 0           ;
; Simple Multipliers (18-bit)           ; 3           ;
; Embedded Multiplier Blocks            ; --          ;
; Embedded Multiplier 9-bit elements    ; 6           ;
; Signed Embedded Multipliers           ; 3           ;
; Unsigned Embedded Multipliers         ; 0           ;
; Mixed Sign Embedded Multipliers       ; 0           ;
; Variable Sign Embedded Multipliers    ; 0           ;
; Dedicated Input Shift Register Chains ; 0           ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.


Encoding Type:  One-Hot
+---------------------------------------------------------------------------+
; State Machine - |block|block_new:inst45|current_state                     ;
+------------------+------------------+------------------+------------------+
; Name             ; current_state.s0 ; current_state.s2 ; current_state.s1 ;
+------------------+------------------+------------------+------------------+
; current_state.s0 ; 0                ; 0                ; 0                ;
; current_state.s1 ; 1                ; 0                ; 1                ;
; current_state.s2 ; 1                ; 1                ; 0                ;
+------------------+------------------+------------------+------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------+
; State Machine - |block|butterfly:inst48|current_state ;
+--------------------+----------------------------------+
; Name               ; current_state.work               ;
+--------------------+----------------------------------+
; current_state.idle ; 0                                ;
; current_state.work ; 1                                ;
+--------------------+----------------------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------+
; State Machine - |block|ctrl_fft:inst3|current_state                                                                    ;
+--------------------------+--------------------------+--------------------------+------------------+--------------------+
; Name                     ; current_state.wait_state ; current_state.assert_eop ; current_state.go ; current_state.idle ;
+--------------------------+--------------------------+--------------------------+------------------+--------------------+
; current_state.idle       ; 0                        ; 0                        ; 0                ; 0                  ;
; current_state.go         ; 0                        ; 0                        ; 1                ; 1                  ;
; current_state.assert_eop ; 0                        ; 1                        ; 0                ; 1                  ;
; current_state.wait_state ; 1                        ; 0                        ; 0                ; 1                  ;
+--------------------------+--------------------------+--------------------------+------------------+--------------------+


Encoding Type:  One-Hot
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |block|T_control:inst46|current_state                                                                                                            ;
+-------------------------+-------------------------+----------------------+--------------------+------------------------+--------------------+--------------------+
; Name                    ; current_state.Pro_write ; current_state.source ; current_state.Wait ; current_state.Pro_read ; current_state.sink ; current_state.idle ;
+-------------------------+-------------------------+----------------------+--------------------+------------------------+--------------------+--------------------+
; current_state.idle      ; 0                       ; 0                    ; 0                  ; 0                      ; 0                  ; 0                  ;
; current_state.sink      ; 0                       ; 0                    ; 0                  ; 0                      ; 1                  ; 1                  ;
; current_state.Pro_read  ; 0                       ; 0                    ; 0                  ; 1                      ; 0                  ; 1                  ;
; current_state.Wait      ; 0                       ; 0                    ; 1                  ; 0                      ; 0                  ; 1                  ;
; current_state.source    ; 0                       ; 1                    ; 0                  ; 0                      ; 0                  ; 1                  ;
; current_state.Pro_write ; 1                       ; 0                    ; 0                  ; 0                      ; 0                  ; 1                  ;
+-------------------------+-------------------------+----------------------+--------------------+------------------------+--------------------+--------------------+


Encoding Type: Safe One-Hot
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state ;
+-----------+-----------+----------+----------+----------+----------+----------+----------+----------+----------+----------+------------------------------------------------------------------+
; Name      ; state.s10 ; state.s9 ; state.s8 ; state.s7 ; state.s6 ; state.s5 ; state.s4 ; state.s3 ; state.s2 ; state.s1 ; state.s0                                                         ;
+-----------+-----------+----------+----------+----------+----------+----------+----------+----------+----------+----------+------------------------------------------------------------------+
; state.s0  ; 0         ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0                                                                ;
; state.s1  ; 0         ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1        ; 1                                                                ;
; state.s2  ; 0         ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1        ; 0        ; 1                                                                ;
; state.s3  ; 0         ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1        ; 0        ; 0        ; 1                                                                ;
; state.s4  ; 0         ; 0        ; 0        ; 0        ; 0        ; 0        ; 1        ; 0        ; 0        ; 0        ; 1                                                                ;
; state.s5  ; 0         ; 0        ; 0        ; 0        ; 0        ; 1        ; 0        ; 0        ; 0        ; 0        ; 1                                                                ;
; state.s6  ; 0         ; 0        ; 0        ; 0        ; 1        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1                                                                ;
; state.s7  ; 0         ; 0        ; 0        ; 1        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1                                                                ;
; state.s8  ; 0         ; 0        ; 1        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1                                                                ;
; state.s9  ; 0         ; 1        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1                                                                ;
; state.s10 ; 1         ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1                                                                ;
+-----------+-----------+----------+----------+----------+----------+----------+----------+----------+----------+----------+------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                                                                                                                                                                                                                    ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                                                                                            ; Reason for Removal                                                                                                                                                                         ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor3|add_sub_i5j:auto_generated|pipeline_dffe[34]                                                      ; Lost fanout                                                                                                                                                                                ;
; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6|mult_add_ie81:auto_generated|dffe2a[34]                                                             ; Lost fanout                                                                                                                                                                                ;
; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor3|add_sub_i5j:auto_generated|pipeline_dffe[33]                                                      ; Lost fanout                                                                                                                                                                                ;
; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6|mult_add_ie81:auto_generated|dffe2a[33]                                                             ; Lost fanout                                                                                                                                                                                ;
; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor2|add_sub_5ji:auto_generated|pipeline_dffe[33..34]                                                  ; Lost fanout                                                                                                                                                                                ;
; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6|mult_add_ie81:auto_generated|dffe2a[35]                                                             ; Lost fanout                                                                                                                                                                                ;
; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add2|mult_add_dqa1:auto_generated|dffe2a[33]                                                             ; Lost fanout                                                                                                                                                                                ;
; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1|mult_add_dqa1:auto_generated|dffe2a[33]                                                             ; Lost fanout                                                                                                                                                                                ;
; p2s:inst28|cnt                                                                                                                                                                                                                           ; Merged with p2s:inst13|cnt                                                                                                                                                                 ;
; s2p:inst6|cnt                                                                                                                                                                                                                            ; Merged with s2p:inst7|cnt                                                                                                                                                                  ;
; butterfly:inst48|real_a[15]                                                                                                                                                                                                              ; Merged with butterfly:inst48|real_a[16]                                                                                                                                                    ;
; butterfly:inst48|imag_a[15]                                                                                                                                                                                                              ; Merged with butterfly:inst48|imag_a[16]                                                                                                                                                    ;
; butterfly:inst48|real_b[15]                                                                                                                                                                                                              ; Merged with butterfly:inst48|real_b[16]                                                                                                                                                    ;
; butterfly:inst48|imag_b[15]                                                                                                                                                                                                              ; Merged with butterfly:inst48|imag_b[16]                                                                                                                                                    ;
; butterfly:inst48|real_WN_in[15]                                                                                                                                                                                                          ; Merged with butterfly:inst48|real_WN_in[16]                                                                                                                                                ;
; butterfly:inst48|imag_WN_in[15]                                                                                                                                                                                                          ; Merged with butterfly:inst48|imag_WN_in[16]                                                                                                                                                ;
; s2p:inst6|count[6]                                                                                                                                                                                                                       ; Merged with s2p:inst7|count[6]                                                                                                                                                             ;
; s2p:inst6|count[5]                                                                                                                                                                                                                       ; Merged with s2p:inst7|count[5]                                                                                                                                                             ;
; s2p:inst6|count[4]                                                                                                                                                                                                                       ; Merged with s2p:inst7|count[4]                                                                                                                                                             ;
; s2p:inst6|count[3]                                                                                                                                                                                                                       ; Merged with s2p:inst7|count[3]                                                                                                                                                             ;
; s2p:inst6|count[2]                                                                                                                                                                                                                       ; Merged with s2p:inst7|count[2]                                                                                                                                                             ;
; s2p:inst6|count[1]                                                                                                                                                                                                                       ; Merged with s2p:inst7|count[1]                                                                                                                                                             ;
; s2p:inst6|count[0]                                                                                                                                                                                                                       ; Merged with s2p:inst7|count[0]                                                                                                                                                             ;
; p2s:inst13|data_temp[0][16]                                                                                                                                                                                                              ; Merged with p2s:inst13|data_temp[0][17]                                                                                                                                                    ;
; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder1|add_sub_5ii:auto_generated|pipeline_dffe[16]                                                           ; Merged with butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder1|add_sub_5ii:auto_generated|pipeline_dffe[17] ;
; p2s:inst28|data_temp[0][16]                                                                                                                                                                                                              ; Merged with p2s:inst28|data_temp[0][17]                                                                                                                                                    ;
; butterfly:inst48|current_state~15                                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                ;
; T_control:inst46|current_state~14                                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                ;
; T_control:inst46|current_state~15                                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                ;
; T_control:inst46|current_state~16                                                                                                                                                                                                        ; Lost fanout                                                                                                                                                                                ;
; ctrl_fft:inst3|current_state.assert_eop                                                                                                                                                                                                  ; Merged with ctrl_fft:inst3|sink_eop                                                                                                                                                        ;
; Total Number of Removed Registers = 32                                                                                                                                                                                                   ;                                                                                                                                                                                            ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_uti:auto_generated|current_reg_q_w[0] ; Stuck at GND due to stuck port data_in                                                                                                                                                     ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|xraddr[0]                                                                                                              ; Stuck at GND due to stuck port data_in                                                                                                                                                     ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][22]                                                                                                           ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][21]                                                                                                           ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][20]                                                                                                           ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][19]                                                                                                           ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][18]                                                                                                           ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][17]                                                                                                           ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][16]                                                                                                           ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][15]                                                                                                           ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][14]                                                                                                           ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][13]                                                                                                           ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][12]                                                                                                           ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][11]                                                                                                           ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][10]                                                                                                           ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][9]                                                                                                            ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][8]                                                                                                            ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][7]                                                                                                            ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][6]                                                                                                            ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][5]                                                                                                            ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][4]                                                                                                            ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][3]                                                                                                            ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][2]                                                                                                            ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][1]                                                                                                            ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][0]                                                                                                            ; Lost fanout                                                                                                                                                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[0]                                                                                                          ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[0]                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[1]                                                                                                          ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[1]                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[2]                                                                                                          ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[2]                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[3]                                                                                                          ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[3]                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[4]                                                                                                          ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[4]                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[5]                                                                                                          ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[5]                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[6]                                                                                                          ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[6]                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[7]                                                                                                          ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[7]                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[8]                                                                                                          ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[8]                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[9]                                                                                                          ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[9]                                                ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[10]                                                                                                         ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[10]                                               ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s2                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                     ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s3                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                     ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s4                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                     ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s5                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                     ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s6                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                     ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s7                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                     ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s8                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                     ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s9                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                                     ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s10                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                                     ;
; Total Number of Removed Registers = 45                                                                                                                                                                                                   ;                                                                                                                                                                                            ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                                                                                                                                                                                                                                                                                                                                          ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                                                                                            ; Reason for Removal        ; Registers Removed due to This Register                                                                                                                                        ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor2|add_sub_5ji:auto_generated|pipeline_dffe[34]                                                      ; Lost Fanouts              ; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add2|mult_add_dqa1:auto_generated|dffe2a[33], ;
;                                                                                                                                                                                                                                          ;                           ; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1|mult_add_dqa1:auto_generated|dffe2a[33]  ;
; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor3|add_sub_i5j:auto_generated|pipeline_dffe[34]                                                      ; Lost Fanouts              ; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6|mult_add_ie81:auto_generated|dffe2a[34]  ;
; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor3|add_sub_i5j:auto_generated|pipeline_dffe[33]                                                      ; Lost Fanouts              ; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6|mult_add_ie81:auto_generated|dffe2a[33]  ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_uti:auto_generated|current_reg_q_w[0] ; Stuck at GND              ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|xraddr[0],                                                  ;
;                                                                                                                                                                                                                                          ; due to stuck port data_in ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][22],                                               ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][21],                                               ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][20],                                               ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][19],                                               ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][18],                                               ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][17],                                               ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][16],                                               ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][15],                                               ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][14],                                               ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][13],                                               ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][12],                                               ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][11],                                               ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][10],                                               ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][9],                                                ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][8],                                                ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][7],                                                ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][6],                                                ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][5],                                                ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][4],                                                ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][3],                                                ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][2],                                                ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][1],                                                ;
;                                                                                                                                                                                                                                          ;                           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][0]                                                 ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by Synthesis                                                                                                                                                                                                                                                        ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; Register Name                                                                                                                                                           ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s1 ; no                                                               ; yes                                        ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s0 ; no                                                               ; yes                                        ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 1655  ;
; Number of registers using Synchronous Clear  ; 43    ;
; Number of registers using Synchronous Load   ; 11    ;
; Number of registers using Asynchronous Clear ; 834   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 591   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                                                      ;
+-----------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                                                       ; Fan out ;
+-----------------------------------------------------------------------------------------------------------------------------------------+---------+
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[5]  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[0]  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[6]  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[2]  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[10] ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[4]  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[8]  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[7]  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[11] ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[1]  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[9]  ; 1       ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[3]  ; 1       ;
; sld_hub:sld_hub_inst|hub_tdo_reg                                                                                                        ; 2       ;
; Total number of inverted registers = 13                                                                                                 ;         ;
+-----------------------------------------------------------------------------------------------------------------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                                                     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1                ; 32 bits   ; 64 LEs        ; 32 LEs               ; 32 LEs                 ; Yes        ; |block|s2p:inst6|data_temp[1][10]                                                                                                                                              ;
; 3:1                ; 60 bits   ; 120 LEs       ; 60 LEs               ; 60 LEs                 ; Yes        ; |block|p2s:inst13|data_temp[1][7]                                                                                                                                              ;
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |block|butterfly:inst48|cnt[7]                                                                                                                                                 ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |block|block_new:inst45|cnt[0]                                                                                                                                                 ;
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |block|s2p:inst7|count[5]                                                                                                                                                      ;
; 3:1                ; 32 bits   ; 64 LEs        ; 32 LEs               ; 32 LEs                 ; Yes        ; |block|s2p:inst6|data_temp[0][7]                                                                                                                                               ;
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |block|p2s:inst28|count[0]                                                                                                                                                     ;
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |block|p2s:inst13|count[3]                                                                                                                                                     ;
; 10:1               ; 6 bits    ; 36 LEs        ; 6 LEs                ; 30 LEs                 ; Yes        ; |block|T_control:inst46|cnt[6]                                                                                                                                                 ;
; 3:1                ; 18 bits   ; 36 LEs        ; 18 LEs               ; 18 LEs                 ; No         ; |block|T_control:inst46|Idata_in[0]                                                                                                                                            ;
; 3:1                ; 18 bits   ; 36 LEs        ; 36 LEs               ; 0 LEs                  ; No         ; |block|T_control:inst46|Rdata_in[9]                                                                                                                                            ;
; 4:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; No         ; |block|T_control:inst46|Realdata_out~42                                                                                                                                        ;
; 3:1                ; 32 bits   ; 64 LEs        ; 32 LEs               ; 32 LEs                 ; No         ; |block|T_control:inst46|rdata_out[9]                                                                                                                                           ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |block|block_new:inst45|next_state~3                                                                                                                                           ;
; 3:1                ; 18 bits   ; 36 LEs        ; 36 LEs               ; 0 LEs                  ; No         ; |block|p2s:inst13|data_out[1]                                                                                                                                                  ;
; 3:1                ; 18 bits   ; 36 LEs        ; 36 LEs               ; 0 LEs                  ; No         ; |block|p2s:inst28|data_out[0]                                                                                                                                                  ;
; 4:1                ; 12 bits   ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; Yes        ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[2]                                              ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|word_counter[3]                                                              ;
; 12:1               ; 4 bits    ; 32 LEs        ; 28 LEs               ; 4 LEs                  ; Yes        ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[1]                                                                   ;
; 3:1                ; 9 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; No         ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state~21 ;
; 3:1                ; 11 bits   ; 22 LEs        ; 11 LEs               ; 11 LEs                 ; No         ; |block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~12                                         ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |block|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1]                                                                                                                                ;
; 5:1                ; 5 bits    ; 15 LEs        ; 5 LEs                ; 10 LEs                 ; Yes        ; |block|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]                                                                                                            ;
; 20:1               ; 4 bits    ; 52 LEs        ; 36 LEs               ; 16 LEs                 ; Yes        ; |block|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]                                                                                                                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Source assignments for T_control:inst46|lpm_ram_dq0:ram1|altsyncram:altsyncram_component|altsyncram_n4a1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                        ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                         ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Source assignments for T_control:inst46|lpm_ram_dq0:ram2|altsyncram:altsyncram_component|altsyncram_n4a1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                        ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                         ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|dpram_fv01:FIFOram|altsyncram_avj1:altsyncram1 ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                               ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1|mult_add_dqa1:auto_generated|ded_mult_1t51:ded_mult1|dffpipe_b3c:pre_result ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                     ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                      ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add2|mult_add_dqa1:auto_generated|ded_mult_1t51:ded_mult1|dffpipe_b3c:pre_result ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                     ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                      ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6|mult_add_ie81:auto_generated|ded_mult_2a21:ded_mult1|dffpipe_d3c:pre_result ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                                                     ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                                      ;
+---------------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------+
; Source assignments for lpm_rom1:inst2|altsyncram:altsyncram_component|altsyncram_qq71:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------+
; Assignment                      ; Value              ; From ; To                                     ;
+---------------------------------+--------------------+------+----------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                      ;
+---------------------------------+--------------------+------+----------------------------------------+


+------------------------------------------------------------------------------------------------------+
; Source assignments for lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_oh91:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------+
; Assignment                      ; Value              ; From ; To                                     ;
+---------------------------------+--------------------+------+----------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                      ;
+---------------------------------+--------------------+------+----------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for lpm_fifo0:inst|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|dpram_fv01:FIFOram|altsyncram_avj1:altsyncram1 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                             ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                              ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------+
; Source assignments for lpm_rom2:inst19|altsyncram:altsyncram_component|altsyncram_kfa1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------+
; Assignment                      ; Value              ; From ; To                                      ;
+---------------------------------+--------------------+------+-----------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                       ;
+---------------------------------+--------------------+------+-----------------------------------------+


+-----------------------------------------------------------------------------+
; Source assignments for lpm_counter0:inst4|lpm_counter:lpm_counter_component ;
+---------------------------+-------+------+----------------------------------+
; Assignment                ; Value ; From ; To                               ;
+---------------------------+-------+------+----------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                ;
+---------------------------+-------+------+----------------------------------+


+---------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body ;
+---------------------------------+-------+------+--------------------------------------------+
; Assignment                      ; Value ; From ; To                                         ;
+---------------------------------+-------+------+--------------------------------------------+
; NOT_GATE_PUSH_BACK              ; OFF   ; -    ; -                                          ;
; POWER_UP_LEVEL                  ; LOW   ; -    ; -                                          ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                          ;
+---------------------------------+-------+------+--------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity ;
+--------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment         ; Value ; From ; To                                                                                                                                                ;
+--------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; SAFE_STATE_MACHINE ; on    ; -    ; state                                                                                                                                             ;
+--------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_i7p3:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                           ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                            ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_i7p3:auto_generated|altsyncram_ugq1:altsyncram1 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                       ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                        ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                                                                                                                                          ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                                                                                                                           ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                                                                                                                           ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                                                                                                                           ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter ;
+---------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                                                                                                                 ;
+---------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                                                                                                  ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                                                                                                  ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                                                                                                  ;
+---------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter ;
+---------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                                                                                                                           ;
+---------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                                                                                                            ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                                                                                                            ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                                                                                                            ;
+---------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                ; Value ; From ; To                                                                                                                                                                        ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                                                                                                         ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                                                                                                         ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                                                                                                         ;
+---------------------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr ;
+----------------------+-------+------+-----------------------------------------------------------------------------+
; Assignment           ; Value ; From ; To                                                                          ;
+----------------------+-------+------+-----------------------------------------------------------------------------+
; AUTO_ROM_RECOGNITION ; OFF   ; -    ; -                                                                           ;
+----------------------+-------+------+-----------------------------------------------------------------------------+


+----------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst              ;
+------------------------------+-------+------+------------+
; Assignment                   ; Value ; From ; To         ;
+------------------------------+-------+------+------------+
; IGNORE_LCELL_BUFFERS         ; OFF   ; -    ; -          ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF   ; -    ; -          ;
; NOT_GATE_PUSH_BACK           ; OFF   ; -    ; CLR_SIGNAL ;
; POWER_UP_LEVEL               ; LOW   ; -    ; CLR_SIGNAL ;
+------------------------------+-------+------+------------+


+---------------------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG ;
+----------------------+-------+------+-------------------------------+
; Assignment           ; Value ; From ; To                            ;
+----------------------+-------+------+-------------------------------+
; AUTO_ROM_RECOGNITION ; OFF   ; -    ; -                             ;
+----------------------+-------+------+-------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component|add_sub_vmg:auto_generated|altshift_taps:pipeline_dffe_rtl_0|shift_taps_5hp:auto_generated|altsyncram_hg31:altsyncram4 ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                 ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                  ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------+
; Parameter Settings for User Entity Instance: T_control:inst46 ;
+----------------+------------+---------------------------------+
; Parameter Name ; Value      ; Type                            ;
+----------------+------------+---------------------------------+
; level_total    ; 0110       ; Unsigned Binary                 ;
; idle           ; 000        ; Unsigned Binary                 ;
; sink           ; 001        ; Unsigned Binary                 ;
; Pro_read       ; 011        ; Unsigned Binary                 ;
; Pro_write      ; 111        ; Unsigned Binary                 ;
; source         ; 110        ; Unsigned Binary                 ;
; Wait           ; 101        ; Unsigned Binary                 ;
; scale          ; 0001000000 ; Unsigned Binary                 ;
+----------------+------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: T_control:inst46|lpm_ram_dq0:ram1|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+----------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                               ;
+------------------------------------+----------------------+----------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                            ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                         ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                       ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                       ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                     ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                            ;
; OPERATION_MODE                     ; SINGLE_PORT          ; Untyped                                            ;
; WIDTH_A                            ; 18                   ; Signed Integer                                     ;
; WIDTHAD_A                          ; 6                    ; Signed Integer                                     ;
; NUMWORDS_A                         ; 64                   ; Signed Integer                                     ;
; OUTDATA_REG_A                      ; CLOCK0               ; Untyped                                            ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                            ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                            ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                            ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                            ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                            ;
; WIDTH_B                            ; 1                    ; Untyped                                            ;
; WIDTHAD_B                          ; 1                    ; Untyped                                            ;
; NUMWORDS_B                         ; 1                    ; Untyped                                            ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                            ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                            ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                            ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                                            ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                            ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                            ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                            ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                            ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                            ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                            ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                            ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                            ;
; WIDTH_BYTEENA_A                    ; 1                    ; Signed Integer                                     ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                            ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                            ;
; BYTE_SIZE                          ; 8                    ; Untyped                                            ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                            ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                            ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                            ;
; INIT_FILE                          ; UNUSED               ; Untyped                                            ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                            ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                            ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS               ; Untyped                                            ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                            ;
; CLOCK_ENABLE_OUTPUT_A              ; BYPASS               ; Untyped                                            ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                            ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                            ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                            ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                            ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                            ;
; CBXI_PARAMETER                     ; altsyncram_n4a1      ; Untyped                                            ;
+------------------------------------+----------------------+----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: T_control:inst46|lpm_ram_dq0:ram2|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+----------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                               ;
+------------------------------------+----------------------+----------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                            ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                         ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                       ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                       ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                     ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                                            ;
; OPERATION_MODE                     ; SINGLE_PORT          ; Untyped                                            ;
; WIDTH_A                            ; 18                   ; Signed Integer                                     ;
; WIDTHAD_A                          ; 6                    ; Signed Integer                                     ;
; NUMWORDS_A                         ; 64                   ; Signed Integer                                     ;
; OUTDATA_REG_A                      ; CLOCK0               ; Untyped                                            ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                            ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                            ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                            ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                            ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                            ;
; WIDTH_B                            ; 1                    ; Untyped                                            ;
; WIDTHAD_B                          ; 1                    ; Untyped                                            ;
; NUMWORDS_B                         ; 1                    ; Untyped                                            ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                            ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                            ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                            ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                                            ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                            ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                            ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                            ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                            ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                            ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                            ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                            ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                            ;
; WIDTH_BYTEENA_A                    ; 1                    ; Signed Integer                                     ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                            ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                            ;
; BYTE_SIZE                          ; 8                    ; Untyped                                            ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                            ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                            ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                            ;
; INIT_FILE                          ; UNUSED               ; Untyped                                            ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                            ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                            ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS               ; Untyped                                            ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                            ;
; CLOCK_ENABLE_OUTPUT_A              ; BYPASS               ; Untyped                                            ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                            ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                            ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                            ;
; ENABLE_ECC                         ; FALSE                ; Untyped                                            ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                            ;
; CBXI_PARAMETER                     ; altsyncram_n4a1      ; Untyped                                            ;
+------------------------------------+----------------------+----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------+
; Parameter Settings for User Entity Instance: reset_ctrl:inst5 ;
+----------------+-------+--------------------------------------+
; Parameter Name ; Value ; Type                                 ;
+----------------+-------+--------------------------------------+
; const          ; 2     ; Untyped                              ;
+----------------+-------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_fifo0:inst24|scfifo:scfifo_component ;
+-------------------------+-------------+-----------------------------------------------+
; Parameter Name          ; Value       ; Type                                          ;
+-------------------------+-------------+-----------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                    ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                  ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                  ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                ;
; lpm_width               ; 18          ; Signed Integer                                ;
; LPM_NUMWORDS            ; 64          ; Signed Integer                                ;
; LPM_WIDTHU              ; 6           ; Signed Integer                                ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                       ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                       ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                       ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                       ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                       ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                       ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                       ;
; USE_EAB                 ; ON          ; Untyped                                       ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                       ;
; DEVICE_FAMILY           ; Cyclone II  ; Untyped                                       ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                       ;
; CBXI_PARAMETER          ; scfifo_7r31 ; Untyped                                       ;
+-------------------------+-------------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------+
; Parameter Settings for User Entity Instance: p2s:inst28 ;
+----------------+---------+------------------------------+
; Parameter Name ; Value   ; Type                         ;
+----------------+---------+------------------------------+
; scale          ; 1000000 ; Unsigned Binary              ;
+----------------+---------+------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------+
; Parameter Settings for User Entity Instance: butterfly:inst48 ;
+----------------+----------+-----------------------------------+
; Parameter Name ; Value    ; Type                              ;
+----------------+----------+-----------------------------------+
; scale          ; 01000000 ; Unsigned Binary                   ;
; idle           ; 00       ; Unsigned Binary                   ;
; work           ; 01       ; Unsigned Binary                   ;
+----------------+----------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component ;
+------------------------+-------------+--------------------------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                                     ;
+------------------------+-------------+--------------------------------------------------------------------------+
; LPM_WIDTH              ; 17          ; Signed Integer                                                           ;
; LPM_REPRESENTATION     ; SIGNED      ; Untyped                                                                  ;
; LPM_DIRECTION          ; ADD         ; Untyped                                                                  ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                                                  ;
; LPM_PIPELINE           ; 4           ; Signed Integer                                                           ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                                                  ;
; REGISTERED_AT_END      ; 0           ; Untyped                                                                  ;
; OPTIMIZE_FOR_SPEED     ; 5           ; Untyped                                                                  ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                                                  ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                  ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                       ;
; DEVICE_FAMILY          ; Cyclone II  ; Untyped                                                                  ;
; USE_WYS                ; OFF         ; Untyped                                                                  ;
; STYLE                  ; FAST        ; Untyped                                                                  ;
; CBXI_PARAMETER         ; add_sub_vmg ; Untyped                                                                  ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                               ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                             ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                             ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                           ;
+------------------------+-------------+--------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: butterfly:inst48|ADD_17:add_imag|lpm_add_sub:lpm_add_sub_component ;
+------------------------+-------------+--------------------------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                                     ;
+------------------------+-------------+--------------------------------------------------------------------------+
; LPM_WIDTH              ; 17          ; Signed Integer                                                           ;
; LPM_REPRESENTATION     ; SIGNED      ; Untyped                                                                  ;
; LPM_DIRECTION          ; ADD         ; Untyped                                                                  ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                                                  ;
; LPM_PIPELINE           ; 4           ; Signed Integer                                                           ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                                                  ;
; REGISTERED_AT_END      ; 0           ; Untyped                                                                  ;
; OPTIMIZE_FOR_SPEED     ; 5           ; Untyped                                                                  ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                                                  ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                  ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                       ;
; DEVICE_FAMILY          ; Cyclone II  ; Untyped                                                                  ;
; USE_WYS                ; OFF         ; Untyped                                                                  ;
; STYLE                  ; FAST        ; Untyped                                                                  ;
; CBXI_PARAMETER         ; add_sub_vmg ; Untyped                                                                  ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                               ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                             ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                             ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                           ;
+------------------------+-------------+--------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component ;
+------------------------+-------------+--------------------------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                                     ;
+------------------------+-------------+--------------------------------------------------------------------------+
; LPM_WIDTH              ; 17          ; Signed Integer                                                           ;
; LPM_REPRESENTATION     ; SIGNED      ; Untyped                                                                  ;
; LPM_DIRECTION          ; SUB         ; Untyped                                                                  ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                                                  ;
; LPM_PIPELINE           ; 0           ; Untyped                                                                  ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                                                  ;
; REGISTERED_AT_END      ; 0           ; Untyped                                                                  ;
; OPTIMIZE_FOR_SPEED     ; 5           ; Untyped                                                                  ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                                                  ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                  ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                       ;
; DEVICE_FAMILY          ; Cyclone II  ; Untyped                                                                  ;
; USE_WYS                ; OFF         ; Untyped                                                                  ;
; STYLE                  ; FAST        ; Untyped                                                                  ;
; CBXI_PARAMETER         ; add_sub_4qe ; Untyped                                                                  ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                               ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                             ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                             ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                           ;
+------------------------+-------------+--------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: butterfly:inst48|SUB_17:sub_imag|lpm_add_sub:lpm_add_sub_component ;
+------------------------+-------------+--------------------------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                                     ;
+------------------------+-------------+--------------------------------------------------------------------------+
; LPM_WIDTH              ; 17          ; Signed Integer                                                           ;
; LPM_REPRESENTATION     ; SIGNED      ; Untyped                                                                  ;
; LPM_DIRECTION          ; SUB         ; Untyped                                                                  ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                                                  ;
; LPM_PIPELINE           ; 0           ; Untyped                                                                  ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                                                  ;
; REGISTERED_AT_END      ; 0           ; Untyped                                                                  ;
; OPTIMIZE_FOR_SPEED     ; 5           ; Untyped                                                                  ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                                                  ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                  ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                       ;
; DEVICE_FAMILY          ; Cyclone II  ; Untyped                                                                  ;
; USE_WYS                ; OFF         ; Untyped                                                                  ;
; STYLE                  ; FAST        ; Untyped                                                                  ;
; CBXI_PARAMETER         ; add_sub_4qe ; Untyped                                                                  ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                               ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                             ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                             ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                           ;
+------------------------+-------------+--------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1 ;
+---------------------------------------+-------------------+-----------------------------------------------------------------------------------------------------------------------+
; Parameter Name                        ; Value             ; Type                                                                                                                  ;
+---------------------------------------+-------------------+-----------------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                     ; ON                ; AUTO_CARRY                                                                                                            ;
; IGNORE_CARRY_BUFFERS                  ; OFF               ; IGNORE_CARRY                                                                                                          ;
; AUTO_CASCADE_CHAINS                   ; ON                ; AUTO_CASCADE                                                                                                          ;
; IGNORE_CASCADE_BUFFERS                ; OFF               ; IGNORE_CASCADE                                                                                                        ;
; ACCUM_DIRECTION                       ; ADD               ; Untyped                                                                                                               ;
; ACCUM_SLOAD_ACLR                      ; ACLR3             ; Untyped                                                                                                               ;
; ACCUM_SLOAD_PIPELINE_ACLR             ; ACLR3             ; Untyped                                                                                                               ;
; ACCUM_SLOAD_PIPELINE_REGISTER         ; CLOCK0            ; Untyped                                                                                                               ;
; ACCUM_SLOAD_REGISTER                  ; CLOCK0            ; Untyped                                                                                                               ;
; ACCUMULATOR                           ; NO                ; Untyped                                                                                                               ;
; ADDER1_ROUNDING                       ; NO                ; Untyped                                                                                                               ;
; ADDER3_ROUNDING                       ; NO                ; Untyped                                                                                                               ;
; ADDNSUB1_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB1_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB1_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB1_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB3_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB3_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB3_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB3_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_ACLR1              ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_ACLR3              ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR1     ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR3     ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_REGISTER1          ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_REGISTER3          ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_ACLR                         ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_ADDER                        ; NO                ; Untyped                                                                                                               ;
; CHAINOUT_REGISTER                     ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_ROUND_OUTPUT_ACLR            ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_ROUND_OUTPUT_REGISTER        ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_ROUNDING                     ; NO                ; Untyped                                                                                                               ;
; CHAINOUT_SATURATE_ACLR                ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_SATURATE_OUTPUT_ACLR         ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_SATURATE_OUTPUT_REGISTER     ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_SATURATE_PIPELINE_ACLR       ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_SATURATE_PIPELINE_REGISTER   ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_SATURATE_REGISTER            ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_SATURATION                   ; NO                ; Untyped                                                                                                               ;
; DEDICATED_MULTIPLIER_CIRCUITRY        ; AUTO              ; Untyped                                                                                                               ;
; DSP_BLOCK_BALANCING                   ; AUTO              ; Untyped                                                                                                               ;
; EXTRA_LATENCY                         ; 0                 ; Untyped                                                                                                               ;
; INPUT_ACLR_A0                         ; ACLR0             ; Untyped                                                                                                               ;
; INPUT_ACLR_A1                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_ACLR_A2                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_ACLR_A3                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_ACLR_B0                         ; ACLR0             ; Untyped                                                                                                               ;
; INPUT_ACLR_B1                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_ACLR_B2                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_ACLR_B3                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_REGISTER_A0                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_A1                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_A2                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_A3                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_B0                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_B1                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_B2                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_B3                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_SOURCE_A0                       ; DATAA             ; Untyped                                                                                                               ;
; INPUT_SOURCE_A1                       ; DATAA             ; Untyped                                                                                                               ;
; INPUT_SOURCE_A2                       ; DATAA             ; Untyped                                                                                                               ;
; INPUT_SOURCE_A3                       ; DATAA             ; Untyped                                                                                                               ;
; INPUT_SOURCE_B0                       ; DATAB             ; Untyped                                                                                                               ;
; INPUT_SOURCE_B1                       ; DATAB             ; Untyped                                                                                                               ;
; INPUT_SOURCE_B2                       ; DATAB             ; Untyped                                                                                                               ;
; INPUT_SOURCE_B3                       ; DATAB             ; Untyped                                                                                                               ;
; MULT01_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                                                               ;
; MULT01_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                                                               ;
; MULT01_SATURATION_ACLR                ; ACLR2             ; Untyped                                                                                                               ;
; MULT01_SATURATION_REGISTER            ; CLOCK0            ; Untyped                                                                                                               ;
; MULT23_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                                                               ;
; MULT23_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                                                               ;
; MULT23_SATURATION_ACLR                ; ACLR3             ; Untyped                                                                                                               ;
; MULT23_SATURATION_REGISTER            ; CLOCK0            ; Untyped                                                                                                               ;
; MULTIPLIER01_ROUNDING                 ; NO                ; Untyped                                                                                                               ;
; MULTIPLIER01_SATURATION               ; NO                ; Untyped                                                                                                               ;
; MULTIPLIER1_DIRECTION                 ; ADD               ; Untyped                                                                                                               ;
; MULTIPLIER23_ROUNDING                 ; NO                ; Untyped                                                                                                               ;
; MULTIPLIER23_SATURATION               ; NO                ; Untyped                                                                                                               ;
; MULTIPLIER3_DIRECTION                 ; ADD               ; Untyped                                                                                                               ;
; MULTIPLIER_ACLR0                      ; ACLR3             ; Untyped                                                                                                               ;
; MULTIPLIER_ACLR1                      ; ACLR3             ; Untyped                                                                                                               ;
; MULTIPLIER_ACLR2                      ; ACLR3             ; Untyped                                                                                                               ;
; MULTIPLIER_ACLR3                      ; ACLR3             ; Untyped                                                                                                               ;
; MULTIPLIER_REGISTER0                  ; UNREGISTERED      ; Untyped                                                                                                               ;
; MULTIPLIER_REGISTER1                  ; CLOCK0            ; Untyped                                                                                                               ;
; MULTIPLIER_REGISTER2                  ; CLOCK0            ; Untyped                                                                                                               ;
; MULTIPLIER_REGISTER3                  ; CLOCK0            ; Untyped                                                                                                               ;
; NUMBER_OF_MULTIPLIERS                 ; 1                 ; Signed Integer                                                                                                        ;
; OUTPUT_ACLR                           ; ACLR0             ; Untyped                                                                                                               ;
; OUTPUT_REGISTER                       ; CLOCK0            ; Untyped                                                                                                               ;
; OUTPUT_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                                                               ;
; OUTPUT_ROUND_PIPELINE_ACLR            ; ACLR3             ; Untyped                                                                                                               ;
; OUTPUT_ROUND_PIPELINE_REGISTER        ; CLOCK0            ; Untyped                                                                                                               ;
; OUTPUT_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                                                               ;
; OUTPUT_ROUND_TYPE                     ; NEAREST_INTEGER   ; Untyped                                                                                                               ;
; OUTPUT_ROUNDING                       ; NO                ; Untyped                                                                                                               ;
; OUTPUT_SATURATE_ACLR                  ; ACLR3             ; Untyped                                                                                                               ;
; OUTPUT_SATURATE_PIPELINE_ACLR         ; ACLR3             ; Untyped                                                                                                               ;
; OUTPUT_SATURATE_PIPELINE_REGISTER     ; CLOCK0            ; Untyped                                                                                                               ;
; OUTPUT_SATURATE_REGISTER              ; CLOCK0            ; Untyped                                                                                                               ;
; OUTPUT_SATURATE_TYPE                  ; ASYMMETRIC        ; Untyped                                                                                                               ;
; OUTPUT_SATURATION                     ; NO                ; Untyped                                                                                                               ;
; port_addnsub1                         ; PORT_CONNECTIVITY ; Untyped                                                                                                               ;
; port_addnsub3                         ; PORT_CONNECTIVITY ; Untyped                                                                                                               ;
; PORT_CHAINOUT_SAT_IS_OVERFLOW         ; PORT_UNUSED       ; Untyped                                                                                                               ;
; PORT_MULT0_IS_SATURATED               ; UNUSED            ; Untyped                                                                                                               ;
; PORT_MULT1_IS_SATURATED               ; UNUSED            ; Untyped                                                                                                               ;
; PORT_MULT2_IS_SATURATED               ; UNUSED            ; Untyped                                                                                                               ;
; PORT_MULT3_IS_SATURATED               ; UNUSED            ; Untyped                                                                                                               ;
; PORT_OUTPUT_IS_OVERFLOW               ; PORT_UNUSED       ; Untyped                                                                                                               ;
; port_signa                            ; PORT_CONNECTIVITY ; Untyped                                                                                                               ;
; port_signb                            ; PORT_CONNECTIVITY ; Untyped                                                                                                               ;
; REPRESENTATION_A                      ; SIGNED            ; Untyped                                                                                                               ;
; REPRESENTATION_B                      ; SIGNED            ; Untyped                                                                                                               ;
; ROTATE_ACLR                           ; ACLR3             ; Untyped                                                                                                               ;
; ROTATE_OUTPUT_ACLR                    ; ACLR3             ; Untyped                                                                                                               ;
; ROTATE_OUTPUT_REGISTER                ; CLOCK0            ; Untyped                                                                                                               ;
; ROTATE_PIPELINE_ACLR                  ; ACLR3             ; Untyped                                                                                                               ;
; ROTATE_PIPELINE_REGISTER              ; CLOCK0            ; Untyped                                                                                                               ;
; ROTATE_REGISTER                       ; CLOCK0            ; Untyped                                                                                                               ;
; WIDTH_MSB                             ; 17                ; Untyped                                                                                                               ;
; WIDTH_SATURATE_SIGN                   ; 1                 ; Untyped                                                                                                               ;
; SCANOUTA_ACLR                         ; ACLR3             ; Untyped                                                                                                               ;
; SCANOUTA_REGISTER                     ; UNREGISTERED      ; Untyped                                                                                                               ;
; SHIFT_MODE                            ; NO                ; Untyped                                                                                                               ;
; SHIFT_RIGHT_ACLR                      ; ACLR3             ; Untyped                                                                                                               ;
; SHIFT_RIGHT_OUTPUT_ACLR               ; ACLR3             ; Untyped                                                                                                               ;
; SHIFT_RIGHT_OUTPUT_REGISTER           ; CLOCK0            ; Untyped                                                                                                               ;
; SHIFT_RIGHT_PIPELINE_ACLR             ; ACLR3             ; Untyped                                                                                                               ;
; SHIFT_RIGHT_PIPELINE_REGISTER         ; CLOCK0            ; Untyped                                                                                                               ;
; SHIFT_RIGHT_REGISTER                  ; CLOCK0            ; Untyped                                                                                                               ;
; SIGNED_ACLR_A                         ; ACLR3             ; Untyped                                                                                                               ;
; SIGNED_ACLR_B                         ; ACLR3             ; Untyped                                                                                                               ;
; SIGNED_PIPELINE_ACLR_A                ; ACLR3             ; Untyped                                                                                                               ;
; SIGNED_PIPELINE_ACLR_B                ; ACLR3             ; Untyped                                                                                                               ;
; SIGNED_PIPELINE_REGISTER_A            ; CLOCK0            ; Untyped                                                                                                               ;
; SIGNED_PIPELINE_REGISTER_B            ; CLOCK0            ; Untyped                                                                                                               ;
; SIGNED_REGISTER_A                     ; CLOCK0            ; Untyped                                                                                                               ;
; SIGNED_REGISTER_B                     ; CLOCK0            ; Untyped                                                                                                               ;
; WIDTH_A                               ; 17                ; Signed Integer                                                                                                        ;
; WIDTH_B                               ; 17                ; Signed Integer                                                                                                        ;
; WIDTH_CHAININ                         ; 1                 ; Untyped                                                                                                               ;
; WIDTH_RESULT                          ; 34                ; Signed Integer                                                                                                        ;
; ZERO_CHAINOUT_OUTPUT_ACLR             ; ACLR3             ; Untyped                                                                                                               ;
; ZERO_CHAINOUT_OUTPUT_REGISTER         ; CLOCK0            ; Untyped                                                                                                               ;
; ZERO_LOOPBACK_ACLR                    ; ACLR3             ; Untyped                                                                                                               ;
; ZERO_LOOPBACK_OUTPUT_ACLR             ; ACLR3             ; Untyped                                                                                                               ;
; ZERO_LOOPBACK_OUTPUT_REGISTER         ; CLOCK0            ; Untyped                                                                                                               ;
; ZERO_LOOPBACK_PIPELINE_ACLR           ; ACLR3             ; Untyped                                                                                                               ;
; ZERO_LOOPBACK_PIPELINE_REGISTER       ; CLOCK0            ; Untyped                                                                                                               ;
; ZERO_LOOPBACK_REGISTER                ; CLOCK0            ; Untyped                                                                                                               ;
; CBXI_PARAMETER                        ; mult_add_dqa1     ; Untyped                                                                                                               ;
; DEVICE_FAMILY                         ; Cyclone II        ; Untyped                                                                                                               ;
+---------------------------------------+-------------------+-----------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add2 ;
+---------------------------------------+-------------------+-----------------------------------------------------------------------------------------------------------------------+
; Parameter Name                        ; Value             ; Type                                                                                                                  ;
+---------------------------------------+-------------------+-----------------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                     ; ON                ; AUTO_CARRY                                                                                                            ;
; IGNORE_CARRY_BUFFERS                  ; OFF               ; IGNORE_CARRY                                                                                                          ;
; AUTO_CASCADE_CHAINS                   ; ON                ; AUTO_CASCADE                                                                                                          ;
; IGNORE_CASCADE_BUFFERS                ; OFF               ; IGNORE_CASCADE                                                                                                        ;
; ACCUM_DIRECTION                       ; ADD               ; Untyped                                                                                                               ;
; ACCUM_SLOAD_ACLR                      ; ACLR3             ; Untyped                                                                                                               ;
; ACCUM_SLOAD_PIPELINE_ACLR             ; ACLR3             ; Untyped                                                                                                               ;
; ACCUM_SLOAD_PIPELINE_REGISTER         ; CLOCK0            ; Untyped                                                                                                               ;
; ACCUM_SLOAD_REGISTER                  ; CLOCK0            ; Untyped                                                                                                               ;
; ACCUMULATOR                           ; NO                ; Untyped                                                                                                               ;
; ADDER1_ROUNDING                       ; NO                ; Untyped                                                                                                               ;
; ADDER3_ROUNDING                       ; NO                ; Untyped                                                                                                               ;
; ADDNSUB1_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB1_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB1_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB1_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB3_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB3_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB3_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB3_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_ACLR1              ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_ACLR3              ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR1     ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR3     ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_REGISTER1          ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_REGISTER3          ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_ACLR                         ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_ADDER                        ; NO                ; Untyped                                                                                                               ;
; CHAINOUT_REGISTER                     ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_ROUND_OUTPUT_ACLR            ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_ROUND_OUTPUT_REGISTER        ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_ROUNDING                     ; NO                ; Untyped                                                                                                               ;
; CHAINOUT_SATURATE_ACLR                ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_SATURATE_OUTPUT_ACLR         ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_SATURATE_OUTPUT_REGISTER     ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_SATURATE_PIPELINE_ACLR       ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_SATURATE_PIPELINE_REGISTER   ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_SATURATE_REGISTER            ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_SATURATION                   ; NO                ; Untyped                                                                                                               ;
; DEDICATED_MULTIPLIER_CIRCUITRY        ; AUTO              ; Untyped                                                                                                               ;
; DSP_BLOCK_BALANCING                   ; AUTO              ; Untyped                                                                                                               ;
; EXTRA_LATENCY                         ; 0                 ; Untyped                                                                                                               ;
; INPUT_ACLR_A0                         ; ACLR0             ; Untyped                                                                                                               ;
; INPUT_ACLR_A1                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_ACLR_A2                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_ACLR_A3                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_ACLR_B0                         ; ACLR0             ; Untyped                                                                                                               ;
; INPUT_ACLR_B1                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_ACLR_B2                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_ACLR_B3                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_REGISTER_A0                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_A1                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_A2                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_A3                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_B0                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_B1                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_B2                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_B3                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_SOURCE_A0                       ; DATAA             ; Untyped                                                                                                               ;
; INPUT_SOURCE_A1                       ; DATAA             ; Untyped                                                                                                               ;
; INPUT_SOURCE_A2                       ; DATAA             ; Untyped                                                                                                               ;
; INPUT_SOURCE_A3                       ; DATAA             ; Untyped                                                                                                               ;
; INPUT_SOURCE_B0                       ; DATAB             ; Untyped                                                                                                               ;
; INPUT_SOURCE_B1                       ; DATAB             ; Untyped                                                                                                               ;
; INPUT_SOURCE_B2                       ; DATAB             ; Untyped                                                                                                               ;
; INPUT_SOURCE_B3                       ; DATAB             ; Untyped                                                                                                               ;
; MULT01_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                                                               ;
; MULT01_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                                                               ;
; MULT01_SATURATION_ACLR                ; ACLR2             ; Untyped                                                                                                               ;
; MULT01_SATURATION_REGISTER            ; CLOCK0            ; Untyped                                                                                                               ;
; MULT23_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                                                               ;
; MULT23_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                                                               ;
; MULT23_SATURATION_ACLR                ; ACLR3             ; Untyped                                                                                                               ;
; MULT23_SATURATION_REGISTER            ; CLOCK0            ; Untyped                                                                                                               ;
; MULTIPLIER01_ROUNDING                 ; NO                ; Untyped                                                                                                               ;
; MULTIPLIER01_SATURATION               ; NO                ; Untyped                                                                                                               ;
; MULTIPLIER1_DIRECTION                 ; ADD               ; Untyped                                                                                                               ;
; MULTIPLIER23_ROUNDING                 ; NO                ; Untyped                                                                                                               ;
; MULTIPLIER23_SATURATION               ; NO                ; Untyped                                                                                                               ;
; MULTIPLIER3_DIRECTION                 ; ADD               ; Untyped                                                                                                               ;
; MULTIPLIER_ACLR0                      ; ACLR3             ; Untyped                                                                                                               ;
; MULTIPLIER_ACLR1                      ; ACLR3             ; Untyped                                                                                                               ;
; MULTIPLIER_ACLR2                      ; ACLR3             ; Untyped                                                                                                               ;
; MULTIPLIER_ACLR3                      ; ACLR3             ; Untyped                                                                                                               ;
; MULTIPLIER_REGISTER0                  ; UNREGISTERED      ; Untyped                                                                                                               ;
; MULTIPLIER_REGISTER1                  ; CLOCK0            ; Untyped                                                                                                               ;
; MULTIPLIER_REGISTER2                  ; CLOCK0            ; Untyped                                                                                                               ;
; MULTIPLIER_REGISTER3                  ; CLOCK0            ; Untyped                                                                                                               ;
; NUMBER_OF_MULTIPLIERS                 ; 1                 ; Signed Integer                                                                                                        ;
; OUTPUT_ACLR                           ; ACLR0             ; Untyped                                                                                                               ;
; OUTPUT_REGISTER                       ; CLOCK0            ; Untyped                                                                                                               ;
; OUTPUT_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                                                               ;
; OUTPUT_ROUND_PIPELINE_ACLR            ; ACLR3             ; Untyped                                                                                                               ;
; OUTPUT_ROUND_PIPELINE_REGISTER        ; CLOCK0            ; Untyped                                                                                                               ;
; OUTPUT_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                                                               ;
; OUTPUT_ROUND_TYPE                     ; NEAREST_INTEGER   ; Untyped                                                                                                               ;
; OUTPUT_ROUNDING                       ; NO                ; Untyped                                                                                                               ;
; OUTPUT_SATURATE_ACLR                  ; ACLR3             ; Untyped                                                                                                               ;
; OUTPUT_SATURATE_PIPELINE_ACLR         ; ACLR3             ; Untyped                                                                                                               ;
; OUTPUT_SATURATE_PIPELINE_REGISTER     ; CLOCK0            ; Untyped                                                                                                               ;
; OUTPUT_SATURATE_REGISTER              ; CLOCK0            ; Untyped                                                                                                               ;
; OUTPUT_SATURATE_TYPE                  ; ASYMMETRIC        ; Untyped                                                                                                               ;
; OUTPUT_SATURATION                     ; NO                ; Untyped                                                                                                               ;
; port_addnsub1                         ; PORT_CONNECTIVITY ; Untyped                                                                                                               ;
; port_addnsub3                         ; PORT_CONNECTIVITY ; Untyped                                                                                                               ;
; PORT_CHAINOUT_SAT_IS_OVERFLOW         ; PORT_UNUSED       ; Untyped                                                                                                               ;
; PORT_MULT0_IS_SATURATED               ; UNUSED            ; Untyped                                                                                                               ;
; PORT_MULT1_IS_SATURATED               ; UNUSED            ; Untyped                                                                                                               ;
; PORT_MULT2_IS_SATURATED               ; UNUSED            ; Untyped                                                                                                               ;
; PORT_MULT3_IS_SATURATED               ; UNUSED            ; Untyped                                                                                                               ;
; PORT_OUTPUT_IS_OVERFLOW               ; PORT_UNUSED       ; Untyped                                                                                                               ;
; port_signa                            ; PORT_CONNECTIVITY ; Untyped                                                                                                               ;
; port_signb                            ; PORT_CONNECTIVITY ; Untyped                                                                                                               ;
; REPRESENTATION_A                      ; SIGNED            ; Untyped                                                                                                               ;
; REPRESENTATION_B                      ; SIGNED            ; Untyped                                                                                                               ;
; ROTATE_ACLR                           ; ACLR3             ; Untyped                                                                                                               ;
; ROTATE_OUTPUT_ACLR                    ; ACLR3             ; Untyped                                                                                                               ;
; ROTATE_OUTPUT_REGISTER                ; CLOCK0            ; Untyped                                                                                                               ;
; ROTATE_PIPELINE_ACLR                  ; ACLR3             ; Untyped                                                                                                               ;
; ROTATE_PIPELINE_REGISTER              ; CLOCK0            ; Untyped                                                                                                               ;
; ROTATE_REGISTER                       ; CLOCK0            ; Untyped                                                                                                               ;
; WIDTH_MSB                             ; 17                ; Untyped                                                                                                               ;
; WIDTH_SATURATE_SIGN                   ; 1                 ; Untyped                                                                                                               ;
; SCANOUTA_ACLR                         ; ACLR3             ; Untyped                                                                                                               ;
; SCANOUTA_REGISTER                     ; UNREGISTERED      ; Untyped                                                                                                               ;
; SHIFT_MODE                            ; NO                ; Untyped                                                                                                               ;
; SHIFT_RIGHT_ACLR                      ; ACLR3             ; Untyped                                                                                                               ;
; SHIFT_RIGHT_OUTPUT_ACLR               ; ACLR3             ; Untyped                                                                                                               ;
; SHIFT_RIGHT_OUTPUT_REGISTER           ; CLOCK0            ; Untyped                                                                                                               ;
; SHIFT_RIGHT_PIPELINE_ACLR             ; ACLR3             ; Untyped                                                                                                               ;
; SHIFT_RIGHT_PIPELINE_REGISTER         ; CLOCK0            ; Untyped                                                                                                               ;
; SHIFT_RIGHT_REGISTER                  ; CLOCK0            ; Untyped                                                                                                               ;
; SIGNED_ACLR_A                         ; ACLR3             ; Untyped                                                                                                               ;
; SIGNED_ACLR_B                         ; ACLR3             ; Untyped                                                                                                               ;
; SIGNED_PIPELINE_ACLR_A                ; ACLR3             ; Untyped                                                                                                               ;
; SIGNED_PIPELINE_ACLR_B                ; ACLR3             ; Untyped                                                                                                               ;
; SIGNED_PIPELINE_REGISTER_A            ; CLOCK0            ; Untyped                                                                                                               ;
; SIGNED_PIPELINE_REGISTER_B            ; CLOCK0            ; Untyped                                                                                                               ;
; SIGNED_REGISTER_A                     ; CLOCK0            ; Untyped                                                                                                               ;
; SIGNED_REGISTER_B                     ; CLOCK0            ; Untyped                                                                                                               ;
; WIDTH_A                               ; 17                ; Signed Integer                                                                                                        ;
; WIDTH_B                               ; 17                ; Signed Integer                                                                                                        ;
; WIDTH_CHAININ                         ; 1                 ; Untyped                                                                                                               ;
; WIDTH_RESULT                          ; 34                ; Signed Integer                                                                                                        ;
; ZERO_CHAINOUT_OUTPUT_ACLR             ; ACLR3             ; Untyped                                                                                                               ;
; ZERO_CHAINOUT_OUTPUT_REGISTER         ; CLOCK0            ; Untyped                                                                                                               ;
; ZERO_LOOPBACK_ACLR                    ; ACLR3             ; Untyped                                                                                                               ;
; ZERO_LOOPBACK_OUTPUT_ACLR             ; ACLR3             ; Untyped                                                                                                               ;
; ZERO_LOOPBACK_OUTPUT_REGISTER         ; CLOCK0            ; Untyped                                                                                                               ;
; ZERO_LOOPBACK_PIPELINE_ACLR           ; ACLR3             ; Untyped                                                                                                               ;
; ZERO_LOOPBACK_PIPELINE_REGISTER       ; CLOCK0            ; Untyped                                                                                                               ;
; ZERO_LOOPBACK_REGISTER                ; CLOCK0            ; Untyped                                                                                                               ;
; CBXI_PARAMETER                        ; mult_add_dqa1     ; Untyped                                                                                                               ;
; DEVICE_FAMILY                         ; Cyclone II        ; Untyped                                                                                                               ;
+---------------------------------------+-------------------+-----------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6 ;
+---------------------------------------+-------------------+-----------------------------------------------------------------------------------------------------------------------+
; Parameter Name                        ; Value             ; Type                                                                                                                  ;
+---------------------------------------+-------------------+-----------------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                     ; ON                ; AUTO_CARRY                                                                                                            ;
; IGNORE_CARRY_BUFFERS                  ; OFF               ; IGNORE_CARRY                                                                                                          ;
; AUTO_CASCADE_CHAINS                   ; ON                ; AUTO_CASCADE                                                                                                          ;
; IGNORE_CASCADE_BUFFERS                ; OFF               ; IGNORE_CASCADE                                                                                                        ;
; ACCUM_DIRECTION                       ; ADD               ; Untyped                                                                                                               ;
; ACCUM_SLOAD_ACLR                      ; ACLR3             ; Untyped                                                                                                               ;
; ACCUM_SLOAD_PIPELINE_ACLR             ; ACLR3             ; Untyped                                                                                                               ;
; ACCUM_SLOAD_PIPELINE_REGISTER         ; CLOCK0            ; Untyped                                                                                                               ;
; ACCUM_SLOAD_REGISTER                  ; CLOCK0            ; Untyped                                                                                                               ;
; ACCUMULATOR                           ; NO                ; Untyped                                                                                                               ;
; ADDER1_ROUNDING                       ; NO                ; Untyped                                                                                                               ;
; ADDER3_ROUNDING                       ; NO                ; Untyped                                                                                                               ;
; ADDNSUB1_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB1_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB1_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB1_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB3_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB3_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB3_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB3_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_ACLR1              ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_ACLR3              ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR1     ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR3     ; ACLR3             ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_REGISTER1          ; CLOCK0            ; Untyped                                                                                                               ;
; ADDNSUB_MULTIPLIER_REGISTER3          ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_ACLR                         ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_ADDER                        ; NO                ; Untyped                                                                                                               ;
; CHAINOUT_REGISTER                     ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_ROUND_ACLR                   ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_ROUND_OUTPUT_ACLR            ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_ROUND_OUTPUT_REGISTER        ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_ROUND_PIPELINE_ACLR          ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_ROUND_PIPELINE_REGISTER      ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_ROUND_REGISTER               ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_ROUNDING                     ; NO                ; Untyped                                                                                                               ;
; CHAINOUT_SATURATE_ACLR                ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_SATURATE_OUTPUT_ACLR         ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_SATURATE_OUTPUT_REGISTER     ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_SATURATE_PIPELINE_ACLR       ; ACLR3             ; Untyped                                                                                                               ;
; CHAINOUT_SATURATE_PIPELINE_REGISTER   ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_SATURATE_REGISTER            ; CLOCK0            ; Untyped                                                                                                               ;
; CHAINOUT_SATURATION                   ; NO                ; Untyped                                                                                                               ;
; DEDICATED_MULTIPLIER_CIRCUITRY        ; AUTO              ; Untyped                                                                                                               ;
; DSP_BLOCK_BALANCING                   ; AUTO              ; Untyped                                                                                                               ;
; EXTRA_LATENCY                         ; 0                 ; Untyped                                                                                                               ;
; INPUT_ACLR_A0                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_ACLR_A1                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_ACLR_A2                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_ACLR_A3                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_ACLR_B0                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_ACLR_B1                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_ACLR_B2                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_ACLR_B3                         ; ACLR3             ; Untyped                                                                                                               ;
; INPUT_REGISTER_A0                     ; UNREGISTERED      ; Untyped                                                                                                               ;
; INPUT_REGISTER_A1                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_A2                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_A3                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_B0                     ; UNREGISTERED      ; Untyped                                                                                                               ;
; INPUT_REGISTER_B1                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_B2                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_REGISTER_B3                     ; CLOCK0            ; Untyped                                                                                                               ;
; INPUT_SOURCE_A0                       ; DATAA             ; Untyped                                                                                                               ;
; INPUT_SOURCE_A1                       ; DATAA             ; Untyped                                                                                                               ;
; INPUT_SOURCE_A2                       ; DATAA             ; Untyped                                                                                                               ;
; INPUT_SOURCE_A3                       ; DATAA             ; Untyped                                                                                                               ;
; INPUT_SOURCE_B0                       ; DATAB             ; Untyped                                                                                                               ;
; INPUT_SOURCE_B1                       ; DATAB             ; Untyped                                                                                                               ;
; INPUT_SOURCE_B2                       ; DATAB             ; Untyped                                                                                                               ;
; INPUT_SOURCE_B3                       ; DATAB             ; Untyped                                                                                                               ;
; MULT01_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                                                               ;
; MULT01_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                                                               ;
; MULT01_SATURATION_ACLR                ; ACLR2             ; Untyped                                                                                                               ;
; MULT01_SATURATION_REGISTER            ; CLOCK0            ; Untyped                                                                                                               ;
; MULT23_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                                                               ;
; MULT23_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                                                               ;
; MULT23_SATURATION_ACLR                ; ACLR3             ; Untyped                                                                                                               ;
; MULT23_SATURATION_REGISTER            ; CLOCK0            ; Untyped                                                                                                               ;
; MULTIPLIER01_ROUNDING                 ; NO                ; Untyped                                                                                                               ;
; MULTIPLIER01_SATURATION               ; NO                ; Untyped                                                                                                               ;
; MULTIPLIER1_DIRECTION                 ; ADD               ; Untyped                                                                                                               ;
; MULTIPLIER23_ROUNDING                 ; NO                ; Untyped                                                                                                               ;
; MULTIPLIER23_SATURATION               ; NO                ; Untyped                                                                                                               ;
; MULTIPLIER3_DIRECTION                 ; ADD               ; Untyped                                                                                                               ;
; MULTIPLIER_ACLR0                      ; ACLR3             ; Untyped                                                                                                               ;
; MULTIPLIER_ACLR1                      ; ACLR3             ; Untyped                                                                                                               ;
; MULTIPLIER_ACLR2                      ; ACLR3             ; Untyped                                                                                                               ;
; MULTIPLIER_ACLR3                      ; ACLR3             ; Untyped                                                                                                               ;
; MULTIPLIER_REGISTER0                  ; UNREGISTERED      ; Untyped                                                                                                               ;
; MULTIPLIER_REGISTER1                  ; CLOCK0            ; Untyped                                                                                                               ;
; MULTIPLIER_REGISTER2                  ; CLOCK0            ; Untyped                                                                                                               ;
; MULTIPLIER_REGISTER3                  ; CLOCK0            ; Untyped                                                                                                               ;
; NUMBER_OF_MULTIPLIERS                 ; 1                 ; Signed Integer                                                                                                        ;
; OUTPUT_ACLR                           ; ACLR0             ; Untyped                                                                                                               ;
; OUTPUT_REGISTER                       ; CLOCK0            ; Untyped                                                                                                               ;
; OUTPUT_ROUND_ACLR                     ; ACLR3             ; Untyped                                                                                                               ;
; OUTPUT_ROUND_PIPELINE_ACLR            ; ACLR3             ; Untyped                                                                                                               ;
; OUTPUT_ROUND_PIPELINE_REGISTER        ; CLOCK0            ; Untyped                                                                                                               ;
; OUTPUT_ROUND_REGISTER                 ; CLOCK0            ; Untyped                                                                                                               ;
; OUTPUT_ROUND_TYPE                     ; NEAREST_INTEGER   ; Untyped                                                                                                               ;
; OUTPUT_ROUNDING                       ; NO                ; Untyped                                                                                                               ;
; OUTPUT_SATURATE_ACLR                  ; ACLR3             ; Untyped                                                                                                               ;
; OUTPUT_SATURATE_PIPELINE_ACLR         ; ACLR3             ; Untyped                                                                                                               ;
; OUTPUT_SATURATE_PIPELINE_REGISTER     ; CLOCK0            ; Untyped                                                                                                               ;
; OUTPUT_SATURATE_REGISTER              ; CLOCK0            ; Untyped                                                                                                               ;
; OUTPUT_SATURATE_TYPE                  ; ASYMMETRIC        ; Untyped                                                                                                               ;
; OUTPUT_SATURATION                     ; NO                ; Untyped                                                                                                               ;
; port_addnsub1                         ; PORT_CONNECTIVITY ; Untyped                                                                                                               ;
; port_addnsub3                         ; PORT_CONNECTIVITY ; Untyped                                                                                                               ;
; PORT_CHAINOUT_SAT_IS_OVERFLOW         ; PORT_UNUSED       ; Untyped                                                                                                               ;
; PORT_MULT0_IS_SATURATED               ; UNUSED            ; Untyped                                                                                                               ;
; PORT_MULT1_IS_SATURATED               ; UNUSED            ; Untyped                                                                                                               ;
; PORT_MULT2_IS_SATURATED               ; UNUSED            ; Untyped                                                                                                               ;
; PORT_MULT3_IS_SATURATED               ; UNUSED            ; Untyped                                                                                                               ;
; PORT_OUTPUT_IS_OVERFLOW               ; PORT_UNUSED       ; Untyped                                                                                                               ;
; port_signa                            ; PORT_CONNECTIVITY ; Untyped                                                                                                               ;
; port_signb                            ; PORT_CONNECTIVITY ; Untyped                                                                                                               ;
; REPRESENTATION_A                      ; SIGNED            ; Untyped                                                                                                               ;
; REPRESENTATION_B                      ; SIGNED            ; Untyped                                                                                                               ;
; ROTATE_ACLR                           ; ACLR3             ; Untyped                                                                                                               ;
; ROTATE_OUTPUT_ACLR                    ; ACLR3             ; Untyped                                                                                                               ;
; ROTATE_OUTPUT_REGISTER                ; CLOCK0            ; Untyped                                                                                                               ;
; ROTATE_PIPELINE_ACLR                  ; ACLR3             ; Untyped                                                                                                               ;
; ROTATE_PIPELINE_REGISTER              ; CLOCK0            ; Untyped                                                                                                               ;
; ROTATE_REGISTER                       ; CLOCK0            ; Untyped                                                                                                               ;
; WIDTH_MSB                             ; 17                ; Untyped                                                                                                               ;
; WIDTH_SATURATE_SIGN                   ; 1                 ; Untyped                                                                                                               ;
; SCANOUTA_ACLR                         ; ACLR3             ; Untyped                                                                                                               ;
; SCANOUTA_REGISTER                     ; UNREGISTERED      ; Untyped                                                                                                               ;
; SHIFT_MODE                            ; NO                ; Untyped                                                                                                               ;
; SHIFT_RIGHT_ACLR                      ; ACLR3             ; Untyped                                                                                                               ;
; SHIFT_RIGHT_OUTPUT_ACLR               ; ACLR3             ; Untyped                                                                                                               ;
; SHIFT_RIGHT_OUTPUT_REGISTER           ; CLOCK0            ; Untyped                                                                                                               ;
; SHIFT_RIGHT_PIPELINE_ACLR             ; ACLR3             ; Untyped                                                                                                               ;
; SHIFT_RIGHT_PIPELINE_REGISTER         ; CLOCK0            ; Untyped                                                                                                               ;
; SHIFT_RIGHT_REGISTER                  ; CLOCK0            ; Untyped                                                                                                               ;
; SIGNED_ACLR_A                         ; ACLR3             ; Untyped                                                                                                               ;
; SIGNED_ACLR_B                         ; ACLR3             ; Untyped                                                                                                               ;
; SIGNED_PIPELINE_ACLR_A                ; ACLR3             ; Untyped                                                                                                               ;
; SIGNED_PIPELINE_ACLR_B                ; ACLR3             ; Untyped                                                                                                               ;
; SIGNED_PIPELINE_REGISTER_A            ; CLOCK0            ; Untyped                                                                                                               ;
; SIGNED_PIPELINE_REGISTER_B            ; CLOCK0            ; Untyped                                                                                                               ;
; SIGNED_REGISTER_A                     ; CLOCK0            ; Untyped                                                                                                               ;
; SIGNED_REGISTER_B                     ; CLOCK0            ; Untyped                                                                                                               ;
; WIDTH_A                               ; 18                ; Signed Integer                                                                                                        ;
; WIDTH_B                               ; 18                ; Signed Integer                                                                                                        ;
; WIDTH_CHAININ                         ; 1                 ; Untyped                                                                                                               ;
; WIDTH_RESULT                          ; 36                ; Signed Integer                                                                                                        ;
; ZERO_CHAINOUT_OUTPUT_ACLR             ; ACLR3             ; Untyped                                                                                                               ;
; ZERO_CHAINOUT_OUTPUT_REGISTER         ; CLOCK0            ; Untyped                                                                                                               ;
; ZERO_LOOPBACK_ACLR                    ; ACLR3             ; Untyped                                                                                                               ;
; ZERO_LOOPBACK_OUTPUT_ACLR             ; ACLR3             ; Untyped                                                                                                               ;
; ZERO_LOOPBACK_OUTPUT_REGISTER         ; CLOCK0            ; Untyped                                                                                                               ;
; ZERO_LOOPBACK_PIPELINE_ACLR           ; ACLR3             ; Untyped                                                                                                               ;
; ZERO_LOOPBACK_PIPELINE_REGISTER       ; CLOCK0            ; Untyped                                                                                                               ;
; ZERO_LOOPBACK_REGISTER                ; CLOCK0            ; Untyped                                                                                                               ;
; CBXI_PARAMETER                        ; mult_add_ie81     ; Untyped                                                                                                               ;
; DEVICE_FAMILY                         ; Cyclone II        ; Untyped                                                                                                               ;
+---------------------------------------+-------------------+-----------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:add_sub7 ;
+------------------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                                                                                                      ;
+------------------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------+
; LPM_WIDTH              ; 35          ; Signed Integer                                                                                                                            ;
; LPM_REPRESENTATION     ; SIGNED      ; Untyped                                                                                                                                   ;
; LPM_DIRECTION          ; ADD         ; Untyped                                                                                                                                   ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                                                                                                                   ;
; LPM_PIPELINE           ; 1           ; Signed Integer                                                                                                                            ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                                                                                                                   ;
; REGISTERED_AT_END      ; 0           ; Untyped                                                                                                                                   ;
; OPTIMIZE_FOR_SPEED     ; 5           ; Untyped                                                                                                                                   ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                                                                                                                   ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                                                   ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                                        ;
; DEVICE_FAMILY          ; Cyclone II  ; Untyped                                                                                                                                   ;
; USE_WYS                ; OFF         ; Untyped                                                                                                                                   ;
; STYLE                  ; FAST        ; Untyped                                                                                                                                   ;
; CBXI_PARAMETER         ; add_sub_esf ; Untyped                                                                                                                                   ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                                                ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                                              ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                                              ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                                            ;
+------------------------+-------------+-------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder1 ;
+------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                                                                                                    ;
+------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------+
; LPM_WIDTH              ; 18          ; Signed Integer                                                                                                                          ;
; LPM_REPRESENTATION     ; SIGNED      ; Untyped                                                                                                                                 ;
; LPM_DIRECTION          ; ADD         ; Untyped                                                                                                                                 ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                                                                                                                 ;
; LPM_PIPELINE           ; 1           ; Signed Integer                                                                                                                          ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                                                                                                                 ;
; REGISTERED_AT_END      ; 0           ; Untyped                                                                                                                                 ;
; OPTIMIZE_FOR_SPEED     ; 5           ; Untyped                                                                                                                                 ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                                                                                                                 ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                                                 ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                                      ;
; DEVICE_FAMILY          ; Cyclone II  ; Untyped                                                                                                                                 ;
; USE_WYS                ; OFF         ; Untyped                                                                                                                                 ;
; STYLE                  ; FAST        ; Untyped                                                                                                                                 ;
; CBXI_PARAMETER         ; add_sub_5ii ; Untyped                                                                                                                                 ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                                              ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                                            ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                                            ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                                          ;
+------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder2 ;
+------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                                                                                                    ;
+------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------+
; LPM_WIDTH              ; 35          ; Signed Integer                                                                                                                          ;
; LPM_REPRESENTATION     ; SIGNED      ; Untyped                                                                                                                                 ;
; LPM_DIRECTION          ; ADD         ; Untyped                                                                                                                                 ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                                                                                                                 ;
; LPM_PIPELINE           ; 2           ; Signed Integer                                                                                                                          ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                                                                                                                 ;
; REGISTERED_AT_END      ; 0           ; Untyped                                                                                                                                 ;
; OPTIMIZE_FOR_SPEED     ; 5           ; Untyped                                                                                                                                 ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                                                                                                                 ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                                                 ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                                      ;
; DEVICE_FAMILY          ; Cyclone II  ; Untyped                                                                                                                                 ;
; USE_WYS                ; OFF         ; Untyped                                                                                                                                 ;
; STYLE                  ; FAST        ; Untyped                                                                                                                                 ;
; CBXI_PARAMETER         ; add_sub_6ii ; Untyped                                                                                                                                 ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                                              ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                                            ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                                            ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                                          ;
+------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1 ;
+------------------------+-------------+----------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                                                                                                         ;
+------------------------+-------------+----------------------------------------------------------------------------------------------------------------------------------------------+
; LPM_WIDTH              ; 18          ; Signed Integer                                                                                                                               ;
; LPM_REPRESENTATION     ; SIGNED      ; Untyped                                                                                                                                      ;
; LPM_DIRECTION          ; SUB         ; Untyped                                                                                                                                      ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                                                                                                                      ;
; LPM_PIPELINE           ; 1           ; Signed Integer                                                                                                                               ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                                                                                                                      ;
; REGISTERED_AT_END      ; 0           ; Untyped                                                                                                                                      ;
; OPTIMIZE_FOR_SPEED     ; 5           ; Untyped                                                                                                                                      ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                                                                                                                      ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                                                      ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                                           ;
; DEVICE_FAMILY          ; Cyclone II  ; Untyped                                                                                                                                      ;
; USE_WYS                ; OFF         ; Untyped                                                                                                                                      ;
; STYLE                  ; FAST        ; Untyped                                                                                                                                      ;
; CBXI_PARAMETER         ; add_sub_6ji ; Untyped                                                                                                                                      ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                                                   ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                                                 ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                                               ;
+------------------------+-------------+----------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor2 ;
+------------------------+-------------+----------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                                                                                                         ;
+------------------------+-------------+----------------------------------------------------------------------------------------------------------------------------------------------+
; LPM_WIDTH              ; 35          ; Signed Integer                                                                                                                               ;
; LPM_REPRESENTATION     ; SIGNED      ; Untyped                                                                                                                                      ;
; LPM_DIRECTION          ; SUB         ; Untyped                                                                                                                                      ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                                                                                                                      ;
; LPM_PIPELINE           ; 1           ; Signed Integer                                                                                                                               ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                                                                                                                      ;
; REGISTERED_AT_END      ; 0           ; Untyped                                                                                                                                      ;
; OPTIMIZE_FOR_SPEED     ; 5           ; Untyped                                                                                                                                      ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                                                                                                                      ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                                                      ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                                           ;
; DEVICE_FAMILY          ; Cyclone II  ; Untyped                                                                                                                                      ;
; USE_WYS                ; OFF         ; Untyped                                                                                                                                      ;
; STYLE                  ; FAST        ; Untyped                                                                                                                                      ;
; CBXI_PARAMETER         ; add_sub_5ji ; Untyped                                                                                                                                      ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                                                   ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                                                 ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                                               ;
+------------------------+-------------+----------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor3 ;
+------------------------+-------------+----------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                                                                                                         ;
+------------------------+-------------+----------------------------------------------------------------------------------------------------------------------------------------------+
; LPM_WIDTH              ; 36          ; Signed Integer                                                                                                                               ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                                                                                                                      ;
; LPM_DIRECTION          ; ADD         ; Untyped                                                                                                                                      ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                                                                                                                      ;
; LPM_PIPELINE           ; 1           ; Signed Integer                                                                                                                               ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                                                                                                                      ;
; REGISTERED_AT_END      ; 0           ; Untyped                                                                                                                                      ;
; OPTIMIZE_FOR_SPEED     ; 5           ; Untyped                                                                                                                                      ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                                                                                                                      ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                                                      ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                                           ;
; DEVICE_FAMILY          ; Cyclone II  ; Untyped                                                                                                                                      ;
; USE_WYS                ; OFF         ; Untyped                                                                                                                                      ;
; STYLE                  ; FAST        ; Untyped                                                                                                                                      ;
; CBXI_PARAMETER         ; add_sub_i5j ; Untyped                                                                                                                                      ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                                                   ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                                                 ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                                               ;
+------------------------+-------------+----------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_compare:comparator1 ;
+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value      ; Type                                                                                                                                          ;
+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_width              ; 17         ; Signed Integer                                                                                                                                ;
; LPM_REPRESENTATION     ; SIGNED     ; Untyped                                                                                                                                       ;
; LPM_PIPELINE           ; 0          ; Untyped                                                                                                                                       ;
; CHAIN_SIZE             ; 8          ; Untyped                                                                                                                                       ;
; ONE_INPUT_IS_CONSTANT  ; NO         ; Untyped                                                                                                                                       ;
; CARRY_CHAIN            ; MANUAL     ; Untyped                                                                                                                                       ;
; CASCADE_CHAIN          ; MANUAL     ; Untyped                                                                                                                                       ;
; CARRY_CHAIN_LENGTH     ; 48         ; CARRY_CHAIN_LENGTH                                                                                                                            ;
; CASCADE_CHAIN_LENGTH   ; 2          ; CASCADE_CHAIN_LENGTH                                                                                                                          ;
; DEVICE_FAMILY          ; Cyclone II ; Untyped                                                                                                                                       ;
; CBXI_PARAMETER         ; cmpr_1cg   ; Untyped                                                                                                                                       ;
; AUTO_CARRY_CHAINS      ; ON         ; AUTO_CARRY                                                                                                                                    ;
; IGNORE_CARRY_BUFFERS   ; OFF        ; IGNORE_CARRY                                                                                                                                  ;
; AUTO_CASCADE_CHAINS    ; ON         ; AUTO_CASCADE                                                                                                                                  ;
; IGNORE_CASCADE_BUFFERS ; OFF        ; IGNORE_CASCADE                                                                                                                                ;
+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: s2p:inst6 ;
+----------------+---------+-----------------------------+
; Parameter Name ; Value   ; Type                        ;
+----------------+---------+-----------------------------+
; scale          ; 1000000 ; Unsigned Binary             ;
+----------------+---------+-----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: s2p:inst7 ;
+----------------+---------+-----------------------------+
; Parameter Name ; Value   ; Type                        ;
+----------------+---------+-----------------------------+
; scale          ; 1000000 ; Unsigned Binary             ;
+----------------+---------+-----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_rom1:inst2|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+---------------------------------+
; Parameter Name                     ; Value                ; Type                            ;
+------------------------------------+----------------------+---------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                         ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                  ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                         ;
; OPERATION_MODE                     ; ROM                  ; Untyped                         ;
; WIDTH_A                            ; 16                   ; Signed Integer                  ;
; WIDTHAD_A                          ; 5                    ; Signed Integer                  ;
; NUMWORDS_A                         ; 32                   ; Signed Integer                  ;
; OUTDATA_REG_A                      ; CLOCK0               ; Untyped                         ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                         ;
; OUTDATA_ACLR_A                     ; CLEAR0               ; Untyped                         ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                         ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                         ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                         ;
; WIDTH_B                            ; 1                    ; Untyped                         ;
; WIDTHAD_B                          ; 1                    ; Untyped                         ;
; NUMWORDS_B                         ; 1                    ; Untyped                         ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                         ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                         ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                         ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                         ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                         ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                         ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                         ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                         ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                         ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                         ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                         ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                         ;
; WIDTH_BYTEENA_A                    ; 1                    ; Signed Integer                  ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                         ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                         ;
; BYTE_SIZE                          ; 8                    ; Untyped                         ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                         ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                         ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                         ;
; INIT_FILE                          ; WN_isin.mif          ; Untyped                         ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                         ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                         ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS               ; Untyped                         ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                         ;
; CLOCK_ENABLE_OUTPUT_A              ; BYPASS               ; Untyped                         ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                         ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                         ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                         ;
; ENABLE_ECC                         ; FALSE                ; Untyped                         ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                         ;
; CBXI_PARAMETER                     ; altsyncram_qq71      ; Untyped                         ;
+------------------------------------+----------------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_rom0:inst1|altsyncram:altsyncram_component ;
+------------------------------------+---------------------------------+----------------------+
; Parameter Name                     ; Value                           ; Type                 ;
+------------------------------------+---------------------------------+----------------------+
; BYTE_SIZE_BLOCK                    ; 8                               ; Untyped              ;
; AUTO_CARRY_CHAINS                  ; ON                              ; AUTO_CARRY           ;
; IGNORE_CARRY_BUFFERS               ; OFF                             ; IGNORE_CARRY         ;
; AUTO_CASCADE_CHAINS                ; ON                              ; AUTO_CASCADE         ;
; IGNORE_CASCADE_BUFFERS             ; OFF                             ; IGNORE_CASCADE       ;
; WIDTH_BYTEENA                      ; 1                               ; Untyped              ;
; OPERATION_MODE                     ; ROM                             ; Untyped              ;
; WIDTH_A                            ; 16                              ; Signed Integer       ;
; WIDTHAD_A                          ; 5                               ; Signed Integer       ;
; NUMWORDS_A                         ; 32                              ; Signed Integer       ;
; OUTDATA_REG_A                      ; CLOCK0                          ; Untyped              ;
; ADDRESS_ACLR_A                     ; NONE                            ; Untyped              ;
; OUTDATA_ACLR_A                     ; CLEAR0                          ; Untyped              ;
; WRCONTROL_ACLR_A                   ; NONE                            ; Untyped              ;
; INDATA_ACLR_A                      ; NONE                            ; Untyped              ;
; BYTEENA_ACLR_A                     ; NONE                            ; Untyped              ;
; WIDTH_B                            ; 1                               ; Untyped              ;
; WIDTHAD_B                          ; 1                               ; Untyped              ;
; NUMWORDS_B                         ; 1                               ; Untyped              ;
; INDATA_REG_B                       ; CLOCK1                          ; Untyped              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                          ; Untyped              ;
; RDCONTROL_REG_B                    ; CLOCK1                          ; Untyped              ;
; ADDRESS_REG_B                      ; CLOCK1                          ; Untyped              ;
; OUTDATA_REG_B                      ; UNREGISTERED                    ; Untyped              ;
; BYTEENA_REG_B                      ; CLOCK1                          ; Untyped              ;
; INDATA_ACLR_B                      ; NONE                            ; Untyped              ;
; WRCONTROL_ACLR_B                   ; NONE                            ; Untyped              ;
; ADDRESS_ACLR_B                     ; NONE                            ; Untyped              ;
; OUTDATA_ACLR_B                     ; NONE                            ; Untyped              ;
; RDCONTROL_ACLR_B                   ; NONE                            ; Untyped              ;
; BYTEENA_ACLR_B                     ; NONE                            ; Untyped              ;
; WIDTH_BYTEENA_A                    ; 1                               ; Signed Integer       ;
; WIDTH_BYTEENA_B                    ; 1                               ; Untyped              ;
; RAM_BLOCK_TYPE                     ; AUTO                            ; Untyped              ;
; BYTE_SIZE                          ; 8                               ; Untyped              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                       ; Untyped              ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ            ; Untyped              ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ            ; Untyped              ;
; INIT_FILE                          ; ../FFT last edition/WN_rcos.mif ; Untyped              ;
; INIT_FILE_LAYOUT                   ; PORT_A                          ; Untyped              ;
; MAXIMUM_DEPTH                      ; 0                               ; Untyped              ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS                          ; Untyped              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                          ; Untyped              ;
; CLOCK_ENABLE_OUTPUT_A              ; BYPASS                          ; Untyped              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                          ; Untyped              ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN                 ; Untyped              ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN                 ; Untyped              ;
; ENABLE_ECC                         ; FALSE                           ; Untyped              ;
; DEVICE_FAMILY                      ; Cyclone II                      ; Untyped              ;
; CBXI_PARAMETER                     ; altsyncram_oh91                 ; Untyped              ;
+------------------------------------+---------------------------------+----------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_fifo0:inst|scfifo:scfifo_component ;
+-------------------------+-------------+---------------------------------------------+
; Parameter Name          ; Value       ; Type                                        ;
+-------------------------+-------------+---------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                  ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                              ;
; lpm_width               ; 18          ; Signed Integer                              ;
; LPM_NUMWORDS            ; 64          ; Signed Integer                              ;
; LPM_WIDTHU              ; 6           ; Signed Integer                              ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                     ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                     ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                     ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                     ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                     ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                     ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                     ;
; USE_EAB                 ; ON          ; Untyped                                     ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                     ;
; DEVICE_FAMILY           ; Cyclone II  ; Untyped                                     ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                     ;
; CBXI_PARAMETER          ; scfifo_7r31 ; Untyped                                     ;
+-------------------------+-------------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------+
; Parameter Settings for User Entity Instance: p2s:inst13 ;
+----------------+---------+------------------------------+
; Parameter Name ; Value   ; Type                         ;
+----------------+---------+------------------------------+
; scale          ; 1000000 ; Unsigned Binary              ;
+----------------+---------+------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_rom2:inst19|altsyncram:altsyncram_component         ;
+------------------------------------+------------------------------------------------+----------------+
; Parameter Name                     ; Value                                          ; Type           ;
+------------------------------------+------------------------------------------------+----------------+
; BYTE_SIZE_BLOCK                    ; 8                                              ; Untyped        ;
; AUTO_CARRY_CHAINS                  ; ON                                             ; AUTO_CARRY     ;
; IGNORE_CARRY_BUFFERS               ; OFF                                            ; IGNORE_CARRY   ;
; AUTO_CASCADE_CHAINS                ; ON                                             ; AUTO_CASCADE   ;
; IGNORE_CASCADE_BUFFERS             ; OFF                                            ; IGNORE_CASCADE ;
; WIDTH_BYTEENA                      ; 1                                              ; Untyped        ;
; OPERATION_MODE                     ; ROM                                            ; Untyped        ;
; WIDTH_A                            ; 16                                             ; Signed Integer ;
; WIDTHAD_A                          ; 6                                              ; Signed Integer ;
; NUMWORDS_A                         ; 64                                             ; Signed Integer ;
; OUTDATA_REG_A                      ; CLOCK0                                         ; Untyped        ;
; ADDRESS_ACLR_A                     ; NONE                                           ; Untyped        ;
; OUTDATA_ACLR_A                     ; CLEAR0                                         ; Untyped        ;
; WRCONTROL_ACLR_A                   ; NONE                                           ; Untyped        ;
; INDATA_ACLR_A                      ; NONE                                           ; Untyped        ;
; BYTEENA_ACLR_A                     ; NONE                                           ; Untyped        ;
; WIDTH_B                            ; 1                                              ; Untyped        ;
; WIDTHAD_B                          ; 1                                              ; Untyped        ;
; NUMWORDS_B                         ; 1                                              ; Untyped        ;
; INDATA_REG_B                       ; CLOCK1                                         ; Untyped        ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                                         ; Untyped        ;
; RDCONTROL_REG_B                    ; CLOCK1                                         ; Untyped        ;
; ADDRESS_REG_B                      ; CLOCK1                                         ; Untyped        ;
; OUTDATA_REG_B                      ; UNREGISTERED                                   ; Untyped        ;
; BYTEENA_REG_B                      ; CLOCK1                                         ; Untyped        ;
; INDATA_ACLR_B                      ; NONE                                           ; Untyped        ;
; WRCONTROL_ACLR_B                   ; NONE                                           ; Untyped        ;
; ADDRESS_ACLR_B                     ; NONE                                           ; Untyped        ;
; OUTDATA_ACLR_B                     ; NONE                                           ; Untyped        ;
; RDCONTROL_ACLR_B                   ; NONE                                           ; Untyped        ;
; BYTEENA_ACLR_B                     ; NONE                                           ; Untyped        ;
; WIDTH_BYTEENA_A                    ; 1                                              ; Signed Integer ;
; WIDTH_BYTEENA_B                    ; 1                                              ; Untyped        ;
; RAM_BLOCK_TYPE                     ; AUTO                                           ; Untyped        ;
; BYTE_SIZE                          ; 8                                              ; Untyped        ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                      ; Untyped        ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ                           ; Untyped        ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ                           ; Untyped        ;
; INIT_FILE                          ; C:/Documents and Settings/wangwei/桌面/sin.mif ; Untyped        ;
; INIT_FILE_LAYOUT                   ; PORT_A                                         ; Untyped        ;
; MAXIMUM_DEPTH                      ; 0                                              ; Untyped        ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS                                         ; Untyped        ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                                         ; Untyped        ;
; CLOCK_ENABLE_OUTPUT_A              ; BYPASS                                         ; Untyped        ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                                         ; Untyped        ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN                                ; Untyped        ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN                                ; Untyped        ;
; ENABLE_ECC                         ; FALSE                                          ; Untyped        ;
; DEVICE_FAMILY                      ; Cyclone II                                     ; Untyped        ;
; CBXI_PARAMETER                     ; altsyncram_kfa1                                ; Untyped        ;
+------------------------------------+------------------------------------------------+----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_counter0:inst4|lpm_counter:lpm_counter_component ;
+------------------------+-------------+------------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                       ;
+------------------------+-------------+------------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                               ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                               ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                             ;
; LPM_WIDTH              ; 6           ; Signed Integer                                             ;
; LPM_DIRECTION          ; UP          ; Untyped                                                    ;
; LPM_MODULUS            ; 0           ; Untyped                                                    ;
; LPM_AVALUE             ; UNUSED      ; Untyped                                                    ;
; LPM_SVALUE             ; UNUSED      ; Untyped                                                    ;
; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                    ;
; DEVICE_FAMILY          ; Cyclone II  ; Untyped                                                    ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                    ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                         ;
; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                         ;
; CARRY_CNT_EN           ; SMART       ; Untyped                                                    ;
; LABWIDE_SCLR           ; ON          ; Untyped                                                    ;
; USE_NEW_VERSION        ; TRUE        ; Untyped                                                    ;
; CBXI_PARAMETER         ; cntr_qkh    ; Untyped                                                    ;
+------------------------+-------------+------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------+
; Parameter Settings for User Entity Instance: block_new:inst45 ;
+----------------+----------+-----------------------------------+
; Parameter Name ; Value    ; Type                              ;
+----------------+----------+-----------------------------------+
; s0             ; 00       ; Unsigned Binary                   ;
; s1             ; 01       ; Unsigned Binary                   ;
; s2             ; 10       ; Unsigned Binary                   ;
; scale          ; 01000000 ; Unsigned Binary                   ;
+----------------+----------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0                                                                                                                                                             ;
+------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
; Parameter Name               ; Value                                                                                                                                                                                       ; Type           ;
+------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
; lpm_type                     ; sld_signaltap                                                                                                                                                                               ; String         ;
; sld_node_info                ; 805334528                                                                                                                                                                                   ; Untyped        ;
; sld_ip_version               ; 6                                                                                                                                                                                           ; Signed Integer ;
; sld_ip_minor_version         ; 0                                                                                                                                                                                           ; Signed Integer ;
; sld_common_ip_version        ; 0                                                                                                                                                                                           ; Signed Integer ;
; sld_data_bits                ; 54                                                                                                                                                                                          ; Untyped        ;
; sld_trigger_bits             ; 54                                                                                                                                                                                          ; Untyped        ;
; sld_node_crc_bits            ; 32                                                                                                                                                                                          ; Signed Integer ;
; sld_node_crc_hiword          ; 32016                                                                                                                                                                                       ; Untyped        ;
; sld_node_crc_loword          ; 3297                                                                                                                                                                                        ; Untyped        ;
; sld_incremental_routing      ; 0                                                                                                                                                                                           ; Signed Integer ;
; sld_sample_depth             ; 2048                                                                                                                                                                                        ; Untyped        ;
; sld_segment_size             ; 2048                                                                                                                                                                                        ; Untyped        ;
; sld_ram_block_type           ; AUTO                                                                                                                                                                                        ; String         ;
; sld_state_bits               ; 11                                                                                                                                                                                          ; Untyped        ;
; sld_buffer_full_stop         ; 1                                                                                                                                                                                           ; Untyped        ;
; sld_mem_address_bits         ; 7                                                                                                                                                                                           ; Signed Integer ;
; sld_data_bit_cntr_bits       ; 4                                                                                                                                                                                           ; Signed Integer ;
; sld_trigger_level            ; 1                                                                                                                                                                                           ; Untyped        ;
; sld_trigger_in_enabled       ; 1                                                                                                                                                                                           ; Untyped        ;
; sld_advanced_trigger_entity  ; basic,1,                                                                                                                                                                                    ; Untyped        ;
; sld_trigger_level_pipeline   ; 1                                                                                                                                                                                           ; Untyped        ;
; sld_enable_advanced_trigger  ; 0                                                                                                                                                                                           ; Untyped        ;
; sld_advanced_trigger_1       ; NONE                                                                                                                                                                                        ; String         ;
; sld_advanced_trigger_2       ; NONE                                                                                                                                                                                        ; String         ;
; sld_advanced_trigger_3       ; NONE                                                                                                                                                                                        ; String         ;
; sld_advanced_trigger_4       ; NONE                                                                                                                                                                                        ; String         ;
; sld_advanced_trigger_5       ; NONE                                                                                                                                                                                        ; String         ;
; sld_advanced_trigger_6       ; NONE                                                                                                                                                                                        ; String         ;
; sld_advanced_trigger_7       ; NONE                                                                                                                                                                                        ; String         ;
; sld_advanced_trigger_8       ; NONE                                                                                                                                                                                        ; String         ;
; sld_advanced_trigger_9       ; NONE                                                                                                                                                                                        ; String         ;
; sld_advanced_trigger_10      ; NONE                                                                                                                                                                                        ; String         ;
; sld_inversion_mask_length    ; 187                                                                                                                                                                                         ; Untyped        ;
; sld_inversion_mask           ; 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Untyped        ;
; sld_power_up_trigger         ; 0                                                                                                                                                                                           ; Untyped        ;
; sld_state_flow_mgr_entity    ; state_flow_mgr_entity.vhd                                                                                                                                                                   ; String         ;
; sld_state_flow_use_generated ; 0                                                                                                                                                                                           ; Untyped        ;
; sld_current_resource_width   ; 1                                                                                                                                                                                           ; Untyped        ;
+------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst         ;
+--------------------------+----------------------------------+-----------------+
; Parameter Name           ; Value                            ; Type            ;
+--------------------------+----------------------------------+-----------------+
; sld_hub_ip_version       ; 1                                ; Untyped         ;
; sld_hub_ip_minor_version ; 3                                ; Untyped         ;
; sld_common_ip_version    ; 0                                ; Untyped         ;
; device_family            ; Cyclone II                       ; Untyped         ;
; n_nodes                  ; 1                                ; Untyped         ;
; n_sel_bits               ; 1                                ; Untyped         ;
; n_node_ir_bits           ; 8                                ; Untyped         ;
; node_info                ; 00110000000000000110111000000000 ; Unsigned Binary ;
; compilation_mode         ; 1                                ; Untyped         ;
+--------------------------+----------------------------------+-----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component|add_sub_vmg:auto_generated|altshift_taps:pipeline_dffe_rtl_0 ;
+----------------+----------------+------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value          ; Type                                                                                                                                           ;
+----------------+----------------+------------------------------------------------------------------------------------------------------------------------------------------------+
; WIDTH_BYTEENA  ; 1              ; Untyped                                                                                                                                        ;
; NUMBER_OF_TAPS ; 1              ; Untyped                                                                                                                                        ;
; TAP_DISTANCE   ; 3              ; Untyped                                                                                                                                        ;
; WIDTH          ; 34             ; Untyped                                                                                                                                        ;
; POWER_UP_STATE ; CLEARED        ; Untyped                                                                                                                                        ;
; CBXI_PARAMETER ; shift_taps_5hp ; Untyped                                                                                                                                        ;
+----------------+----------------+------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------+
; scfifo Parameter Settings by Entity Instance                          ;
+----------------------------+------------------------------------------+
; Name                       ; Value                                    ;
+----------------------------+------------------------------------------+
; Number of entity instances ; 2                                        ;
; Entity Instance            ; lpm_fifo0:inst24|scfifo:scfifo_component ;
;     -- FIFO Type           ; Single Clock                             ;
;     -- lpm_width           ; 18                                       ;
;     -- LPM_NUMWORDS        ; 64                                       ;
;     -- LPM_SHOWAHEAD       ; OFF                                      ;
;     -- USE_EAB             ; ON                                       ;
; Entity Instance            ; lpm_fifo0:inst|scfifo:scfifo_component   ;
;     -- FIFO Type           ; Single Clock                             ;
;     -- lpm_width           ; 18                                       ;
;     -- LPM_NUMWORDS        ; 64                                       ;
;     -- LPM_SHOWAHEAD       ; OFF                                      ;
;     -- USE_EAB             ; ON                                       ;
+----------------------------+------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; altmult_add Parameter Settings by Entity Instance                                                                                                                            ;
+---------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+
; Name                                  ; Value                                                                                                                                ;
+---------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+
; Number of entity instances            ; 3                                                                                                                                    ;
; Entity Instance                       ; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1 ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                                                                                 ;
;     -- NUMBER_OF_MULTIPLIERS          ; 1                                                                                                                                    ;
;     -- port_signa                     ; PORT_CONNECTIVITY                                                                                                                    ;
;     -- port_signb                     ; PORT_CONNECTIVITY                                                                                                                    ;
;     -- REPRESENTATION_A               ; SIGNED                                                                                                                               ;
;     -- REPRESENTATION_B               ; SIGNED                                                                                                                               ;
;     -- WIDTH_A                        ; 17                                                                                                                                   ;
;     -- WIDTH_B                        ; 17                                                                                                                                   ;
;     -- WIDTH_RESULT                   ; 34                                                                                                                                   ;
; Entity Instance                       ; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add2 ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                                                                                 ;
;     -- NUMBER_OF_MULTIPLIERS          ; 1                                                                                                                                    ;
;     -- port_signa                     ; PORT_CONNECTIVITY                                                                                                                    ;
;     -- port_signb                     ; PORT_CONNECTIVITY                                                                                                                    ;
;     -- REPRESENTATION_A               ; SIGNED                                                                                                                               ;
;     -- REPRESENTATION_B               ; SIGNED                                                                                                                               ;
;     -- WIDTH_A                        ; 17                                                                                                                                   ;
;     -- WIDTH_B                        ; 17                                                                                                                                   ;
;     -- WIDTH_RESULT                   ; 34                                                                                                                                   ;
; Entity Instance                       ; butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6 ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                                                                                 ;
;     -- NUMBER_OF_MULTIPLIERS          ; 1                                                                                                                                    ;
;     -- port_signa                     ; PORT_CONNECTIVITY                                                                                                                    ;
;     -- port_signb                     ; PORT_CONNECTIVITY                                                                                                                    ;
;     -- REPRESENTATION_A               ; SIGNED                                                                                                                               ;
;     -- REPRESENTATION_B               ; SIGNED                                                                                                                               ;
;     -- WIDTH_A                        ; 18                                                                                                                                   ;
;     -- WIDTH_B                        ; 18                                                                                                                                   ;
;     -- WIDTH_RESULT                   ; 36                                                                                                                                   ;
+---------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; altshift_taps Parameter Settings by Entity Instance                                                                                                          ;
+----------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Name                       ; Value                                                                                                                           ;
+----------------------------+---------------------------------------------------------------------------------------------------------------------------------+
; Number of entity instances ; 1                                                                                                                               ;
; Entity Instance            ; butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component|add_sub_vmg:auto_generated|altshift_taps:pipeline_dffe_rtl_0 ;
;     -- NUMBER_OF_TAPS      ; 1                                                                                                                               ;
;     -- TAP_DISTANCE        ; 3                                                                                                                               ;
;     -- WIDTH               ; 34                                                                                                                              ;
+----------------------------+---------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SignalTap II Logic Analyzer Settings                                                                                                                                                                                                                        ;
+----------------+------------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+--------------------------+----------------------------+-------------------------+
; Instance Index ; Instance Name    ; Trigger Input Width ; Data Input Width ; Sample Depth ; Trigger Levels ; Advanced Trigger Levels ; Trigger In Used ; Trigger Out Used ; Power-Up Trigger Enabled ; Incremental Trigger Inputs ; Incremental Data Inputs ;
+----------------+------------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+--------------------------+----------------------------+-------------------------+
; 0              ; auto_signaltap_0 ; 54                  ; 54               ; 2048         ; 1              ; 0                       ; no              ; no               ; no                       ; 0                          ; 0                       ;
+----------------+------------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+--------------------------+----------------------------+-------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sun Jun 06 17:09:57 2010
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FFT -c FFT
Info: Found 1 design units, including 1 entities, in source file T_control.v
    Info: Found entity 1: T_control
Info: Found 1 design units, including 1 entities, in source file block.bdf
    Info: Found entity 1: block
Info: Found 1 design units, including 1 entities, in source file butterfly.v
    Info: Found entity 1: butterfly
Info: Found 1 design units, including 1 entities, in source file s2p.v
    Info: Found entity 1: s2p
Info: Found 1 design units, including 1 entities, in source file p2s.v
    Info: Found entity 1: p2s
Info: Found 1 design units, including 1 entities, in source file block_new.v
    Info: Found entity 1: block_new
Info: Found 1 design units, including 1 entities, in source file makeup_sign.v
    Info: Found entity 1: makeup_sign
Info: Found 2 design units, including 1 entities, in source file ctrl_fft.vhd
    Info: Found design unit 1: ctrl_fft-one
    Info: Found entity 1: ctrl_fft
Info: Found 2 design units, including 1 entities, in source file reset_ctrl.vhd
    Info: Found design unit 1: reset_ctrl-rtl
    Info: Found entity 1: reset_ctrl
Info: Elaborating entity "block" for the top level hierarchy
Info: Elaborating entity "T_control" for hierarchy "T_control:inst46"
Warning: Using design file lpm_ram_dq0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_ram_dq0
Info: Elaborating entity "lpm_ram_dq0" for hierarchy "T_control:inst46|lpm_ram_dq0:ram1"
Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "T_control:inst46|lpm_ram_dq0:ram1|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "T_control:inst46|lpm_ram_dq0:ram1|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_n4a1.tdf
    Info: Found entity 1: altsyncram_n4a1
Info: Elaborating entity "altsyncram_n4a1" for hierarchy "T_control:inst46|lpm_ram_dq0:ram1|altsyncram:altsyncram_component|altsyncram_n4a1:auto_generated"
Info: Elaborating entity "reset_ctrl" for hierarchy "reset_ctrl:inst5"
Info: Elaborating entity "ctrl_fft" for hierarchy "ctrl_fft:inst3"
Warning: Using design file lpm_fifo0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_fifo0
Info: Elaborating entity "lpm_fifo0" for hierarchy "lpm_fifo0:inst24"
Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/scfifo.tdf
    Info: Found entity 1: scfifo
Info: Elaborating entity "scfifo" for hierarchy "lpm_fifo0:inst24|scfifo:scfifo_component"
Info: Elaborated megafunction instantiation "lpm_fifo0:inst24|scfifo:scfifo_component"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_7r31.tdf
    Info: Found entity 1: scfifo_7r31
Info: Elaborating entity "scfifo_7r31" for hierarchy "lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_e141.tdf
    Info: Found entity 1: a_dpfifo_e141
Info: Elaborating entity "a_dpfifo_e141" for hierarchy "lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_b6f.tdf
    Info: Found entity 1: a_fefifo_b6f
Info: Elaborating entity "a_fefifo_b6f" for hierarchy "lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|a_fefifo_b6f:fifo_state"
Info: Found 1 design units, including 1 entities, in source file db/cntr_tk7.tdf
    Info: Found entity 1: cntr_tk7
Info: Elaborating entity "cntr_tk7" for hierarchy "lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|a_fefifo_b6f:fifo_state|cntr_tk7:count_usedw"
Info: Found 1 design units, including 1 entities, in source file db/dpram_fv01.tdf
    Info: Found entity 1: dpram_fv01
Info: Elaborating entity "dpram_fv01" for hierarchy "lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|dpram_fv01:FIFOram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_avj1.tdf
    Info: Found entity 1: altsyncram_avj1
Info: Elaborating entity "altsyncram_avj1" for hierarchy "lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|dpram_fv01:FIFOram|altsyncram_avj1:altsyncram1"
Info: Found 1 design units, including 1 entities, in source file db/cntr_fjb.tdf
    Info: Found entity 1: cntr_fjb
Info: Elaborating entity "cntr_fjb" for hierarchy "lpm_fifo0:inst24|scfifo:scfifo_component|scfifo_7r31:auto_generated|a_dpfifo_e141:dpfifo|cntr_fjb:rd_ptr_count"
Info: Elaborating entity "p2s" for hierarchy "p2s:inst28"
Info: Elaborating entity "butterfly" for hierarchy "butterfly:inst48"
Warning: Using design file ADD_17.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: ADD_17
Info: Elaborating entity "ADD_17" for hierarchy "butterfly:inst48|ADD_17:add_real"
Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Elaborating entity "lpm_add_sub" for hierarchy "butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component"
Info: Elaborated megafunction instantiation "butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_vmg.tdf
    Info: Found entity 1: add_sub_vmg
Info: Elaborating entity "add_sub_vmg" for hierarchy "butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component|add_sub_vmg:auto_generated"
Warning: Using design file SUB_17.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: SUB_17
Info: Elaborating entity "SUB_17" for hierarchy "butterfly:inst48|SUB_17:sub_real"
Info: Elaborating entity "lpm_add_sub" for hierarchy "butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component"
Info: Elaborated megafunction instantiation "butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_4qe.tdf
    Info: Found entity 1: add_sub_4qe
Info: Elaborating entity "add_sub_4qe" for hierarchy "butterfly:inst48|SUB_17:sub_real|lpm_add_sub:lpm_add_sub_component|add_sub_4qe:auto_generated"
Warning: Clear box output file C:/Documents and Settings/wangwei/桌面/FFT last edition/complex_mult.v is not compatible with the current compile. Used regenerated output file C:/Documents and Settings/wangwei/桌面/FFT last edition/db/complex_mult.v for elaboration
Info: Found 2 design units, including 2 entities, in source file db/complex_mult.v
    Info: Found entity 1: complex_mult_altmult_complex_q5p
    Info: Found entity 2: complex_mult
Info: Elaborating entity "complex_mult" for hierarchy "butterfly:inst48|complex_mult:mult"
Info: Elaborating entity "complex_mult_altmult_complex_q5p" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component"
Warning (10036): Verilog HDL or VHDL warning at complex_mult.v(68): object "dffe5a" assigned a value but never read
Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/altmult_add.tdf
    Info: Found entity 1: altmult_add
Info: Elaborating entity "altmult_add" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1"
Info: Elaborated megafunction instantiation "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1"
Info: Found 1 design units, including 1 entities, in source file db/mult_add_dqa1.tdf
    Info: Found entity 1: mult_add_dqa1
Info: Elaborating entity "mult_add_dqa1" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1|mult_add_dqa1:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/ded_mult_1t51.tdf
    Info: Found entity 1: ded_mult_1t51
Info: Elaborating entity "ded_mult_1t51" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1|mult_add_dqa1:auto_generated|ded_mult_1t51:ded_mult1"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_b3c.tdf
    Info: Found entity 1: dffpipe_b3c
Info: Elaborating entity "dffpipe_b3c" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1|mult_add_dqa1:auto_generated|ded_mult_1t51:ded_mult1|dffpipe_b3c:pre_result"
Info: Elaborating entity "altmult_add" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6"
Info: Elaborated megafunction instantiation "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6"
Info: Found 1 design units, including 1 entities, in source file db/mult_add_ie81.tdf
    Info: Found entity 1: mult_add_ie81
Info: Elaborating entity "mult_add_ie81" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6|mult_add_ie81:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/ded_mult_2a21.tdf
    Info: Found entity 1: ded_mult_2a21
Info: Elaborating entity "ded_mult_2a21" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6|mult_add_ie81:auto_generated|ded_mult_2a21:ded_mult1"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_d3c.tdf
    Info: Found entity 1: dffpipe_d3c
Info: Elaborating entity "dffpipe_d3c" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6|mult_add_ie81:auto_generated|ded_mult_2a21:ded_mult1|dffpipe_d3c:pre_result"
Info: Elaborating entity "lpm_add_sub" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:add_sub7"
Info: Elaborated megafunction instantiation "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:add_sub7"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_esf.tdf
    Info: Found entity 1: add_sub_esf
Info: Elaborating entity "add_sub_esf" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:add_sub7|add_sub_esf:auto_generated"
Warning: Variable or input pin "aclr" is defined but never used
Warning: Variable or input pin "clken" is defined but never used
Info: Elaborating entity "lpm_add_sub" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder1"
Info: Elaborated megafunction instantiation "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder1"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_5ii.tdf
    Info: Found entity 1: add_sub_5ii
Info: Elaborating entity "add_sub_5ii" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder1|add_sub_5ii:auto_generated"
Warning: Variable or input pin "aclr" is defined but never used
Warning: Variable or input pin "clken" is defined but never used
Info: Elaborating entity "lpm_add_sub" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder2"
Info: Elaborated megafunction instantiation "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder2"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_6ii.tdf
    Info: Found entity 1: add_sub_6ii
Info: Elaborating entity "add_sub_6ii" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder2|add_sub_6ii:auto_generated"
Warning: Variable or input pin "aclr" is defined but never used
Warning: Variable or input pin "clken" is defined but never used
Info: Elaborating entity "lpm_add_sub" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1"
Info: Elaborated megafunction instantiation "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_6ji.tdf
    Info: Found entity 1: add_sub_6ji
Info: Elaborating entity "add_sub_6ji" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor1|add_sub_6ji:auto_generated"
Warning: Variable or input pin "aclr" is defined but never used
Warning: Variable or input pin "clken" is defined but never used
Info: Elaborating entity "lpm_add_sub" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor2"
Info: Elaborated megafunction instantiation "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor2"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_5ji.tdf
    Info: Found entity 1: add_sub_5ji
Info: Elaborating entity "add_sub_5ji" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor2|add_sub_5ji:auto_generated"
Warning: Variable or input pin "aclr" is defined but never used
Warning: Variable or input pin "clken" is defined but never used
Info: Elaborating entity "lpm_add_sub" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor3"
Info: Elaborated megafunction instantiation "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor3"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_i5j.tdf
    Info: Found entity 1: add_sub_i5j
Info: Elaborating entity "add_sub_i5j" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor3|add_sub_i5j:auto_generated"
Warning: Variable or input pin "aclr" is defined but never used
Warning: Variable or input pin "clken" is defined but never used
Warning: Variable or input pin "dataa" is defined but never used
Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/lpm_compare.tdf
    Info: Found entity 1: lpm_compare
Info: Elaborating entity "lpm_compare" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_compare:comparator1"
Info: Elaborated megafunction instantiation "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_compare:comparator1"
Info: Found 1 design units, including 1 entities, in source file db/cmpr_1cg.tdf
    Info: Found entity 1: cmpr_1cg
Info: Elaborating entity "cmpr_1cg" for hierarchy "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_compare:comparator1|cmpr_1cg:auto_generated"
Info: Elaborating entity "s2p" for hierarchy "s2p:inst6"
Warning: Using design file D.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: D
Info: Elaborating entity "D" for hierarchy "D:inst16"
Warning: Using design file lpm_rom1.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_rom1
Info: Elaborating entity "lpm_rom1" for hierarchy "lpm_rom1:inst2"
Info: Elaborating entity "altsyncram" for hierarchy "lpm_rom1:inst2|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "lpm_rom1:inst2|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_qq71.tdf
    Info: Found entity 1: altsyncram_qq71
Info: Elaborating entity "altsyncram_qq71" for hierarchy "lpm_rom1:inst2|altsyncram:altsyncram_component|altsyncram_qq71:auto_generated"
Warning: Using design file lpm_rom0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_rom0
Info: Elaborating entity "lpm_rom0" for hierarchy "lpm_rom0:inst1"
Info: Elaborating entity "altsyncram" for hierarchy "lpm_rom0:inst1|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "lpm_rom0:inst1|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_oh91.tdf
    Info: Found entity 1: altsyncram_oh91
Info: Elaborating entity "altsyncram_oh91" for hierarchy "lpm_rom0:inst1|altsyncram:altsyncram_component|altsyncram_oh91:auto_generated"
Info: Elaborating entity "makeup_sign" for hierarchy "makeup_sign:inst32"
Warning: Using design file lpm_rom2.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_rom2
Info: Elaborating entity "lpm_rom2" for hierarchy "lpm_rom2:inst19"
Info: Elaborating entity "altsyncram" for hierarchy "lpm_rom2:inst19|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "lpm_rom2:inst19|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_kfa1.tdf
    Info: Found entity 1: altsyncram_kfa1
Info: Elaborating entity "altsyncram_kfa1" for hierarchy "lpm_rom2:inst19|altsyncram:altsyncram_component|altsyncram_kfa1:auto_generated"
Warning: Using design file lpm_counter0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_counter0
Info: Elaborating entity "lpm_counter0" for hierarchy "lpm_counter0:inst4"
Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborating entity "lpm_counter" for hierarchy "lpm_counter0:inst4|lpm_counter:lpm_counter_component"
Info: Elaborated megafunction instantiation "lpm_counter0:inst4|lpm_counter:lpm_counter_component"
Info: Found 1 design units, including 1 entities, in source file db/cntr_qkh.tdf
    Info: Found entity 1: cntr_qkh
Info: Elaborating entity "cntr_qkh" for hierarchy "lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_qkh:auto_generated"
Info: Elaborating entity "block_new" for hierarchy "block_new:inst45"
Info: Found 7 design units, including 2 entities, in source file e:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd
    Info: Found design unit 1: sld_signaltap_pack
    Info: Found design unit 2: sld_signaltap_lib
    Info: Found design unit 3: sld_signaltap_lib-body
    Info: Found design unit 4: sld_signaltap-rtl
    Info: Found design unit 5: sld_signaltap_impl-rtl
    Info: Found entity 1: sld_signaltap
    Info: Found entity 2: sld_signaltap_impl
Info: Found 4 design units, including 2 entities, in source file e:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd
    Info: Found design unit 1: sld_ela_control-rtl
    Info: Found design unit 2: sld_ela_basic_multi_level_trigger-rtl
    Info: Found entity 1: sld_ela_control
    Info: Found entity 2: sld_ela_basic_multi_level_trigger
Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf
    Info: Found entity 1: lpm_shiftreg
Info: Found 4 design units, including 2 entities, in source file e:/altera/72/quartus/libraries/megafunctions/sld_mbpmg.vhd
    Info: Found design unit 1: sld_mbpmg-rtl
    Info: Found design unit 2: sld_sbpmg-rtl
    Info: Found entity 1: sld_mbpmg
    Info: Found entity 2: sld_sbpmg
Info: Found 2 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd
    Info: Found design unit 1: sld_ela_trigger_flow_mgr-rtl
    Info: Found entity 1: sld_ela_trigger_flow_mgr
Info: Found 4 design units, including 2 entities, in source file e:/altera/72/quartus/libraries/megafunctions/sld_buffer_manager.vhd
    Info: Found design unit 1: sld_buffer_manager-rtl
    Info: Found design unit 2: sld_offload_buffer_mgr-rtl
    Info: Found entity 1: sld_buffer_manager
    Info: Found entity 2: sld_offload_buffer_mgr
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_i7p3.tdf
    Info: Found entity 1: altsyncram_i7p3
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ugq1.tdf
    Info: Found entity 1: altsyncram_ugq1
Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/altdpram.tdf
    Info: Found entity 1: altdpram
Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/lpm_mux.tdf
    Info: Found entity 1: lpm_mux
Info: Found 1 design units, including 1 entities, in source file db/mux_9oc.tdf
    Info: Found entity 1: mux_9oc
Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/lpm_decode.tdf
    Info: Found entity 1: lpm_decode
Info: Found 1 design units, including 1 entities, in source file db/decode_rqf.tdf
    Info: Found entity 1: decode_rqf
Info: Found 1 design units, including 1 entities, in source file db/cntr_fbi.tdf
    Info: Found entity 1: cntr_fbi
Info: Found 1 design units, including 1 entities, in source file db/cntr_c4j.tdf
    Info: Found entity 1: cntr_c4j
Info: Found 1 design units, including 1 entities, in source file db/cntr_bbi.tdf
    Info: Found entity 1: cntr_bbi
Info: Found 1 design units, including 1 entities, in source file db/cntr_uti.tdf
    Info: Found entity 1: cntr_uti
Info: Found 2 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd
    Info: Found design unit 1: sld_rom_sr-INFO_REG
    Info: Found entity 1: sld_rom_sr
Info: Analysis and Synthesis generated SignalTap II or debug node instance "auto_signaltap_0"
Info: Duplicate registers merged to single register
    Info: Duplicate register "p2s:inst28|cnt" merged to single register "p2s:inst13|cnt"
    Info: Duplicate register "s2p:inst6|cnt" merged to single register "s2p:inst7|cnt"
    Info: Duplicate register "butterfly:inst48|real_a[15]" merged to single register "butterfly:inst48|real_a[16]"
    Info: Duplicate register "butterfly:inst48|imag_a[15]" merged to single register "butterfly:inst48|imag_a[16]"
    Info: Duplicate register "butterfly:inst48|real_b[15]" merged to single register "butterfly:inst48|real_b[16]"
    Info: Duplicate register "butterfly:inst48|imag_b[15]" merged to single register "butterfly:inst48|imag_b[16]"
    Info: Duplicate register "butterfly:inst48|real_WN_in[15]" merged to single register "butterfly:inst48|real_WN_in[16]"
    Info: Duplicate register "butterfly:inst48|imag_WN_in[15]" merged to single register "butterfly:inst48|imag_WN_in[16]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "s2p:inst6|count[6]" merged to single register "s2p:inst7|count[6]"
    Info: Duplicate register "s2p:inst6|count[5]" merged to single register "s2p:inst7|count[5]"
    Info: Duplicate register "s2p:inst6|count[4]" merged to single register "s2p:inst7|count[4]"
    Info: Duplicate register "s2p:inst6|count[3]" merged to single register "s2p:inst7|count[3]"
    Info: Duplicate register "s2p:inst6|count[2]" merged to single register "s2p:inst7|count[2]"
    Info: Duplicate register "s2p:inst6|count[1]" merged to single register "s2p:inst7|count[1]"
    Info: Duplicate register "s2p:inst6|count[0]" merged to single register "s2p:inst7|count[0]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "p2s:inst13|data_temp[0][16]" merged to single register "p2s:inst13|data_temp[0][17]"
    Info: Duplicate register "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder1|add_sub_5ii:auto_generated|pipeline_dffe[16]" merged to single register "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:adder1|add_sub_5ii:auto_generated|pipeline_dffe[17]"
    Info: Duplicate register "p2s:inst28|data_temp[0][16]" merged to single register "p2s:inst28|data_temp[0][17]"
Info: State machine "|block|block_new:inst45|current_state" contains 3 states
Info: State machine "|block|butterfly:inst48|current_state" contains 2 states
Info: State machine "|block|ctrl_fft:inst3|current_state" contains 4 states
Info: State machine "|block|T_control:inst46|current_state" contains 6 states
Info: Selected Auto state machine encoding method for state machine "|block|block_new:inst45|current_state"
Info: Encoding result for state machine "|block|block_new:inst45|current_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "block_new:inst45|current_state.s0"
        Info: Encoded state bit "block_new:inst45|current_state.s2"
        Info: Encoded state bit "block_new:inst45|current_state.s1"
    Info: State "|block|block_new:inst45|current_state.s0" uses code string "000"
    Info: State "|block|block_new:inst45|current_state.s1" uses code string "101"
    Info: State "|block|block_new:inst45|current_state.s2" uses code string "110"
Info: Selected Auto state machine encoding method for state machine "|block|butterfly:inst48|current_state"
Info: Encoding result for state machine "|block|butterfly:inst48|current_state"
    Info: Completed encoding using 1 state bits
        Info: Encoded state bit "butterfly:inst48|current_state.work"
    Info: State "|block|butterfly:inst48|current_state.idle" uses code string "0"
    Info: State "|block|butterfly:inst48|current_state.work" uses code string "1"
Info: Selected Auto state machine encoding method for state machine "|block|ctrl_fft:inst3|current_state"
Info: Encoding result for state machine "|block|ctrl_fft:inst3|current_state"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "ctrl_fft:inst3|current_state.wait_state"
        Info: Encoded state bit "ctrl_fft:inst3|current_state.assert_eop"
        Info: Encoded state bit "ctrl_fft:inst3|current_state.go"
        Info: Encoded state bit "ctrl_fft:inst3|current_state.idle"
    Info: State "|block|ctrl_fft:inst3|current_state.idle" uses code string "0000"
    Info: State "|block|ctrl_fft:inst3|current_state.go" uses code string "0011"
    Info: State "|block|ctrl_fft:inst3|current_state.assert_eop" uses code string "0101"
    Info: State "|block|ctrl_fft:inst3|current_state.wait_state" uses code string "1001"
Info: Selected Auto state machine encoding method for state machine "|block|T_control:inst46|current_state"
Info: Encoding result for state machine "|block|T_control:inst46|current_state"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "T_control:inst46|current_state.Pro_write"
        Info: Encoded state bit "T_control:inst46|current_state.source"
        Info: Encoded state bit "T_control:inst46|current_state.Wait"
        Info: Encoded state bit "T_control:inst46|current_state.Pro_read"
        Info: Encoded state bit "T_control:inst46|current_state.sink"
        Info: Encoded state bit "T_control:inst46|current_state.idle"
    Info: State "|block|T_control:inst46|current_state.idle" uses code string "000000"
    Info: State "|block|T_control:inst46|current_state.sink" uses code string "000011"
    Info: State "|block|T_control:inst46|current_state.Pro_read" uses code string "000101"
    Info: State "|block|T_control:inst46|current_state.Wait" uses code string "001001"
    Info: State "|block|T_control:inst46|current_state.source" uses code string "010001"
    Info: State "|block|T_control:inst46|current_state.Pro_write" uses code string "100001"
Info: Duplicate registers merged to single register
    Info: Duplicate register "ctrl_fft:inst3|current_state.assert_eop" merged to single register "ctrl_fft:inst3|sink_eop"
Info: Inferred 1 megafunctions from design logic
    Info: Inferred altshift_taps megafunction from the following design logic: "butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component|add_sub_vmg:auto_generated|pipeline_dffe[32]~68"
        Info: Parameter NUMBER_OF_TAPS set to 1
        Info: Parameter TAP_DISTANCE set to 3
        Info: Parameter WIDTH set to 34
Warning (14130): Reduced register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_uti:auto_generated|current_reg_q_w[0]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|xraddr[0]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[0]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[0]"
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[1]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[1]"
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[2]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[2]"
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[3]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[3]"
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[4]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[4]"
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[5]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[5]"
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[6]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[6]"
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[7]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[7]"
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[8]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[8]"
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[9]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[9]"
    Info: Duplicate register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[10]" merged to single register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[10]"
Info: State machine "|block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state" contains 11 states
Info: Selected Auto state machine encoding method for state machine "|block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state"
Info: State machine "|block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state" will be implemented as a safe state machine.
Info: Encoding result for state machine "|block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state"
    Info: Completed encoding using 11 state bits
        Info: Encoded state bit "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s10"
        Info: Encoded state bit "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s9"
        Info: Encoded state bit "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s8"
        Info: Encoded state bit "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s7"
        Info: Encoded state bit "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s6"
        Info: Encoded state bit "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s5"
        Info: Encoded state bit "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s4"
        Info: Encoded state bit "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s3"
        Info: Encoded state bit "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s2"
        Info: Encoded state bit "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s1"
        Info: Encoded state bit "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s0"
    Info: State "|block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s0" uses code string "00000000000"
    Info: State "|block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s1" uses code string "00000000011"
    Info: State "|block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s2" uses code string "00000000101"
    Info: State "|block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s3" uses code string "00000001001"
    Info: State "|block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s4" uses code string "00000010001"
    Info: State "|block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s5" uses code string "00000100001"
    Info: State "|block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s6" uses code string "00001000001"
    Info: State "|block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s7" uses code string "00010000001"
    Info: State "|block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s8" uses code string "00100000001"
    Info: State "|block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s9" uses code string "01000000001"
    Info: State "|block|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s10" uses code string "10000000001"
Warning (14130): Reduced register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s2" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s3" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s4" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s5" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s6" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s7" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s8" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s9" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state.s10" with stuck data_in port to stuck value GND
Info: Found 1 design units, including 1 entities, in source file e:/altera/72/quartus/libraries/megafunctions/altshift_taps.tdf
    Info: Found entity 1: altshift_taps
Info: Elaborated megafunction instantiation "butterfly:inst48|ADD_17:add_real|lpm_add_sub:lpm_add_sub_component|add_sub_vmg:auto_generated|altshift_taps:pipeline_dffe_rtl_0"
Info: Found 1 design units, including 1 entities, in source file db/shift_taps_5hp.tdf
    Info: Found entity 1: shift_taps_5hp
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_hg31.tdf
    Info: Found entity 1: altsyncram_hg31
Info: Found 1 design units, including 1 entities, in source file db/add_sub_gvd.tdf
    Info: Found entity 1: add_sub_gvd
Info: Found 1 design units, including 1 entities, in source file db/cntr_kkf.tdf
    Info: Found entity 1: cntr_kkf
Info: 13 registers lost all their fanouts during netlist optimizations. The first 13 are displayed below.
    Info: Register "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor3|add_sub_i5j:auto_generated|pipeline_dffe[34]" lost all its fanouts during netlist optimizations.
    Info: Register "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6|mult_add_ie81:auto_generated|dffe2a[34]" lost all its fanouts during netlist optimizations.
    Info: Register "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor3|add_sub_i5j:auto_generated|pipeline_dffe[33]" lost all its fanouts during netlist optimizations.
    Info: Register "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6|mult_add_ie81:auto_generated|dffe2a[33]" lost all its fanouts during netlist optimizations.
    Info: Register "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor2|add_sub_5ji:auto_generated|pipeline_dffe[34]" lost all its fanouts during netlist optimizations.
    Info: Register "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|lpm_add_sub:subtractor2|add_sub_5ji:auto_generated|pipeline_dffe[33]" lost all its fanouts during netlist optimizations.
    Info: Register "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add6|mult_add_ie81:auto_generated|dffe2a[35]" lost all its fanouts during netlist optimizations.
    Info: Register "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add2|mult_add_dqa1:auto_generated|dffe2a[33]" lost all its fanouts during netlist optimizations.
    Info: Register "butterfly:inst48|complex_mult:mult|complex_mult_altmult_complex_q5p:complex_mult_altmult_complex_q5p_component|altmult_add:mult_add1|mult_add_dqa1:auto_generated|dffe2a[33]" lost all its fanouts during netlist optimizations.
    Info: Register "butterfly:inst48|current_state~15" lost all its fanouts during netlist optimizations.
    Info: Register "T_control:inst46|current_state~14" lost all its fanouts during netlist optimizations.
    Info: Register "T_control:inst46|current_state~15" lost all its fanouts during netlist optimizations.
    Info: Register "T_control:inst46|current_state~16" lost all its fanouts during netlist optimizations.
Info: Found the following redundant logic cells in design
Info: Registers with preset signals will power-up high
Warning: NOT_GATE_PUSH_BACK-forbidden assignments are ignored
    Warning: NOT_GATE_PUSH_BACK performed on sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[0]
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Critical Warning: Ignored Power-Up Level option on the following registers
    Critical Warning: Register sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[0] will power up to High
    Critical Warning: Register sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[5] will power up to High
    Critical Warning: Register sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[6] will power up to High
    Critical Warning: Register sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[2] will power up to High
    Critical Warning: Register sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[10] will power up to High
    Critical Warning: Register sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[4] will power up to High
    Critical Warning: Register sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[7] will power up to High
    Critical Warning: Register sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[8] will power up to High
    Critical Warning: Register sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[1] will power up to High
    Critical Warning: Register sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[11] will power up to High
    Critical Warning: Register sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[9] will power up to High
    Critical Warning: Register sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[3] will power up to High
Info: 23 registers lost all their fanouts during netlist optimizations. The first 23 are displayed below.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][22]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][21]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][20]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][19]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][18]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][17]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][16]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][15]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][14]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][13]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][12]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][11]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][10]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][9]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][8]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][7]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][6]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][5]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][4]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][3]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][2]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][1]" lost all its fanouts during netlist optimizations.
    Info: Register "sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem|cells[1][0]" lost all its fanouts during netlist optimizations.
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Generated suppressed messages file C:/Documents and Settings/wangwei/桌面/FFT last edition/FFT.map.smsg
Info: Implemented 2639 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 54 output pins
    Info: Implemented 2365 logic cells
    Info: Implemented 208 RAM segments
    Info: Implemented 6 DSP elements
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 50 warnings
    Info: Allocated 202 megabytes of memory during processing
    Info: Processing ended: Sun Jun 06 17:12:22 2010
    Info: Elapsed time: 00:02:25


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in C:/Documents and Settings/wangwei/桌面/FFT last edition/FFT.map.smsg.


