--alt_u_div DEVICE_FAMILY="Stratix II" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=4 WIDTH_N=4 WIDTH_Q=4 WIDTH_R=4 denominator numerator quotient remainder
--VERSION_BEGIN 7.2 cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
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--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
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--  applicable agreement for further details.



--synthesis_resources = lut 14 
SUBDESIGN alt_u_div_i0f
( 
	den_out[3..0]	:	output;
	denominator[3..0]	:	input;
	numerator[3..0]	:	input;
	quotient[3..0]	:	output;
	remainder[3..0]	:	output;
) 
VARIABLE
	add_sub_0_result_int[1..0]	:	WIRE;
	add_sub_0_cout	:	WIRE;
	add_sub_0_dataa[0..0]	:	WIRE;
	add_sub_0_datab[0..0]	:	WIRE;
	add_sub_0_result[0..0]	:	WIRE;
	add_sub_1_result_int[2..0]	:	WIRE;
	add_sub_1_cout	:	WIRE;
	add_sub_1_dataa[1..0]	:	WIRE;
	add_sub_1_datab[1..0]	:	WIRE;
	add_sub_1_result[1..0]	:	WIRE;
	add_sub_2_result_int[3..0]	:	WIRE;
	add_sub_2_cout	:	WIRE;
	add_sub_2_dataa[2..0]	:	WIRE;
	add_sub_2_datab[2..0]	:	WIRE;
	add_sub_2_result[2..0]	:	WIRE;
	add_sub_3_result_int[4..0]	:	WIRE;
	add_sub_3_cout	:	WIRE;
	add_sub_3_dataa[3..0]	:	WIRE;
	add_sub_3_datab[3..0]	:	WIRE;
	add_sub_3_result[3..0]	:	WIRE;
	DenominatorIn[24..0]	: WIRE;
	DenominatorIn_tmp[24..0]	: WIRE;
	gnd_wire	: WIRE;
	nose[19..0]	: WIRE;
	NumeratorIn[19..0]	: WIRE;
	NumeratorIn_tmp[19..0]	: WIRE;
	prestg[15..0]	: WIRE;
	quotient_tmp[3..0]	: WIRE;
	sel[19..0]	: WIRE;
	selnose[19..0]	: WIRE;
	StageIn[19..0]	: WIRE;
	StageIn_tmp[19..0]	: WIRE;
	StageOut[15..0]	: WIRE;

BEGIN 
	add_sub_0_result_int[] = (0, add_sub_0_dataa[]) - (0, add_sub_0_datab[]);
	add_sub_0_result[] = add_sub_0_result_int[0..0];
	add_sub_0_cout = !add_sub_0_result_int[1];
	add_sub_0_dataa[] = NumeratorIn[3..3];
	add_sub_0_datab[] = DenominatorIn[0..0];
	add_sub_1_result_int[] = (0, add_sub_1_dataa[]) - (0, add_sub_1_datab[]);
	add_sub_1_result[] = add_sub_1_result_int[1..0];
	add_sub_1_cout = !add_sub_1_result_int[2];
	add_sub_1_dataa[] = ( StageIn[4..4], NumeratorIn[6..6]);
	add_sub_1_datab[] = DenominatorIn[6..5];
	add_sub_2_result_int[] = (0, add_sub_2_dataa[]) - (0, add_sub_2_datab[]);
	add_sub_2_result[] = add_sub_2_result_int[2..0];
	add_sub_2_cout = !add_sub_2_result_int[3];
	add_sub_2_dataa[] = ( StageIn[9..8], NumeratorIn[9..9]);
	add_sub_2_datab[] = DenominatorIn[12..10];
	add_sub_3_result_int[] = (0, add_sub_3_dataa[]) - (0, add_sub_3_datab[]);
	add_sub_3_result[] = add_sub_3_result_int[3..0];
	add_sub_3_cout = !add_sub_3_result_int[4];
	add_sub_3_dataa[] = ( StageIn[14..12], NumeratorIn[12..12]);
	add_sub_3_datab[] = DenominatorIn[18..15];
	den_out[3..0] = DenominatorIn[18..15];
	DenominatorIn[] = (gnd_wire # DenominatorIn_tmp[]);
	DenominatorIn_tmp[] = ( DenominatorIn[19..0], ( gnd_wire, denominator[]));
	gnd_wire = B"0";
	nose[] = ( B"0000", (add_sub_3_cout # gnd_wire), B"0000", (add_sub_2_cout # gnd_wire), B"0000", (add_sub_1_cout # gnd_wire), B"0000", (add_sub_0_cout # gnd_wire));
	NumeratorIn[] = (gnd_wire # NumeratorIn_tmp[]);
	NumeratorIn_tmp[] = ( NumeratorIn[15..0], numerator[]);
	prestg[] = ( add_sub_3_result[], GND, add_sub_2_result[], B"00", add_sub_1_result[], B"000", add_sub_0_result[]);
	quotient[] = quotient_tmp[];
	quotient_tmp[] = ( (! selnose[0..0]), (! selnose[5..5]), (! selnose[10..10]), (! selnose[15..15]));
	remainder[3..0] = StageIn[19..16];
	sel[] = ( gnd_wire, (gnd_wire # (sel[19..19] # DenominatorIn[23..23])), (gnd_wire # (sel[18..18] # DenominatorIn[22..22])), (gnd_wire # (sel[17..17] # DenominatorIn[21..21])), gnd_wire, (gnd_wire # (sel[15..15] # DenominatorIn[18..18])), (gnd_wire # (sel[14..14] # DenominatorIn[17..17])), (gnd_wire # (sel[13..13] # DenominatorIn[16..16])), gnd_wire, (gnd_wire # (sel[11..11] # DenominatorIn[13..13])), (gnd_wire # (sel[10..10] # DenominatorIn[12..12])), (gnd_wire # (sel[9..9] # DenominatorIn[11..11])), gnd_wire, (gnd_wire # (sel[7..7] # DenominatorIn[8..8])), (gnd_wire # (sel[6..6] # DenominatorIn[7..7])), (gnd_wire # (sel[5..5] # DenominatorIn[6..6])), gnd_wire, (gnd_wire # (sel[3..3] # DenominatorIn[3..3])), (gnd_wire # (sel[2..2] # DenominatorIn[2..2])), (gnd_wire # (sel[1..1] # DenominatorIn[1..1])));
	selnose[] = ( ((gnd_wire # (! nose[19..19])) # sel[19..19]), ((gnd_wire # (! nose[18..18])) # sel[18..18]), ((gnd_wire # (! nose[17..17])) # sel[17..17]), ((gnd_wire # (! nose[16..16])) # sel[16..16]), ((gnd_wire # (! nose[15..15])) # sel[15..15]), ((gnd_wire # (! nose[14..14])) # sel[14..14]), ((gnd_wire # (! nose[13..13])) # sel[13..13]), ((gnd_wire # (! nose[12..12])) # sel[12..12]), ((gnd_wire # (! nose[11..11])) # sel[11..11]), ((gnd_wire # (! nose[10..10])) # sel[10..10]), ((gnd_wire # (! nose[9..9])) # sel[9..9]), ((gnd_wire # (! nose[8..8])) # sel[8..8]), ((gnd_wire # (! nose[7..7])) # sel[7..7]), ((gnd_wire # (! nose[6..6])) # sel[6..6]), ((gnd_wire # (! nose[5..5])) # sel[5..5]), ((gnd_wire # (! nose[4..4])) # sel[4..4]), ((gnd_wire # (! nose[3..3])) # sel[3..3]), ((gnd_wire # (! nose[2..2])) # sel[2..2]), ((gnd_wire # (! nose[1..1])) # sel[1..1]), ((gnd_wire # (! nose[0..0])) # sel[0..0]));
	StageIn[] = (gnd_wire # StageIn_tmp[]);
	StageIn_tmp[] = ( StageOut[15..0], B"0000");
	StageOut[] = ( ((( StageIn[14..12], NumeratorIn[12..12]) & selnose[15..15]) # (prestg[15..12] & (! selnose[15..15]))), ((( StageIn[10..8], NumeratorIn[9..9]) & selnose[10..10]) # (prestg[11..8] & (! selnose[10..10]))), ((( StageIn[6..4], NumeratorIn[6..6]) & selnose[5..5]) # (prestg[7..4] & (! selnose[5..5]))), ((( StageIn[2..0], NumeratorIn[3..3]) & selnose[0..0]) # (prestg[3..0] & (! selnose[0..0]))));
END;
--VALID FILE
