--altmult_add CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" DSP_BLOCK_BALANCING="Auto" INPUT_ACLR_A0="ACLR0" INPUT_ACLR_B0="ACLR0" INPUT_REGISTER_A0="CLOCK0" INPUT_REGISTER_B0="CLOCK0" MULTIPLIER_REGISTER0="UNREGISTERED" NUMBER_OF_MULTIPLIERS=1 OUTPUT_ACLR="ACLR0" OUTPUT_REGISTER="CLOCK0" REPRESENTATION_A="SIGNED" REPRESENTATION_B="SIGNED" WIDTH_A=17 WIDTH_B=17 WIDTH_RESULT=34 clock0 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 7.2 cbx_alt_ded_mult_y 2007:03:05:16:04:08:SJ cbx_altmult_add 2007:08:27:13:54:20:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_mult 2007:07:20:16:47:26:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_padd 2007:07:12:14:48:24:SJ cbx_parallel_add 2007:01:30:03:53:08:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ  VERSION_END


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FUNCTION ded_mult_1t51 (aclr[3..0], clock[3..0], dataa[16..0], datab[16..0], ena[3..0])
RETURNS ( result[33..0]);

--synthesis_resources = dsp_9bit 2 reg 34 
SUBDESIGN mult_add_dqa1
( 
	clock0	:	input;
	dataa[16..0]	:	input;
	datab[16..0]	:	input;
	result[33..0]	:	output;
) 
VARIABLE 
	ded_mult1 : ded_mult_1t51;
	dffe2a[33..0] : dffe;
	aclr0	: NODE;
	dataa_bus[16..0]	: WIRE;
	datab_bus[16..0]	: WIRE;
	ena0	: NODE;
	pre_result[33..0]	: WIRE;

BEGIN 
	ded_mult1.aclr[] = ( B"000", aclr0);
	ded_mult1.clock[] = ( B"111", clock0);
	ded_mult1.dataa[] = ( dataa_bus[16..0]);
	ded_mult1.datab[] = ( datab_bus[16..0]);
	ded_mult1.ena[] = ( B"111", ena0);
	dffe2a[].clk = clock0;
	dffe2a[].clrn = (! aclr0);
	dffe2a[].d = pre_result[];
	dffe2a[].ena = ena0;
	aclr0 = GND;
	dataa_bus[] = ( dataa[16..0]);
	datab_bus[] = ( datab[16..0]);
	ena0 = VCC;
	pre_result[33..0] = ded_mult1.result[33..0];
	result[33..0] = dffe2a[33..0].q;
END;
--VALID FILE
