<session jtag_chain="USB-Blaster [USB-0]" jtag_device="@1: EP2C8 (0x020B20DD)" sof_file="FFT.sof" top_level_entity="block">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <mnemonics/>
  <static_plugin_mnemonics/>
  <instance compilation_mode="full" entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
    <signal_set is_expanded="true" name="signal_set: 2010/06/05 21:12:02  #0">
      <clock name="clk" polarity="posedge" tap_mode="probeonly"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="2048" trigger_in_enable="yes" trigger_in_pin="auto_stp_trigger_in_0" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire name="Imagdata_out[0]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[10]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[11]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[12]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[13]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[14]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[15]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[1]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[2]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[3]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[4]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[5]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[6]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[7]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[8]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[9]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[0]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[10]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[11]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[12]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[13]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[14]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[15]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[1]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[2]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[3]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[4]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[5]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[6]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[7]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[8]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[9]" tap_mode="classic" type="output pin"/>
          <wire name="aclr" tap_mode="classic" type="input pin"/>
          <wire name="sin[0]" tap_mode="classic" type="output pin"/>
          <wire name="sin[10]" tap_mode="classic" type="output pin"/>
          <wire name="sin[11]" tap_mode="classic" type="output pin"/>
          <wire name="sin[12]" tap_mode="classic" type="output pin"/>
          <wire name="sin[13]" tap_mode="classic" type="output pin"/>
          <wire name="sin[14]" tap_mode="classic" type="output pin"/>
          <wire name="sin[15]" tap_mode="classic" type="output pin"/>
          <wire name="sin[16]" tap_mode="classic" type="output pin"/>
          <wire name="sin[17]" tap_mode="classic" type="output pin"/>
          <wire name="sin[1]" tap_mode="classic" type="output pin"/>
          <wire name="sin[2]" tap_mode="classic" type="output pin"/>
          <wire name="sin[3]" tap_mode="classic" type="output pin"/>
          <wire name="sin[4]" tap_mode="classic" type="output pin"/>
          <wire name="sin[5]" tap_mode="classic" type="output pin"/>
          <wire name="sin[6]" tap_mode="classic" type="output pin"/>
          <wire name="sin[7]" tap_mode="classic" type="output pin"/>
          <wire name="sin[8]" tap_mode="classic" type="output pin"/>
          <wire name="sin[9]" tap_mode="classic" type="output pin"/>
          <wire name="source_eop" tap_mode="classic" type="output pin"/>
          <wire name="source_sop" tap_mode="classic" type="output pin"/>
          <wire name="source_valid18" tap_mode="classic" type="output pin"/>
          <wire name="state[0]" tap_mode="classic" type="output pin"/>
          <wire name="state[1]" tap_mode="classic" type="output pin"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire name="Imagdata_out[0]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[10]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[11]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[12]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[13]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[14]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[15]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[1]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[2]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[3]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[4]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[5]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[6]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[7]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[8]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[9]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[0]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[10]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[11]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[12]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[13]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[14]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[15]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[1]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[2]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[3]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[4]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[5]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[6]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[7]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[8]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[9]" tap_mode="classic" type="output pin"/>
          <wire name="aclr" tap_mode="classic" type="input pin"/>
          <wire name="sin[0]" tap_mode="classic" type="output pin"/>
          <wire name="sin[10]" tap_mode="classic" type="output pin"/>
          <wire name="sin[11]" tap_mode="classic" type="output pin"/>
          <wire name="sin[12]" tap_mode="classic" type="output pin"/>
          <wire name="sin[13]" tap_mode="classic" type="output pin"/>
          <wire name="sin[14]" tap_mode="classic" type="output pin"/>
          <wire name="sin[15]" tap_mode="classic" type="output pin"/>
          <wire name="sin[16]" tap_mode="classic" type="output pin"/>
          <wire name="sin[17]" tap_mode="classic" type="output pin"/>
          <wire name="sin[1]" tap_mode="classic" type="output pin"/>
          <wire name="sin[2]" tap_mode="classic" type="output pin"/>
          <wire name="sin[3]" tap_mode="classic" type="output pin"/>
          <wire name="sin[4]" tap_mode="classic" type="output pin"/>
          <wire name="sin[5]" tap_mode="classic" type="output pin"/>
          <wire name="sin[6]" tap_mode="classic" type="output pin"/>
          <wire name="sin[7]" tap_mode="classic" type="output pin"/>
          <wire name="sin[8]" tap_mode="classic" type="output pin"/>
          <wire name="sin[9]" tap_mode="classic" type="output pin"/>
          <wire name="source_eop" tap_mode="classic" type="output pin"/>
          <wire name="source_sop" tap_mode="classic" type="output pin"/>
          <wire name="source_valid18" tap_mode="classic" type="output pin"/>
          <wire name="state[0]" tap_mode="classic" type="output pin"/>
          <wire name="state[1]" tap_mode="classic" type="output pin"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <net is_signal_inverted="no" name="aclr"/>
          <net is_signal_inverted="no" name="Imagdata_out[0]"/>
          <net is_signal_inverted="no" name="Imagdata_out[1]"/>
          <net is_signal_inverted="no" name="Imagdata_out[2]"/>
          <net is_signal_inverted="no" name="Imagdata_out[3]"/>
          <net is_signal_inverted="no" name="Imagdata_out[4]"/>
          <net is_signal_inverted="no" name="Imagdata_out[5]"/>
          <net is_signal_inverted="no" name="Imagdata_out[6]"/>
          <net is_signal_inverted="no" name="Imagdata_out[7]"/>
          <net is_signal_inverted="no" name="Imagdata_out[8]"/>
          <net is_signal_inverted="no" name="Imagdata_out[9]"/>
          <net is_signal_inverted="no" name="Imagdata_out[10]"/>
          <net is_signal_inverted="no" name="Imagdata_out[11]"/>
          <net is_signal_inverted="no" name="Imagdata_out[12]"/>
          <net is_signal_inverted="no" name="Imagdata_out[13]"/>
          <net is_signal_inverted="no" name="Imagdata_out[14]"/>
          <net is_signal_inverted="no" name="Imagdata_out[15]"/>
          <net is_signal_inverted="no" name="Realdata_out[0]"/>
          <net is_signal_inverted="no" name="Realdata_out[1]"/>
          <net is_signal_inverted="no" name="Realdata_out[2]"/>
          <net is_signal_inverted="no" name="Realdata_out[3]"/>
          <net is_signal_inverted="no" name="Realdata_out[4]"/>
          <net is_signal_inverted="no" name="Realdata_out[5]"/>
          <net is_signal_inverted="no" name="Realdata_out[6]"/>
          <net is_signal_inverted="no" name="Realdata_out[7]"/>
          <net is_signal_inverted="no" name="Realdata_out[8]"/>
          <net is_signal_inverted="no" name="Realdata_out[9]"/>
          <net is_signal_inverted="no" name="Realdata_out[10]"/>
          <net is_signal_inverted="no" name="Realdata_out[11]"/>
          <net is_signal_inverted="no" name="Realdata_out[12]"/>
          <net is_signal_inverted="no" name="Realdata_out[13]"/>
          <net is_signal_inverted="no" name="Realdata_out[14]"/>
          <net is_signal_inverted="no" name="Realdata_out[15]"/>
          <net is_signal_inverted="no" name="sin[0]"/>
          <net is_signal_inverted="no" name="sin[1]"/>
          <net is_signal_inverted="no" name="sin[2]"/>
          <net is_signal_inverted="no" name="sin[3]"/>
          <net is_signal_inverted="no" name="sin[4]"/>
          <net is_signal_inverted="no" name="sin[5]"/>
          <net is_signal_inverted="no" name="sin[6]"/>
          <net is_signal_inverted="no" name="sin[7]"/>
          <net is_signal_inverted="no" name="sin[8]"/>
          <net is_signal_inverted="no" name="sin[9]"/>
          <net is_signal_inverted="no" name="sin[10]"/>
          <net is_signal_inverted="no" name="sin[11]"/>
          <net is_signal_inverted="no" name="sin[12]"/>
          <net is_signal_inverted="no" name="sin[13]"/>
          <net is_signal_inverted="no" name="sin[14]"/>
          <net is_signal_inverted="no" name="sin[15]"/>
          <net is_signal_inverted="no" name="sin[16]"/>
          <net is_signal_inverted="no" name="sin[17]"/>
          <net is_signal_inverted="no" name="source_eop"/>
          <net is_signal_inverted="no" name="source_sop"/>
          <net is_signal_inverted="no" name="source_valid18"/>
          <net is_signal_inverted="no" name="state[0]"/>
          <net is_signal_inverted="no" name="state[1]"/>
        </data_view>
        <setup_view/>
      </presentation>
      <trigger CRC="FFC8329D" is_expanded="true" name="trigger: 2010/06/05 21:12:02  #1" position="pre" power_up_trigger_mode="false" segment_size="1024" trigger_in="rising edge" trigger_out="active high" trigger_type="circular">
        <power_up_trigger position="pre" trigger_in="dont_care" trigger_out="active high"/>
        <events use_custom_flow_control="no">
          <level enabled="yes" name="condition1" type="basic">
            <power_up enabled="yes">
            </power_up>
            <op_node/>
          </level>
          <custom_flow_control>
            <flow_expression><![CDATA[state ST1:
trigger;]]>
            </flow_expression>
            <runtime_configurable comparison_operator="yes" counter_action="no" flag_action="no" logical_operator="yes" numerical_value="yes" state_transition="yes"/>
          </custom_flow_control>
        </events>
        <log>
          <data name="log: 2010/06/05 21:12:02  #2" power_up_mode="false" sample_depth="2048" trigger_position="-1">[encoded data, 114688 characters]</data>
          <extradata>T0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</extradata>
        </log>
      </trigger>
    </signal_set>
    <signal_set global_temp="1" is_expanded="true" name="signal_set: 2010/06/06 17:08:43  #0">
      <clock name="clk" polarity="posedge" tap_mode="classic"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="2048" trigger_in_enable="yes" trigger_in_node="aclr" trigger_in_tap_mode="classic" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire name="Imagdata_out[0]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[10]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[11]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[12]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[13]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[14]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[15]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[1]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[2]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[3]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[4]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[5]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[6]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[7]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[8]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[9]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[0]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[10]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[11]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[12]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[13]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[14]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[15]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[1]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[2]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[3]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[4]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[5]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[6]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[7]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[8]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[9]" tap_mode="classic" type="output pin"/>
          <wire name="aclr" tap_mode="classic" type="input pin"/>
          <wire name="sin[0]" tap_mode="classic" type="output pin"/>
          <wire name="sin[10]" tap_mode="classic" type="output pin"/>
          <wire name="sin[11]" tap_mode="classic" type="output pin"/>
          <wire name="sin[12]" tap_mode="classic" type="output pin"/>
          <wire name="sin[13]" tap_mode="classic" type="output pin"/>
          <wire name="sin[14]" tap_mode="classic" type="output pin"/>
          <wire name="sin[15]" tap_mode="classic" type="output pin"/>
          <wire name="sin[1]" tap_mode="classic" type="output pin"/>
          <wire name="sin[2]" tap_mode="classic" type="output pin"/>
          <wire name="sin[3]" tap_mode="classic" type="output pin"/>
          <wire name="sin[4]" tap_mode="classic" type="output pin"/>
          <wire name="sin[5]" tap_mode="classic" type="output pin"/>
          <wire name="sin[6]" tap_mode="classic" type="output pin"/>
          <wire name="sin[7]" tap_mode="classic" type="output pin"/>
          <wire name="sin[8]" tap_mode="classic" type="output pin"/>
          <wire name="sin[9]" tap_mode="classic" type="output pin"/>
          <wire name="source_eop" tap_mode="classic" type="output pin"/>
          <wire name="source_sop" tap_mode="classic" type="output pin"/>
          <wire name="source_valid18" tap_mode="classic" type="output pin"/>
          <wire name="state[0]" tap_mode="classic" type="output pin"/>
          <wire name="state[1]" tap_mode="classic" type="output pin"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire name="Imagdata_out[0]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[10]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[11]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[12]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[13]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[14]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[15]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[1]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[2]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[3]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[4]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[5]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[6]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[7]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[8]" tap_mode="classic" type="output pin"/>
          <wire name="Imagdata_out[9]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[0]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[10]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[11]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[12]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[13]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[14]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[15]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[1]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[2]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[3]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[4]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[5]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[6]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[7]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[8]" tap_mode="classic" type="output pin"/>
          <wire name="Realdata_out[9]" tap_mode="classic" type="output pin"/>
          <wire name="aclr" tap_mode="classic" type="input pin"/>
          <wire name="sin[0]" tap_mode="classic" type="output pin"/>
          <wire name="sin[10]" tap_mode="classic" type="output pin"/>
          <wire name="sin[11]" tap_mode="classic" type="output pin"/>
          <wire name="sin[12]" tap_mode="classic" type="output pin"/>
          <wire name="sin[13]" tap_mode="classic" type="output pin"/>
          <wire name="sin[14]" tap_mode="classic" type="output pin"/>
          <wire name="sin[15]" tap_mode="classic" type="output pin"/>
          <wire name="sin[1]" tap_mode="classic" type="output pin"/>
          <wire name="sin[2]" tap_mode="classic" type="output pin"/>
          <wire name="sin[3]" tap_mode="classic" type="output pin"/>
          <wire name="sin[4]" tap_mode="classic" type="output pin"/>
          <wire name="sin[5]" tap_mode="classic" type="output pin"/>
          <wire name="sin[6]" tap_mode="classic" type="output pin"/>
          <wire name="sin[7]" tap_mode="classic" type="output pin"/>
          <wire name="sin[8]" tap_mode="classic" type="output pin"/>
          <wire name="sin[9]" tap_mode="classic" type="output pin"/>
          <wire name="source_eop" tap_mode="classic" type="output pin"/>
          <wire name="source_sop" tap_mode="classic" type="output pin"/>
          <wire name="source_valid18" tap_mode="classic" type="output pin"/>
          <wire name="state[0]" tap_mode="classic" type="output pin"/>
          <wire name="state[1]" tap_mode="classic" type="output pin"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <bus is_signal_inverted="no" link="all" name="Imagdata_out" order="lsb_to_msb" radix="line_signed" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="Imagdata_out[0]"/>
            <net is_signal_inverted="no" name="Imagdata_out[1]"/>
            <net is_signal_inverted="no" name="Imagdata_out[2]"/>
            <net is_signal_inverted="no" name="Imagdata_out[3]"/>
            <net is_signal_inverted="no" name="Imagdata_out[4]"/>
            <net is_signal_inverted="no" name="Imagdata_out[5]"/>
            <net is_signal_inverted="no" name="Imagdata_out[6]"/>
            <net is_signal_inverted="no" name="Imagdata_out[7]"/>
            <net is_signal_inverted="no" name="Imagdata_out[8]"/>
            <net is_signal_inverted="no" name="Imagdata_out[9]"/>
            <net is_signal_inverted="no" name="Imagdata_out[10]"/>
            <net is_signal_inverted="no" name="Imagdata_out[11]"/>
            <net is_signal_inverted="no" name="Imagdata_out[12]"/>
            <net is_signal_inverted="no" name="Imagdata_out[13]"/>
            <net is_signal_inverted="no" name="Imagdata_out[14]"/>
            <net is_signal_inverted="no" name="Imagdata_out[15]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="Realdata_out" order="lsb_to_msb" radix="line_signed" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="Realdata_out[0]"/>
            <net is_signal_inverted="no" name="Realdata_out[1]"/>
            <net is_signal_inverted="no" name="Realdata_out[2]"/>
            <net is_signal_inverted="no" name="Realdata_out[3]"/>
            <net is_signal_inverted="no" name="Realdata_out[4]"/>
            <net is_signal_inverted="no" name="Realdata_out[5]"/>
            <net is_signal_inverted="no" name="Realdata_out[6]"/>
            <net is_signal_inverted="no" name="Realdata_out[7]"/>
            <net is_signal_inverted="no" name="Realdata_out[8]"/>
            <net is_signal_inverted="no" name="Realdata_out[9]"/>
            <net is_signal_inverted="no" name="Realdata_out[10]"/>
            <net is_signal_inverted="no" name="Realdata_out[11]"/>
            <net is_signal_inverted="no" name="Realdata_out[12]"/>
            <net is_signal_inverted="no" name="Realdata_out[13]"/>
            <net is_signal_inverted="no" name="Realdata_out[14]"/>
            <net is_signal_inverted="no" name="Realdata_out[15]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="sin" order="lsb_to_msb" radix="line_signed" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="sin[0]"/>
            <net is_signal_inverted="no" name="sin[1]"/>
            <net is_signal_inverted="no" name="sin[2]"/>
            <net is_signal_inverted="no" name="sin[3]"/>
            <net is_signal_inverted="no" name="sin[4]"/>
            <net is_signal_inverted="no" name="sin[5]"/>
            <net is_signal_inverted="no" name="sin[6]"/>
            <net is_signal_inverted="no" name="sin[7]"/>
            <net is_signal_inverted="no" name="sin[8]"/>
            <net is_signal_inverted="no" name="sin[9]"/>
            <net is_signal_inverted="no" name="sin[10]"/>
            <net is_signal_inverted="no" name="sin[11]"/>
            <net is_signal_inverted="no" name="sin[12]"/>
            <net is_signal_inverted="no" name="sin[13]"/>
            <net is_signal_inverted="no" name="sin[14]"/>
            <net is_signal_inverted="no" name="sin[15]"/>
          </bus>
          <net is_signal_inverted="no" name="source_eop"/>
          <net is_signal_inverted="no" name="source_sop"/>
          <net is_signal_inverted="no" name="source_valid18"/>
          <bus is_signal_inverted="no" link="all" name="state" order="msb_to_lsb" radix="hex" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="state[0]"/>
            <net is_signal_inverted="no" name="state[1]"/>
          </bus>
          <net is_signal_inverted="no" name="aclr"/>
        </data_view>
        <setup_view>
          <bus is_signal_inverted="no" link="all" name="Imagdata_out" order="lsb_to_msb" radix="line_signed" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="Imagdata_out[0]"/>
            <net is_signal_inverted="no" name="Imagdata_out[1]"/>
            <net is_signal_inverted="no" name="Imagdata_out[2]"/>
            <net is_signal_inverted="no" name="Imagdata_out[3]"/>
            <net is_signal_inverted="no" name="Imagdata_out[4]"/>
            <net is_signal_inverted="no" name="Imagdata_out[5]"/>
            <net is_signal_inverted="no" name="Imagdata_out[6]"/>
            <net is_signal_inverted="no" name="Imagdata_out[7]"/>
            <net is_signal_inverted="no" name="Imagdata_out[8]"/>
            <net is_signal_inverted="no" name="Imagdata_out[9]"/>
            <net is_signal_inverted="no" name="Imagdata_out[10]"/>
            <net is_signal_inverted="no" name="Imagdata_out[11]"/>
            <net is_signal_inverted="no" name="Imagdata_out[12]"/>
            <net is_signal_inverted="no" name="Imagdata_out[13]"/>
            <net is_signal_inverted="no" name="Imagdata_out[14]"/>
            <net is_signal_inverted="no" name="Imagdata_out[15]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="Realdata_out" order="lsb_to_msb" radix="line_signed" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="Realdata_out[0]"/>
            <net is_signal_inverted="no" name="Realdata_out[1]"/>
            <net is_signal_inverted="no" name="Realdata_out[2]"/>
            <net is_signal_inverted="no" name="Realdata_out[3]"/>
            <net is_signal_inverted="no" name="Realdata_out[4]"/>
            <net is_signal_inverted="no" name="Realdata_out[5]"/>
            <net is_signal_inverted="no" name="Realdata_out[6]"/>
            <net is_signal_inverted="no" name="Realdata_out[7]"/>
            <net is_signal_inverted="no" name="Realdata_out[8]"/>
            <net is_signal_inverted="no" name="Realdata_out[9]"/>
            <net is_signal_inverted="no" name="Realdata_out[10]"/>
            <net is_signal_inverted="no" name="Realdata_out[11]"/>
            <net is_signal_inverted="no" name="Realdata_out[12]"/>
            <net is_signal_inverted="no" name="Realdata_out[13]"/>
            <net is_signal_inverted="no" name="Realdata_out[14]"/>
            <net is_signal_inverted="no" name="Realdata_out[15]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="sin" order="lsb_to_msb" radix="line_signed" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="sin[0]"/>
            <net is_signal_inverted="no" name="sin[1]"/>
            <net is_signal_inverted="no" name="sin[2]"/>
            <net is_signal_inverted="no" name="sin[3]"/>
            <net is_signal_inverted="no" name="sin[4]"/>
            <net is_signal_inverted="no" name="sin[5]"/>
            <net is_signal_inverted="no" name="sin[6]"/>
            <net is_signal_inverted="no" name="sin[7]"/>
            <net is_signal_inverted="no" name="sin[8]"/>
            <net is_signal_inverted="no" name="sin[9]"/>
            <net is_signal_inverted="no" name="sin[10]"/>
            <net is_signal_inverted="no" name="sin[11]"/>
            <net is_signal_inverted="no" name="sin[12]"/>
            <net is_signal_inverted="no" name="sin[13]"/>
            <net is_signal_inverted="no" name="sin[14]"/>
            <net is_signal_inverted="no" name="sin[15]"/>
          </bus>
          <net is_signal_inverted="no" name="source_eop"/>
          <net is_signal_inverted="no" name="source_sop"/>
          <net is_signal_inverted="no" name="source_valid18"/>
          <bus is_signal_inverted="no" link="all" name="state" order="msb_to_lsb" radix="hex" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="state[0]"/>
            <net is_signal_inverted="no" name="state[1]"/>
          </bus>
          <net is_signal_inverted="no" name="aclr"/>
        </setup_view>
      </presentation>
      <trigger CRC="7D100CE1" global_temp="1" is_expanded="true" name="trigger: 2010/06/06 17:08:43  #1" position="pre" power_up_trigger_mode="false" segment_size="1024" trigger_in="low" trigger_out="active high" trigger_type="circular">
        <power_up_trigger position="pre" trigger_in="dont_care" trigger_out="active high"/>
        <events use_custom_flow_control="no">
          <level enabled="yes" name="condition1" type="basic">
            <power_up enabled="yes">
            </power_up>
            <op_node/>
          </level>
          <custom_flow_control>
            <runtime_configurable comparison_operator="yes" counter_action="no" flag_action="no" logical_operator="yes" numerical_value="yes" state_transition="yes"/>
            <flow_expression><![CDATA[state ST1:
trigger;]]>
            </flow_expression>
            <power_up_flow_expression><![CDATA[state ST1:
trigger;]]>
            </power_up_flow_expression>
          </custom_flow_control>
        </events>
        <log>
          <data global_temp="1" name="log: 2010/06/08 23:09:33  #0" power_up_mode="false" sample_depth="2048" trigger_position="256">[encoded data, 110592 characters]</data>
          <extradata>1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111T111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</extradata>
        </log>
      </trigger>
    </signal_set>
    <position_info>
      <single attribute="active tab" value="0"/>
      <single attribute="data horizontal scroll position" value="0"/>
      <single attribute="data vertical scroll position" value="0"/>
      <single attribute="setup horizontal scroll position" value="0"/>
      <single attribute="setup vertical scroll position" value="0"/>
      <single attribute="zoom level denominator" value="1"/>
      <single attribute="zoom level numerator" value="1"/>
      <single attribute="zoom offset denominator" value="1"/>
      <single attribute="zoom offset numerator" value="129024"/>
    </position_info>
  </instance>
  <global_info>
    <single attribute="active instance" value="0"/>
    <single attribute="lock mode" value="36110"/>
    <multi attribute="window position" size="9" value="879,385,398,124,0,50,32,0,2"/>
  </global_info>
</session>
