Sample Waveforms for altpll0.v

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Sample behavioral waveforms for design file altpll0.v

The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design altpll0.v. The design altpll0.v has Stratix II AUTO pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. Output port LOCKED will go high when the PLL locks to the input clock.

Fig. 1 : Wave showing NORMAL mode operation.

When input port ARESET is asserted, it will cause the LOCKED port and all CLK outputs to drop to zero. The PLL will relock to the input clock when this port is deasserted.