--alt_ded_mult_y CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" device_family="Cyclone II" dsp_block_balancing="Auto" input_aclr_a="ACLR0" input_aclr_b="ACLR0" input_reg_a="CLOCK0" input_reg_b="CLOCK0" output_aclr="ACLR0" output_reg="CLOCK0" pipeline_reg="UNREGISTERED" representation_a="SIGNED" representation_b="SIGNED" sub_dedicated_multiplier_circuitry="YES" width_a=18 width_b=18 aclr clock dataa datab ena result
--VERSION_BEGIN 7.2 cbx_alt_ded_mult_y 2007:03:05:16:04:08:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_padd 2007:07:12:14:48:24:SJ cbx_parallel_add 2007:01:30:03:53:08:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION cycloneii_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb)
WITH ( dataa_clock, dataa_width, datab_clock, datab_width, signa_clock, signb_clock)
RETURNS ( dataout[dataa_width+datab_width-1..0]);
FUNCTION cycloneii_mac_out (aclr, clk, dataa[dataa_width-1..0], ena)
WITH ( dataa_width = 0, output_clock)
RETURNS ( dataout[dataa_width-1..0]);
FUNCTION dffpipe_d3c (d[35..0])
RETURNS ( q[35..0]);

--synthesis_resources = dsp_9bit 2 
SUBDESIGN ded_mult_jf51
( 
	aclr[3..0]	:	input;
	clock[3..0]	:	input;
	dataa[17..0]	:	input;
	datab[17..0]	:	input;
	ena[3..0]	:	input;
	result[35..0]	:	output;
) 
VARIABLE 
	mac_mult86 : cycloneii_mac_mult
		WITH (
			dataa_clock = "0",
			dataa_width = 18,
			datab_clock = "0",
			datab_width = 18
		);
	mac_out87 : cycloneii_mac_out
		WITH (
			dataa_width = 36,
			output_clock = "0"
		);
	pre_result : dffpipe_d3c;
	x_dataa[17..0]	: WIRE;
	x_datab[17..0]	: WIRE;
	x_signa[0..0]	: WIRE;
	x_signb[0..0]	: WIRE;

BEGIN 
	mac_mult86.aclr = aclr[0..0];
	mac_mult86.clk = clock[0..0];
	mac_mult86.dataa[] = ( x_dataa[]);
	mac_mult86.datab[] = ( x_datab[]);
	mac_mult86.ena = ena[0..0];
	mac_mult86.signa = x_signa[];
	mac_mult86.signb = x_signb[];
	mac_out87.aclr = aclr[0..0];
	mac_out87.clk = clock[0..0];
	mac_out87.dataa[] = ( mac_mult86.dataout[35..0]);
	mac_out87.ena = ena[0..0];
	pre_result.d[35..0] = mac_out87.dataout[35..0];
	result[] = pre_result.q[];
	x_dataa[] = dataa[];
	x_datab[] = datab[];
	x_signa[] = B"1";
	x_signb[] = B"1";
END;
--VALID FILE
