module D(reset,clk,data_in,data_out);//for the delay of ROM

input clk,reset;
input[15:0] data_in;
output[15:0] data_out;

reg[15:0] temp;

always@(posedge clk or negedge reset)begin
	if(!reset)
		temp<=0;
	else
		temp<=data_in;
end

assign data_out=temp;

endmodule 