// megafunction wizard: %ALTMULT_COMPLEX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altmult_complex 

// ============================================================
// File Name: altmult_complex0.v
// Megafunction Name(s):
// 			altmult_complex
//
// Simulation Library Files(s):
// 			altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 151 09/26/2007 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altmult_complex0 (
	clock,
	dataa_imag,
	dataa_real,
	datab_imag,
	datab_real,
	result_imag,
	result_real);

	input	  clock;
	input	[16:0]  dataa_imag;
	input	[16:0]  dataa_real;
	input	[16:0]  datab_imag;
	input	[16:0]  datab_real;
	output	[33:0]  result_imag;
	output	[33:0]  result_real;

	wire [33:0] sub_wire0;
	wire [33:0] sub_wire1;
	wire [33:0] result_real = sub_wire0[33:0];
	wire [33:0] result_imag = sub_wire1[33:0];

	altmult_complex	altmult_complex_component (
				.datab_imag (datab_imag),
				.clock (clock),
				.dataa_imag (dataa_imag),
				.datab_real (datab_real),
				.dataa_real (dataa_real),
				.result_real (sub_wire0),
				.result_imag (sub_wire1),
				.aclr (1'b0),
				.ena (1'b1));
	defparam
		altmult_complex_component.implementation_style = "AUTO",
		altmult_complex_component.intended_device_family = "Stratix II",
		altmult_complex_component.pipeline = 3,
		altmult_complex_component.representation_a = "SIGNED",
		altmult_complex_component.representation_b = "SIGNED",
		altmult_complex_component.width_a = 17,
		altmult_complex_component.width_b = 17,
		altmult_complex_component.width_result = 34;


endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: IMPLEMENTATION_STYLE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "3"
// Retrieval info: CONSTANT: REPRESENTATION_A STRING "SIGNED"
// Retrieval info: CONSTANT: REPRESENTATION_B STRING "SIGNED"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "17"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "17"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "34"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa_imag 0 0 17 0 INPUT NODEFVAL "dataa_imag[16..0]"
// Retrieval info: USED_PORT: dataa_real 0 0 17 0 INPUT NODEFVAL "dataa_real[16..0]"
// Retrieval info: USED_PORT: datab_imag 0 0 17 0 INPUT NODEFVAL "datab_imag[16..0]"
// Retrieval info: USED_PORT: datab_real 0 0 17 0 INPUT NODEFVAL "datab_real[16..0]"
// Retrieval info: USED_PORT: result_imag 0 0 34 0 OUTPUT NODEFVAL "result_imag[33..0]"
// Retrieval info: USED_PORT: result_real 0 0 34 0 OUTPUT NODEFVAL "result_real[33..0]"
// Retrieval info: CONNECT: @datab_real 0 0 17 0 datab_real 0 0 17 0
// Retrieval info: CONNECT: result_imag 0 0 34 0 @result_imag 0 0 34 0
// Retrieval info: CONNECT: result_real 0 0 34 0 @result_real 0 0 34 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa_imag 0 0 17 0 dataa_imag 0 0 17 0
// Retrieval info: CONNECT: @datab_imag 0 0 17 0 datab_imag 0 0 17 0
// Retrieval info: CONNECT: @dataa_real 0 0 17 0 dataa_real 0 0 17 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altmult_complex0.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altmult_complex0.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altmult_complex0.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altmult_complex0.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altmult_complex0_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altmult_complex0_bb.v TRUE FALSE
// Retrieval info: LIB_FILE: altera_mf
