module p2s(clk,reset,sink_valid,data_in0,data_in1,data_out,source_valid);

input clk,reset,sink_valid;
input [17:0] data_in0,data_in1;
output source_valid;
output[17:0] data_out;

parameter scale=7'b1000000; 
reg cnt;
reg[6:0]count;
reg[17:0] data_temp[1:0];

always@(posedge clk or negedge reset)begin
	if(!reset)begin
		count<=7'b0000_000;
		cnt<=1'b0;
		data_temp[0]<=18'b0000_0000_0000_0000_00;
		data_temp[1]<=18'b0000_0000_0000_0000_00;
		end
	else if(sink_valid==1'b1)
		begin
		cnt<=cnt+1'b1;
		if(count<scale)
			count<=count+7'b0000_001;
		else
			count<=7'b0000_000;
		data_temp[0]<=data_in0;
		data_temp[1]<=data_in1;
		end
	else begin
		cnt<=1'b0;
		count<=7'b0000_000;
		data_temp[0]<=18'b0000_0000_0000_0000_00;
		data_temp[1]<=18'b0000_0000_0000_0000_00;
		end
end


assign data_out=(count>0&&cnt==0)?data_temp[1]:
				(count>0&&cnt==1)?data_temp[0]:18'b0000_0000_0000_0000_00;
//attention to why the number is reversed. it is because of the cnt.
assign source_valid=(count>0&&reset==1)?1'b0:1'b1;

endmodule	