--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Stratix II" LPM_DIRECTION="ADD" LPM_PIPELINE=3 LPM_WIDTH=17 ONE_INPUT_IS_CONSTANT="NO" clock dataa datab result
--VERSION_BEGIN 7.2 cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION stratixii_lcell_comb (cin, dataa, datab, datac, datad, datae, dataf, datag, sharein)
WITH ( EXTENDED_LUT, LUT_MASK, SHARED_ARITH)
RETURNS ( combout, cout, shareout, sumout);

--synthesis_resources = lut 57 reg 54 
SUBDESIGN add_sub_vng
( 
	clock	:	input;
	dataa[16..0]	:	input;
	datab[16..0]	:	input;
	result[16..0]	:	output;
) 
VARIABLE 
	add_sub_cell_ffa[16..0] : dffe;
	inter_regrs_cin_ffa[2..0] : dffe;
	pad_cell_ffa[33..0] : dffe;
	add_sub_cella[16..0] : stratixii_lcell_comb
		WITH (
			EXTENDED_LUT = "off",
			LUT_MASK = "000033330000AAAA",
			SHARED_ARITH = "off"
		);
	inter_regrs_cina[2..0] : stratixii_lcell_comb
		WITH (
			EXTENDED_LUT = "off",
			LUT_MASK = "0000AAAA00005555",
			SHARED_ARITH = "off"
		);
	inter_regrs_couta[2..0] : stratixii_lcell_comb
		WITH (
			EXTENDED_LUT = "off",
			LUT_MASK = "000055550000AAAA",
			SHARED_ARITH = "off"
		);
	pad_cella[33..0] : stratixii_lcell_comb
		WITH (
			EXTENDED_LUT = "off",
			LUT_MASK = "000033330000AAAA",
			SHARED_ARITH = "off"
		);

BEGIN 
	add_sub_cell_ffa[].clk = clock;
	add_sub_cell_ffa[].d = add_sub_cella[].sumout;
	inter_regrs_cin_ffa[].clk = clock;
	inter_regrs_cin_ffa[].d = inter_regrs_cina[].sumout;
	pad_cell_ffa[].clk = clock;
	pad_cell_ffa[].d = pad_cella[].sumout;
	add_sub_cella[].cin = ( add_sub_cella[15..10].cout, B"0", add_sub_cella[8..5].cout, B"0", add_sub_cella[3..0].cout, B"0");
	add_sub_cella[].dataa = dataa[];
	add_sub_cella[].datab = datab[];
	inter_regrs_cina[].cin = ( pad_cella[9].cout, add_sub_cella[9].cout, add_sub_cella[4].cout);
	inter_regrs_cina[].dataa = B"111";
	inter_regrs_couta[].cin = B"000";
	inter_regrs_couta[].dataa = ( inter_regrs_cin_ffa[2..0].q);
	pad_cella[].cin = ( pad_cella[32..27].cout, inter_regrs_couta[2].cout, pad_cella[25..22].cout, B"0", pad_cella[20..17].cout, B"0", pad_cella[15..10].cout, inter_regrs_couta[1].cout, pad_cella[8..5].cout, inter_regrs_couta[0].cout, pad_cella[3..0].cout, B"0");
	pad_cella[].dataa = ( pad_cell_ffa[16..0].q, add_sub_cell_ffa[].q);
	pad_cella[].datab = B"0000000000000000000000000000000000";
	result[16..0] = pad_cell_ffa[33..17].q;
END;
--VALID FILE
