--altmult_add CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix II" DSP_BLOCK_BALANCING="Auto" INPUT_ACLR_A0="ACLR0" INPUT_ACLR_A1="ACLR0" INPUT_ACLR_B0="ACLR0" INPUT_ACLR_B1="ACLR0" INPUT_REGISTER_A0="CLOCK0" INPUT_REGISTER_A1="CLOCK0" INPUT_REGISTER_B0="CLOCK0" INPUT_REGISTER_B1="CLOCK0" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_A1="DATAA" MULTIPLIER1_DIRECTION="SUB" MULTIPLIER_ACLR0="ACLR0" MULTIPLIER_ACLR1="ACLR0" MULTIPLIER_REGISTER0="CLOCK0" MULTIPLIER_REGISTER1="CLOCK0" NUMBER_OF_MULTIPLIERS=2 OUTPUT_ACLR="ACLR0" OUTPUT_REGISTER="CLOCK0" REPRESENTATION_A="UNSIGNED" REPRESENTATION_B="UNSIGNED" WIDTH_A=18 WIDTH_B=18 WIDTH_RESULT=36 clock0 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 7.2 cbx_alt_ded_mult_y 2007:03:05:16:04:08:SJ cbx_altmult_add 2007:08:27:13:54:20:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_mult 2007:07:20:16:47:26:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_padd 2007:07:12:14:48:24:SJ cbx_parallel_add 2007:01:30:03:53:08:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
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--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION stratixii_mac_mult (aclr[3..0], clk[3..0], dataa[dataa_width-1..0], datab[datab_width-1..0], ena[3..0], mode, round, saturate, scanina[dataa_width-1..0], scaninb[datab_width-1..0], signa, signb, sourcea, sourceb, zeroacc)
WITH ( bypass_multiplier, dataa_clear, dataa_clock, dataa_width, datab_clear, datab_clock, datab_width, dynamic_mode, mode_clear, mode_clock, output_clear, output_clock, round_clear, round_clock, saturate_clear, saturate_clock, signa_clear, signa_clock, signa_internally_grounded, signb_clear, signb_clock, signb_internally_grounded, zeroacc_clear, zeroacc_clock)
RETURNS ( dataout[dataa_width+datab_width-1..0], scanouta[dataa_width-1..0], scanoutb[datab_width-1..0]);
FUNCTION stratixii_mac_out (aclr[3..0], addnsub0, addnsub1, clk[3..0], dataa[dataa_width-1..0], datab[datab_width-1..0], datac[datac_width-1..0], datad[datad_width-1..0], ena[3..0], mode0, mode1, multabsaturate, multcdsaturate, round0, round1, saturate, saturate1, signa, signb, zeroacc, zeroacc1)
WITH ( addnsub0_clear, addnsub0_clock, addnsub0_pipeline_clear, addnsub0_pipeline_clock, addnsub1_clear, addnsub1_clock, addnsub1_pipeline_clear, addnsub1_pipeline_clock, dataa_forced_to_zero, dataa_width = 1, datab_width = 1, datac_forced_to_zero, datac_width = 1, datad_width = 1, dataout_width = 144, mode0_clear, mode0_clock, mode0_pipeline_clear, mode0_pipeline_clock, mode1_clear, mode1_clock, mode1_pipeline_clear, mode1_pipeline_clock, multabsaturate_clear, multabsaturate_clock, multabsaturate_pipeline_clear, multabsaturate_pipeline_clock, multcdsaturate_clear, multcdsaturate_clock, multcdsaturate_pipeline_clear, multcdsaturate_pipeline_clock, operation_mode, output1_clear, output1_clock, output2_clear, output2_clock, output3_clear, output3_clock, output4_clear, output4_clock, output5_clear, output5_clock, output6_clear, output6_clock, output7_clear, output7_clock, output_clear, output_clock, round0_clear, round0_clock, round0_pipeline_clear, round0_pipeline_clock, round1_clear, round1_clock, round1_pipeline_clear, round1_pipeline_clock, saturate1_clear, saturate1_clock, saturate1_pipeline_clear, saturate1_pipeline_clock, saturate_clear, saturate_clock, saturate_pipeline_clear, saturate_pipeline_clock, signa_clear, signa_clock, signa_pipeline_clear, signa_pipeline_clock, signb_clear, signb_clock, signb_pipeline_clear, signb_pipeline_clock, zeroacc1_clear, zeroacc1_clock, zeroacc1_pipeline_clear, zeroacc1_pipeline_clock, zeroacc_clear, zeroacc_clock, zeroacc_pipeline_clear, zeroacc_pipeline_clock)
RETURNS ( accoverflow, dataout[dataout_width-1..0]);

--synthesis_resources = dsp_9bit 4 
SUBDESIGN mult_add_1f12
( 
	clock0	:	input;
	dataa[35..0]	:	input;
	datab[35..0]	:	input;
	result[35..0]	:	output;
) 
VARIABLE 
	mac_mult1 : stratixii_mac_mult
		WITH (
			dataa_clear = "0",
			dataa_clock = "0",
			dataa_width = 18,
			datab_clear = "0",
			datab_clock = "0",
			datab_width = 18,
			output_clear = "0",
			output_clock = "0"
		);
	mac_mult2 : stratixii_mac_mult
		WITH (
			dataa_clear = "0",
			dataa_clock = "0",
			dataa_width = 18,
			datab_clear = "0",
			datab_clock = "0",
			datab_width = 18,
			output_clear = "0",
			output_clock = "0"
		);
	mac_out3 : stratixii_mac_out
		WITH (
			dataa_width = 36,
			datab_width = 36,
			dataout_width = 144,
			operation_mode = "one_level_adder",
			output_clear = "0",
			output_clock = "0"
		);
	aclr0	: NODE;
	aclr1	: NODE;
	aclr2	: NODE;
	aclr3	: NODE;
	clock1	: NODE;
	clock2	: NODE;
	clock3	: NODE;
	dataa_bus[35..0]	: WIRE;
	datab_bus[35..0]	: WIRE;
	ena0	: NODE;
	ena1	: NODE;
	ena2	: NODE;
	ena3	: NODE;
	global_gnd	: WIRE;

BEGIN 
	mac_mult1.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_mult1.clk[] = ( clock3, clock2, clock1, clock0);
	mac_mult1.dataa[] = ( dataa_bus[17..0]);
	mac_mult1.datab[] = ( datab_bus[17..0]);
	mac_mult1.ena[] = ( ena3, ena2, ena1, ena0);
	mac_mult1.signa = B"0";
	mac_mult1.signb = B"0";
	mac_mult1.sourcea = global_gnd;
	mac_mult1.sourceb = global_gnd;
	mac_mult2.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_mult2.clk[] = ( clock3, clock2, clock1, clock0);
	mac_mult2.dataa[] = ( dataa_bus[35..18]);
	mac_mult2.datab[] = ( datab_bus[35..18]);
	mac_mult2.ena[] = ( ena3, ena2, ena1, ena0);
	mac_mult2.signa = B"0";
	mac_mult2.signb = B"0";
	mac_mult2.sourcea = global_gnd;
	mac_mult2.sourceb = global_gnd;
	mac_out3.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_out3.addnsub0 = B"0";
	mac_out3.addnsub1 = B"1";
	mac_out3.clk[] = ( clock3, clock2, clock1, clock0);
	mac_out3.dataa[] = ( mac_mult1.dataout[35..0]);
	mac_out3.datab[] = ( mac_mult2.dataout[35..0]);
	mac_out3.ena[] = ( ena3, ena2, ena1, ena0);
	mac_out3.signa = B"0";
	mac_out3.signb = B"0";
	aclr0 = GND;
	aclr1 = GND;
	aclr2 = GND;
	aclr3 = GND;
	clock1 = VCC;
	clock2 = VCC;
	clock3 = VCC;
	dataa_bus[] = ( dataa[35..0]);
	datab_bus[] = ( datab[35..0]);
	ena0 = VCC;
	ena1 = VCC;
	ena2 = VCC;
	ena3 = VCC;
	global_gnd = B"0";
	result[35..0] = mac_out3.dataout[35..0];
END;
--VALID FILE
