module D_state(reset,clk,clk_en,data_in,data_out);//for the delay of ROM

input clk,reset,clk_en;
input[1:0] data_in;
output[1:0] data_out;

reg[1:0] temp;

always@(posedge clk or negedge reset)begin
	if(!reset)
		temp<=0;
	else
			temp<=data_in;
end

assign data_out=temp;

endmodule 