{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 17 12:52:47 2006 " "Info: Processing started: Mon Jul 17 12:52:47 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off subtracter_4 -c subtracter_4 " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off subtracter_4 -c subtracter_4" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "X\[0\] BOUT 8.100 ns Longest " "Info: Longest tpd from source pin \"X\[0\]\" to destination pin \"BOUT\" is 8.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns X\[0\] 1 PIN PIN_6 24 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_6; Fanout = 24; PIN Node = 'X\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/db/subtracter_4_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/db/subtracter_4_cmp.qrpt" Compiler "subtracter_4" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/db/subtracter_4.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/" "" "" { X[0] } "NODE_NAME" } "" } } { "subtracter_4.v" "" { Text "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/subtracter_4.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.100 ns) 4.300 ns subtracter_1:U1\|D~2 2 COMB SEXP13 1 " "Info: 2: + IC(1.000 ns) + CELL(3.100 ns) = 4.300 ns; Loc. = SEXP13; Fanout = 1; COMB Node = 'subtracter_1:U1\|D~2'" {  } { { "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/db/subtracter_4_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/db/subtracter_4_cmp.qrpt" Compiler "subtracter_4" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/db/subtracter_4.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/" "" "4.100 ns" { X[0] subtracter_1:U1|D~2 } "NODE_NAME" } "" } } { "subtracter_1.v" "" { Text "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/subtracter_1.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.600 ns) 7.900 ns subtracter_1:U1\|add~54 3 COMB LC11 1 " "Info: 3: + IC(0.000 ns) + CELL(3.600 ns) = 7.900 ns; Loc. = LC11; Fanout = 1; COMB Node = 'subtracter_1:U1\|add~54'" {  } { { "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/db/subtracter_4_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/db/subtracter_4_cmp.qrpt" Compiler "subtracter_4" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/db/subtracter_4.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/" "" "3.600 ns" { subtracter_1:U1|D~2 subtracter_1:U1|add~54 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.100 ns BOUT 4 PIN PIN_16 0 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 8.100 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'BOUT'" {  } { { "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/db/subtracter_4_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/db/subtracter_4_cmp.qrpt" Compiler "subtracter_4" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/db/subtracter_4.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/" "" "0.200 ns" { subtracter_1:U1|add~54 BOUT } "NODE_NAME" } "" } } { "subtracter_4.v" "" { Text "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/subtracter_4.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.100 ns 87.65 % " "Info: Total cell delay = 7.100 ns ( 87.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 12.35 % " "Info: Total interconnect delay = 1.000 ns ( 12.35 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/db/subtracter_4_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/db/subtracter_4_cmp.qrpt" Compiler "subtracter_4" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/db/subtracter_4.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/第1章/subtracter_4/" "" "8.100 ns" { X[0] subtracter_1:U1|D~2 subtracter_1:U1|add~54 BOUT } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.100 ns" { X[0] X[0]~out subtracter_1:U1|D~2 subtracter_1:U1|add~54 BOUT } { 0.000ns 0.000ns 1.000ns 0.000ns 0.000ns } { 0.000ns 0.200ns 3.100ns 3.600ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 17 12:52:48 2006 " "Info: Processing ended: Mon Jul 17 12:52:48 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}
