{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 08 11:29:00 2006 " "Info: Processing started: Tue Aug 08 11:29:00 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off Data_Mux -c Data_Mux " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Data_Mux -c Data_Mux" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Data_Mux.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Data_Mux.v" { { "Info" "ISGN_ENTITY_NAME" "1 Data_Mux " "Info: Found entity 1: Data_Mux" {  } { { "Data_Mux.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Data_Mux/Data_Mux.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "Y_1 Data_Mux.v(15) " "Warning: Verilog HDL Always Construct warning at Data_Mux.v(15): variable Y_1 may not be assigned a new value in every possible path through the Always Construct.  Variable Y_1 holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "Data_Mux.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Data_Mux/Data_Mux.v" 15 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "Y_2 Data_Mux.v(15) " "Warning: Verilog HDL Always Construct warning at Data_Mux.v(15): variable Y_2 may not be assigned a new value in every possible path through the Always Construct.  Variable Y_2 holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "Data_Mux.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Data_Mux/Data_Mux.v" 15 0 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "Y_1\$latch " "Warning: LATCH primitive \"Y_1\$latch\" is permanently enabled" {  } { { "Data_Mux.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Data_Mux/Data_Mux.v" 19 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "18 " "Info: Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "3 " "Info: Implemented 3 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "1 " "Info: Implemented 1 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 08 11:29:01 2006 " "Info: Processing ended: Tue Aug 08 11:29:01 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}
