Analysis & Synthesis report for main
Sat Jul 15 23:18:27 2006
Version 4.2 Build 157 12/07/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Multiplexer Restructuring Statistics (Restructuring Performed)
  5. User-Specified and Inferred Latches
  6. General Register Statistics
  7. WYSIWYG Cells
  8. Hierarchy
  9. Analysis & Synthesis Resource Utilization by Entity
 10. Analysis & Synthesis Equations
 11. Analysis & Synthesis Source Files Read
 12. Analysis & Synthesis Resource Usage Summary
 13. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sat Jul 15 23:18:27 2006    ;
; Quartus II Version          ; 4.2 Build 157 12/07/2004 SJ Full Version ;
; Revision Name               ; main                                     ;
; Top-level Entity Name       ; main                                     ;
; Family                      ; Stratix                                  ;
; Total logic elements        ; 501                                      ;
; Total pins                  ; 18                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 0                                        ;
; DSP block 9-bit elements    ; 0                                        ;
; Total PLLs                  ; 0                                        ;
; Total DLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                     ;
+--------------------------------------------------------------------+--------------+---------------+
; Option                                                             ; Setting      ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Use smart compilation                                              ; Normal       ; Normal        ;
; Restructure Multiplexers                                           ; Auto         ; Auto          ;
; Create Debugging Nodes for IP Cores                                ; off          ; off           ;
; Preserve fewer node names                                          ; On           ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off          ; Off           ;
; Verilog Version                                                    ; Verilog_2001 ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93       ; VHDL93        ;
; Family name                                                        ; Stratix      ; Stratix       ;
; Top-level entity name                                              ; main         ; main          ;
; State Machine Processing                                           ; Auto         ; Auto          ;
; Extract Verilog State Machines                                     ; On           ; On            ;
; Extract VHDL State Machines                                        ; On           ; On            ;
; DSP Block Balancing                                                ; Auto         ; Auto          ;
; NOT Gate Push-Back                                                 ; On           ; On            ;
; Power-Up Don't Care                                                ; On           ; On            ;
; Remove Redundant Logic Cells                                       ; Off          ; Off           ;
; Remove Duplicate Registers                                         ; On           ; On            ;
; Ignore CARRY Buffers                                               ; Off          ; Off           ;
; Ignore CASCADE Buffers                                             ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                              ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                                          ; Off          ; Off           ;
; Ignore LCELL Buffers                                               ; Off          ; Off           ;
; Ignore SOFT Buffers                                                ; On           ; On            ;
; Limit AHDL Integers to 32 Bits                                     ; Off          ; Off           ;
; Optimization Technique -- Stratix/Stratix GX                       ; Balanced     ; Balanced      ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70           ; 70            ;
; Auto Carry Chains                                                  ; On           ; On            ;
; Auto Open-Drain Pins                                               ; On           ; On            ;
; Remove Duplicate Logic                                             ; On           ; On            ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off          ; Off           ;
; Perform gate-level register retiming                               ; Off          ; Off           ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On           ; On            ;
; Auto ROM Replacement                                               ; On           ; On            ;
; Auto RAM Replacement                                               ; On           ; On            ;
; Auto DSP Block Replacement                                         ; On           ; On            ;
; Auto Shift Register Replacement                                    ; On           ; On            ;
; Auto Clock Enable Replacement                                      ; On           ; On            ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On           ; On            ;
; Auto RAM Block Balancing                                           ; On           ; On            ;
; Auto Resource Sharing                                              ; Off          ; Off           ;
; Allow Any RAM Size For Recognition                                 ; Off          ; Off           ;
; Allow Any ROM Size For Recognition                                 ; Off          ; Off           ;
; Allow Any Shift Register Size For Recognition                      ; Off          ; Off           ;
; Enable M512 Memory Blocks                                          ; On           ; On            ;
+--------------------------------------------------------------------+--------------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------+
; 2:1                ; 2 bits    ; 2 LEs         ; 2 LEs                ; 0 LEs                  ; Yes        ; |main|alarmclock:inst11|disp_drive[2]                                                           ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|alarmclock:inst11|second_set0[0]                                                          ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|second_data0[0] ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|second_set0[3]                                  ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|alarmclock:inst11|second_set1[0]                                                          ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|second_data1[0] ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|second_set1[3]                                  ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|alarmclock:inst11|minute_set0[0]                                                          ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|minute_data0[0] ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|minute_set0[3]                                  ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|alarmclock:inst11|minute_set1[0]                                                          ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|minute_data1[0] ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|minute_set1[3]                                  ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|hour_set0[3]                                    ;
; 2:1                ; 3 bits    ; 3 LEs         ; 3 LEs                ; 0 LEs                  ; Yes        ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[2]                                   ;
; 2:1                ; 3 bits    ; 3 LEs         ; 3 LEs                ; 0 LEs                  ; Yes        ; |main|maincontrol:inst3|Function[0]                                                             ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|date_main:inst4|setdate:b2v_inst2|month_set0[1]                                           ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|date_main:inst4|setdate:b2v_inst2|day_set1[1]                                             ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|date_main:inst4|setdate:b2v_inst2|day_set0[2]                                             ;
; 2:1                ; 3 bits    ; 3 LEs         ; 3 LEs                ; 0 LEs                  ; Yes        ; |main|time_disp_select:inst6|auto_disp_drive[0]                                                 ;
; 2:1                ; 32 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |main|fdiv:inst5|CNT3[14]                                                                       ;
; 2:1                ; 32 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |main|fdiv:inst5|CNT2[24]                                                                       ;
; 2:1                ; 32 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |main|fdiv:inst5|CNT1[16]                                                                       ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|alarmclock:inst11|hour_set1[2]                                                            ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|hour_data1[2]      ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|hour_set1[1]                                    ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |main|date_main:inst4|setdate:b2v_inst2|month_set1[1]                                           ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |main|alarmclock:inst11|hour_set0[2]                                                            ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|hour_data0[0]      ;
; 3:1                ; 20 bits   ; 40 LEs        ; 20 LEs               ; 20 LEs                 ; Yes        ; |main|date_main:inst4|datecontrol:b2v_inst1|disp_select[3]                                      ;
; 8:1                ; 4 bits    ; 20 LEs        ; 4 LEs                ; 16 LEs                 ; Yes        ; |main|date_main:inst4|autodate:b2v_inst|day0[2]                                                 ;
; 9:1                ; 4 bits    ; 24 LEs        ; 4 LEs                ; 20 LEs                 ; Yes        ; |main|date_main:inst4|autodate:b2v_inst|month1[2]                                               ;
; 9:1                ; 4 bits    ; 24 LEs        ; 4 LEs                ; 20 LEs                 ; Yes        ; |main|date_main:inst4|autodate:b2v_inst|day1[1]                                                 ;
; 11:1               ; 4 bits    ; 28 LEs        ; 4 LEs                ; 24 LEs                 ; Yes        ; |main|date_main:inst4|autodate:b2v_inst|month0[3]                                               ;
; 2:1                ; 24 bits   ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; No         ; |main|time_auto_and_set:inst1|time_mux:b2v_inst2|minute_0[3]                                    ;
; 2:1                ; 4 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |main|time_disp_select:inst6|disp_drive~0                                                       ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |main|disp_data_mux:inst8|disp_select~10                                                        ;
; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |main|disp_data_mux:inst8|disp_select~6                                                         ;
; 19:1               ; 4 bits    ; 48 LEs        ; 24 LEs               ; 24 LEs                 ; No         ; |main|disp_data_mux:inst8|Data~7                                                                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------+


+----------------------------------------------------+
; User-Specified and Inferred Latches                ;
+-----------------------------------------------+----+
; Latch Name                                    ;    ;
+-----------------------------------------------+----+
; disp_data_mux:inst8|Data[0]                   ;    ;
; disp_data_mux:inst8|Data[1]                   ;    ;
; disp_data_mux:inst8|Data[2]                   ;    ;
; disp_data_mux:inst8|Data[3]                   ;    ;
; disp_data_mux:inst8|disp_select[5]            ;    ;
; disp_data_mux:inst8|disp_select[4]            ;    ;
; disp_data_mux:inst8|disp_select[3]            ;    ;
; disp_data_mux:inst8|disp_select[2]            ;    ;
; disp_data_mux:inst8|disp_select[1]            ;    ;
; disp_data_mux:inst8|disp_select[0]            ;    ;
; time_disp_select:inst6|disp_drive[2]          ;    ;
; time_disp_select:inst6|disp_drive[1]          ;    ;
; time_disp_select:inst6|disp_drive[0]          ;    ;
; time_disp_select:inst6|clk                    ;    ;
; Number of user-specified and inferred latches ; 14 ;
+-----------------------------------------------+----+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 256   ;
; Number of registers using Synchronous Clear  ; 196   ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 132   ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 196   ;
; Number of synthesis-generated cells                    ; 305   ;
; Number of WYSIWYG LUTs                                 ; 196   ;
; Number of synthesis-generated LUTs                     ; 289   ;
; Number of WYSIWYG registers                            ; 196   ;
; Number of synthesis-generated registers                ; 60    ;
; Number of cells with combinational logic only          ; 245   ;
; Number of cells with registers only                    ; 16    ;
; Number of cells with combinational logic and registers ; 240   ;
+--------------------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
main
 |-- time_auto_and_set:inst1
      |-- timepiece_main:b2v_inst1
           |-- hour_counter:b2v_inst
                |-- lpm_counter:hour_data0_rtl_13
                     |-- cntr_e08:auto_generated
                |-- lpm_counter:hour_data1_rtl_16
                     |-- cntr_e08:auto_generated
           |-- minute_counter:b2v_inst1
                |-- lpm_counter:minute_data0_rtl_7
                     |-- cntr_e08:auto_generated
                |-- lpm_counter:minute_data1_rtl_10
                     |-- cntr_e08:auto_generated
           |-- second_counter:b2v_inst2
                |-- lpm_counter:second_data0_rtl_1
                     |-- cntr_e08:auto_generated
                |-- lpm_counter:second_data1_rtl_4
                     |-- cntr_e08:auto_generated
      |-- time_mux:b2v_inst2
      |-- timeset:b2v_inst3
           |-- lpm_counter:hour_set0_rtl_14
                |-- cntr_e08:auto_generated
           |-- lpm_counter:hour_set1_rtl_17
                |-- cntr_e08:auto_generated
           |-- lpm_counter:minute_set0_rtl_8
                |-- cntr_e08:auto_generated
           |-- lpm_counter:minute_set1_rtl_11
                |-- cntr_e08:auto_generated
           |-- lpm_counter:second_set0_rtl_2
                |-- cntr_e08:auto_generated
           |-- lpm_counter:second_set1_rtl_5
                |-- cntr_e08:auto_generated
 |-- stopwatch:inst2
 |-- maincontrol:inst3
 |-- date_main:inst4
      |-- autodate:b2v_inst
           |-- lpm_counter:day0_rtl_23
                |-- cntr_e08:auto_generated
           |-- lpm_counter:day1_rtl_21
                |-- cntr_e08:auto_generated
           |-- lpm_counter:month0_rtl_26
                |-- cntr_e08:auto_generated
      |-- datecontrol:b2v_inst1
      |-- setdate:b2v_inst2
           |-- lpm_counter:day_set0_rtl_22
                |-- cntr_e08:auto_generated
           |-- lpm_counter:day_set1_rtl_20
                |-- cntr_e08:auto_generated
           |-- lpm_counter:month_set0_rtl_25
                |-- cntr_e08:auto_generated
           |-- lpm_counter:month_set1_rtl_24
                |-- cntr_e08:auto_generated
 |-- fdiv:inst5
      |-- lpm_counter:CNT1_rtl_27
           |-- cntr_jd7:auto_generated
      |-- lpm_counter:CNT2_rtl_19
           |-- cntr_jd7:auto_generated
      |-- lpm_counter:CNT3_rtl_18
           |-- cntr_jd7:auto_generated
 |-- time_disp_select:inst6
 |-- disp_data_mux:inst8
 |-- alarmclock:inst11
      |-- lpm_counter:hour_set0_rtl_12
           |-- cntr_e08:auto_generated
      |-- lpm_counter:hour_set1_rtl_15
           |-- cntr_e08:auto_generated
      |-- lpm_counter:minute_set0_rtl_6
           |-- cntr_e08:auto_generated
      |-- lpm_counter:minute_set1_rtl_9
           |-- cntr_e08:auto_generated
      |-- lpm_counter:second_set0_rtl_0
           |-- cntr_e08:auto_generated
      |-- lpm_counter:second_set1_rtl_3
           |-- cntr_e08:auto_generated


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                               ;
+-----------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                    ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                                                                                                     ;
+-----------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------+
; |main                                         ; 501 (0)     ; 256          ; 0           ; 0            ; 0       ; 0         ; 0         ; 18   ; 0            ; 245 (0)      ; 16 (0)            ; 240 (0)          ; 196 (0)         ; |main                                                                                                                                   ;
;    |alarmclock:inst11|                        ; 63 (39)     ; 33           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 30 (30)      ; 7 (7)             ; 26 (2)           ; 24 (0)          ; |main|alarmclock:inst11                                                                                                                 ;
;       |lpm_counter:hour_set0_rtl_12|          ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|alarmclock:inst11|lpm_counter:hour_set0_rtl_12                                                                                    ;
;          |cntr_e08:auto_generated|            ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated                                                            ;
;       |lpm_counter:hour_set1_rtl_15|          ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|alarmclock:inst11|lpm_counter:hour_set1_rtl_15                                                                                    ;
;          |cntr_e08:auto_generated|            ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated                                                            ;
;       |lpm_counter:minute_set0_rtl_6|         ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|alarmclock:inst11|lpm_counter:minute_set0_rtl_6                                                                                   ;
;          |cntr_e08:auto_generated|            ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|alarmclock:inst11|lpm_counter:minute_set0_rtl_6|cntr_e08:auto_generated                                                           ;
;       |lpm_counter:minute_set1_rtl_9|         ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|alarmclock:inst11|lpm_counter:minute_set1_rtl_9                                                                                   ;
;          |cntr_e08:auto_generated|            ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|alarmclock:inst11|lpm_counter:minute_set1_rtl_9|cntr_e08:auto_generated                                                           ;
;       |lpm_counter:second_set0_rtl_0|         ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|alarmclock:inst11|lpm_counter:second_set0_rtl_0                                                                                   ;
;          |cntr_e08:auto_generated|            ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|alarmclock:inst11|lpm_counter:second_set0_rtl_0|cntr_e08:auto_generated                                                           ;
;       |lpm_counter:second_set1_rtl_3|         ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|alarmclock:inst11|lpm_counter:second_set1_rtl_3                                                                                   ;
;          |cntr_e08:auto_generated|            ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|alarmclock:inst11|lpm_counter:second_set1_rtl_3|cntr_e08:auto_generated                                                           ;
;    |date_main:inst4|                          ; 89 (0)      ; 52           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 37 (0)       ; 3 (0)             ; 49 (0)           ; 28 (0)          ; |main|date_main:inst4                                                                                                                   ;
;       |autodate:b2v_inst|                     ; 42 (30)     ; 14           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 28 (28)      ; 2 (2)             ; 12 (0)           ; 12 (0)          ; |main|date_main:inst4|autodate:b2v_inst                                                                                                 ;
;          |lpm_counter:day0_rtl_23|            ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|date_main:inst4|autodate:b2v_inst|lpm_counter:day0_rtl_23                                                                         ;
;             |cntr_e08:auto_generated|         ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|date_main:inst4|autodate:b2v_inst|lpm_counter:day0_rtl_23|cntr_e08:auto_generated                                                 ;
;          |lpm_counter:day1_rtl_21|            ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21                                                                         ;
;             |cntr_e08:auto_generated|         ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated                                                 ;
;          |lpm_counter:month0_rtl_26|          ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|date_main:inst4|autodate:b2v_inst|lpm_counter:month0_rtl_26                                                                       ;
;             |cntr_e08:auto_generated|         ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|date_main:inst4|autodate:b2v_inst|lpm_counter:month0_rtl_26|cntr_e08:auto_generated                                               ;
;       |datecontrol:b2v_inst1|                 ; 25 (25)     ; 20           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 20 (20)          ; 0 (0)           ; |main|date_main:inst4|datecontrol:b2v_inst1                                                                                             ;
;       |setdate:b2v_inst2|                     ; 22 (6)      ; 18           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 4 (4)        ; 1 (1)             ; 17 (1)           ; 16 (0)          ; |main|date_main:inst4|setdate:b2v_inst2                                                                                                 ;
;          |lpm_counter:day_set0_rtl_22|        ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|date_main:inst4|setdate:b2v_inst2|lpm_counter:day_set0_rtl_22                                                                     ;
;             |cntr_e08:auto_generated|         ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|date_main:inst4|setdate:b2v_inst2|lpm_counter:day_set0_rtl_22|cntr_e08:auto_generated                                             ;
;          |lpm_counter:day_set1_rtl_20|        ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|date_main:inst4|setdate:b2v_inst2|lpm_counter:day_set1_rtl_20                                                                     ;
;             |cntr_e08:auto_generated|         ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|date_main:inst4|setdate:b2v_inst2|lpm_counter:day_set1_rtl_20|cntr_e08:auto_generated                                             ;
;          |lpm_counter:month_set0_rtl_25|      ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|date_main:inst4|setdate:b2v_inst2|lpm_counter:month_set0_rtl_25                                                                   ;
;             |cntr_e08:auto_generated|         ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|date_main:inst4|setdate:b2v_inst2|lpm_counter:month_set0_rtl_25|cntr_e08:auto_generated                                           ;
;          |lpm_counter:month_set1_rtl_24|      ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|date_main:inst4|setdate:b2v_inst2|lpm_counter:month_set1_rtl_24                                                                   ;
;             |cntr_e08:auto_generated|         ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|date_main:inst4|setdate:b2v_inst2|lpm_counter:month_set1_rtl_24|cntr_e08:auto_generated                                           ;
;    |disp_data_mux:inst8|                      ; 86 (86)     ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 86 (86)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |main|disp_data_mux:inst8                                                                                                               ;
;    |fdiv:inst5|                               ; 130 (18)    ; 99           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 31 (15)      ; 3 (3)             ; 96 (0)           ; 96 (0)          ; |main|fdiv:inst5                                                                                                                        ;
;       |lpm_counter:CNT1_rtl_27|               ; 41 (0)      ; 32           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 9 (0)        ; 0 (0)             ; 32 (0)           ; 32 (0)          ; |main|fdiv:inst5|lpm_counter:CNT1_rtl_27                                                                                                ;
;          |cntr_jd7:auto_generated|            ; 41 (41)     ; 32           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 9 (9)        ; 0 (0)             ; 32 (32)          ; 32 (32)         ; |main|fdiv:inst5|lpm_counter:CNT1_rtl_27|cntr_jd7:auto_generated                                                                        ;
;       |lpm_counter:CNT2_rtl_19|               ; 39 (0)      ; 32           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 7 (0)        ; 0 (0)             ; 32 (0)           ; 32 (0)          ; |main|fdiv:inst5|lpm_counter:CNT2_rtl_19                                                                                                ;
;          |cntr_jd7:auto_generated|            ; 39 (39)     ; 32           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 32 (32)          ; 32 (32)         ; |main|fdiv:inst5|lpm_counter:CNT2_rtl_19|cntr_jd7:auto_generated                                                                        ;
;       |lpm_counter:CNT3_rtl_18|               ; 32 (0)      ; 32           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (0)           ; 32 (0)          ; |main|fdiv:inst5|lpm_counter:CNT3_rtl_18                                                                                                ;
;          |cntr_jd7:auto_generated|            ; 32 (32)     ; 32           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (32)          ; 32 (32)         ; |main|fdiv:inst5|lpm_counter:CNT3_rtl_18|cntr_jd7:auto_generated                                                                        ;
;    |maincontrol:inst3|                        ; 9 (9)       ; 9            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; 0 (0)           ; |main|maincontrol:inst3                                                                                                                 ;
;    |stopwatch:inst2|                          ; 1 (1)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |main|stopwatch:inst2                                                                                                                   ;
;    |time_auto_and_set:inst1|                  ; 101 (0)     ; 54           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 47 (0)       ; 3 (0)             ; 51 (0)           ; 48 (0)          ; |main|time_auto_and_set:inst1                                                                                                           ;
;       |time_mux:b2v_inst2|                    ; 24 (24)     ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 24 (24)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |main|time_auto_and_set:inst1|time_mux:b2v_inst2                                                                                        ;
;       |timepiece_main:b2v_inst1|              ; 38 (0)      ; 27           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 11 (0)       ; 3 (0)             ; 24 (0)           ; 24 (0)          ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1                                                                                  ;
;          |hour_counter:b2v_inst|              ; 14 (6)      ; 9            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 5 (5)        ; 1 (1)             ; 8 (0)            ; 8 (0)           ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst                                                            ;
;             |lpm_counter:hour_data0_rtl_13|   ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_13                              ;
;                |cntr_e08:auto_generated|      ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_13|cntr_e08:auto_generated      ;
;             |lpm_counter:hour_data1_rtl_16|   ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_16                              ;
;                |cntr_e08:auto_generated|      ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data1_rtl_16|cntr_e08:auto_generated      ;
;          |minute_counter:b2v_inst1|           ; 12 (4)      ; 9            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 3 (3)        ; 1 (1)             ; 8 (0)            ; 8 (0)           ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1                                                         ;
;             |lpm_counter:minute_data0_rtl_7|  ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|lpm_counter:minute_data0_rtl_7                          ;
;                |cntr_e08:auto_generated|      ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|lpm_counter:minute_data0_rtl_7|cntr_e08:auto_generated  ;
;             |lpm_counter:minute_data1_rtl_10| ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|lpm_counter:minute_data1_rtl_10                         ;
;                |cntr_e08:auto_generated|      ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|lpm_counter:minute_data1_rtl_10|cntr_e08:auto_generated ;
;          |second_counter:b2v_inst2|           ; 12 (4)      ; 9            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 3 (3)        ; 1 (1)             ; 8 (0)            ; 8 (0)           ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2                                                         ;
;             |lpm_counter:second_data0_rtl_1|  ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|lpm_counter:second_data0_rtl_1                          ;
;                |cntr_e08:auto_generated|      ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|lpm_counter:second_data0_rtl_1|cntr_e08:auto_generated  ;
;             |lpm_counter:second_data1_rtl_4|  ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|lpm_counter:second_data1_rtl_4                          ;
;                |cntr_e08:auto_generated|      ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|lpm_counter:second_data1_rtl_4|cntr_e08:auto_generated  ;
;       |timeset:b2v_inst3|                     ; 39 (15)     ; 27           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 12 (12)      ; 0 (0)             ; 27 (3)           ; 24 (0)          ; |main|time_auto_and_set:inst1|timeset:b2v_inst3                                                                                         ;
;          |lpm_counter:hour_set0_rtl_14|       ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|lpm_counter:hour_set0_rtl_14                                                            ;
;             |cntr_e08:auto_generated|         ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|lpm_counter:hour_set0_rtl_14|cntr_e08:auto_generated                                    ;
;          |lpm_counter:hour_set1_rtl_17|       ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|lpm_counter:hour_set1_rtl_17                                                            ;
;             |cntr_e08:auto_generated|         ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|lpm_counter:hour_set1_rtl_17|cntr_e08:auto_generated                                    ;
;          |lpm_counter:minute_set0_rtl_8|      ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|lpm_counter:minute_set0_rtl_8                                                           ;
;             |cntr_e08:auto_generated|         ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|lpm_counter:minute_set0_rtl_8|cntr_e08:auto_generated                                   ;
;          |lpm_counter:minute_set1_rtl_11|     ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|lpm_counter:minute_set1_rtl_11                                                          ;
;             |cntr_e08:auto_generated|         ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|lpm_counter:minute_set1_rtl_11|cntr_e08:auto_generated                                  ;
;          |lpm_counter:second_set0_rtl_2|      ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|lpm_counter:second_set0_rtl_2                                                           ;
;             |cntr_e08:auto_generated|         ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|lpm_counter:second_set0_rtl_2|cntr_e08:auto_generated                                   ;
;          |lpm_counter:second_set1_rtl_5|      ; 4 (0)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|lpm_counter:second_set1_rtl_5                                                           ;
;             |cntr_e08:auto_generated|         ; 4 (4)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |main|time_auto_and_set:inst1|timeset:b2v_inst3|lpm_counter:second_set1_rtl_5|cntr_e08:auto_generated                                   ;
;    |time_disp_select:inst6|                   ; 22 (22)     ; 9            ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 13 (13)      ; 0 (0)             ; 9 (9)            ; 0 (0)           ; |main|time_disp_select:inst6                                                                                                            ;
+-----------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.map.eqn.


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                   ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                                        ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; main.bdf                         ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf            ;
; alarmclock.v                     ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/alarmclock.v        ;
; maincontrol.v                    ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/maincontrol.v       ;
; fdiv.v                           ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/fdiv.v              ;
; time_auto_and_set.v              ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_auto_and_set.v ;
; timepiece_main.v                 ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/timepiece_main.v    ;
; hour_counter.v                   ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/hour_counter.v      ;
; minute_counter.v                 ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/minute_counter.v    ;
; second_counter.v                 ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/second_counter.v    ;
; time_mux.v                       ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_mux.v          ;
; timeset.v                        ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/timeset.v           ;
; stopwatch.v                      ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/stopwatch.v         ;
; disp_data_mux.v                  ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v     ;
; date_main.v                      ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/date_main.v         ;
; autodate.v                       ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/autodate.v          ;
; datecontrol.v                    ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/datecontrol.v       ;
; setdate.v                        ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/setdate.v           ;
; time_disp_select.v               ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v  ;
; lpm_counter.tdf                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf         ;
; lpm_constant.inc                 ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_constant.inc        ;
; lpm_decode.inc                   ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_decode.inc          ;
; lpm_add_sub.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_add_sub.inc         ;
; cmpconst.inc                     ; yes             ; d:/altera/quartus42/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; d:/altera/quartus42/libraries/megafunctions/dffeea.inc              ;
; alt_synch_counter.inc            ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter.inc   ;
; alt_synch_counter_f.inc          ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc            ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.inc   ;
; alt_counter_stratix.inc          ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal42.inc                    ; yes             ; d:/altera/quartus42/libraries/megafunctions/aglobal42.inc           ;
; db/cntr_e08.tdf                  ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf     ;
; db/cntr_jd7.tdf                  ; yes             ; E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_jd7.tdf     ;
+----------------------------------+-----------------+---------------------------------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+-----------------------------------+-------------------+
; Resource                          ; Usage             ;
+-----------------------------------+-------------------+
; Logic cells                       ; 501               ;
; Total combinational functions     ; 485               ;
; Total 4-input functions           ; 173               ;
; Total 3-input functions           ; 89                ;
; Total 2-input functions           ; 27                ;
; Total 1-input functions           ; 196               ;
; Total 0-input functions           ; 0                 ;
; Combinational cells for routing   ; 0                 ;
; Total registers                   ; 256               ;
; Total logic cells in carry chains ; 196               ;
; I/O pins                          ; 18                ;
; Maximum fan-out node              ; fdiv:inst5|f200hz ;
; Maximum fan-out                   ; 93                ;
; Total fan-out                     ; 1991              ;
; Average fan-out                   ; 3.84              ;
+-----------------------------------+-------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Sat Jul 15 23:18:01 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off main -c main
Warning: Can't analyze file -- file E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.v is missing
Info: Found 1 design units, including 1 entities, in source file main.bdf
    Info: Found entity 1: main
Info: Using design file alarmclock.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: alarmclock
Info: Using design file maincontrol.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: maincontrol
Info: Using design file fdiv.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: fdiv
Info: Using design file time_auto_and_set.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: time_auto_and_set
Info: Using design file timepiece_main.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: timepiece_main
Info: Using design file hour_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: hour_counter
Info: Using design file minute_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: minute_counter
Info: Using design file second_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: second_counter
Info: Using design file time_mux.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: time_mux
Info: Using design file timeset.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: timeset
Warning: Verilog HDL unsupported feature warning at timeset.v(36): Initial Construct is not supported and will be ignored
Info: Using design file stopwatch.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: stopwatch
Info: Using design file disp_data_mux.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: disp_data_mux
Warning: Verilog HDL Always Construct warning at disp_data_mux.v(97): variable "Data" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at disp_data_mux.v(40): variable disp_select may not be assigned a new value in every possible path through the Always Construct.  Variable disp_select holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at disp_data_mux.v(40): variable Data may not be assigned a new value in every possible path through the Always Construct.  Variable Data holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Using design file date_main.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: date_main
Info: Using design file autodate.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: autodate
Info: Using design file datecontrol.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: datecontrol
Info: Using design file setdate.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: setdate
Info: Using design file time_disp_select.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: time_disp_select
Warning: Verilog HDL Always Construct warning at time_disp_select.v(43): variable clk may not be assigned a new value in every possible path through the Always Construct.  Variable clk holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at time_disp_select.v(43): variable disp_drive may not be assigned a new value in every possible path through the Always Construct.  Variable disp_drive holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Reduced register "date_main:inst4|datecontrol:b2v_inst1|disp_select[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "date_main:inst4|datecontrol:b2v_inst1|disp_select[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "date_main:inst4|autodate:b2v_inst|month1[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "date_main:inst4|autodate:b2v_inst|month1[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "date_main:inst4|autodate:b2v_inst|month1[3]" with stuck data_in port to stuck value GND
Info: Power-up level of register "date_main:inst4|datecontrol:b2v_inst1|auto_disp_drive[1]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "date_main:inst4|datecontrol:b2v_inst1|auto_disp_drive[1]" with stuck data_in port to stuck value VCC
Info: Inferred 28 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "alarmclock:inst11|second_set0[0]~12"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|second_data0[0]~12"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "time_auto_and_set:inst1|timeset:b2v_inst3|second_set0[0]~12"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "alarmclock:inst11|second_set1[0]~12"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|second_data1[0]~20"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "time_auto_and_set:inst1|timeset:b2v_inst3|second_set1[0]~12"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "alarmclock:inst11|minute_set0[0]~12"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|minute_data0[0]~12"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "time_auto_and_set:inst1|timeset:b2v_inst3|minute_set0[0]~12"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "alarmclock:inst11|minute_set1[0]~12"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|minute_data1[0]~20"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "time_auto_and_set:inst1|timeset:b2v_inst3|minute_set1[0]~12"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "alarmclock:inst11|hour_set0[0]~17"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|hour_data0[0]~17"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "time_auto_and_set:inst1|timeset:b2v_inst3|hour_set0[0]~12"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "alarmclock:inst11|hour_set1[0]~12"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|hour_data1[0]~20"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "time_auto_and_set:inst1|timeset:b2v_inst3|hour_set1[0]~12"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: "fdiv:inst5|CNT3[0]~64"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: "fdiv:inst5|CNT2[0]~64"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "date_main:inst4|setdate:b2v_inst2|day_set1[0]~12"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "date_main:inst4|autodate:b2v_inst|day1[0]~157"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "date_main:inst4|setdate:b2v_inst2|day_set0[0]~12"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "date_main:inst4|autodate:b2v_inst|day0[0]~75"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "date_main:inst4|setdate:b2v_inst2|month_set1[0]~12"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "date_main:inst4|setdate:b2v_inst2|month_set0[0]~12"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "date_main:inst4|autodate:b2v_inst|month0[0]~101"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: "fdiv:inst5|CNT1[0]~64"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_e08.tdf
    Info: Found entity 1: cntr_e08
Info: Found 1 design units, including 1 entities, in source file db/cntr_jd7.tdf
    Info: Found entity 1: cntr_jd7
Info: Implemented 519 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 14 output pins
    Info: Implemented 501 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings
    Info: Processing ended: Sat Jul 15 23:18:27 2006
    Info: Elapsed time: 00:00:27


