module Now_Direction_Disp(
							Reset,
							En,
							Clock_1KHz,
							Now_Direction,
							Direction_Disp_Row1,
							Direction_Disp_Row2
							);
input  Reset;
input  En;
input  Clock_1KHz;
input  [1:0] Now_Direction;
output [6:0] Direction_Disp_Row1; //行数据
output [4:0] Direction_Disp_Row2; //列选通

reg [6:0] Direction_Disp_Row1; //5 X 7点阵显示
reg [4:0] Direction_Disp_Row2;

always @(posedge Clock_1KHz)
begin
  if(Direction_Disp_Row2 != 5'b10000)
    Direction_Disp_Row2 <= ( 5'b1 << Direction_Disp_Row2);
  else
    Direction_Disp_Row2 <= 5'b00001;
end

always @(Reset or En or Direction_Disp_Row2 or Now_Direction)
begin
  if((Reset == 1'b1) || (En == 1'b1))
    begin
      Direction_Disp_Row1 <= 7'b1111111;
    end
  else
    begin
      if(Now_Direction == 2'b10) //上升]
        begin
          case(Direction_Disp_Row2)
            5'b00001 : Direction_Disp_Row1 <= 7'b1101111;
            5'b00010 : Direction_Disp_Row1 <= 7'b1011111;
            5'b00100 : Direction_Disp_Row1 <= 7'b0000000;
            5'b01000 : Direction_Disp_Row1 <= 7'b1011111;
            5'b10000 : Direction_Disp_Row1 <= 7'b1101111;
          endcase
        end
      else if(Now_Direction == 2'b01) //下降
        begin
          case(Direction_Disp_Row2)
            5'b00001 : Direction_Disp_Row1 <= 7'b1111011;
            5'b00010 : Direction_Disp_Row1 <= 7'b1111101;
            5'b00100 : Direction_Disp_Row1 <= 7'b0000000;
            5'b01000 : Direction_Disp_Row1 <= 7'b1111101;
            5'b10000 : Direction_Disp_Row1 <= 7'b1111011;
          endcase
        end
      else
        Direction_Disp_Row1 <= 7'b1111111;
    end
end

endmodule