module  Fdiv(Clock_In,Clock_Out);
input  Clock_In;
output Clock_Out;

reg  Clock_Out;
reg  [3:0] CNT;

always  @(posedge Clock_In)

begin
  if(CNT < 4'b1001)
    begin
      CNT <= CNT + 4'b1;
      Clock_Out <= 1'b0;
    end
  else
    begin
      CNT <= 4'b0;
      Clock_Out <= 1'b1;
    end
end

endmodule 