module Position_adc_ctrl( Reset,
                          En,
						  Clk,
						  Adc_Over,
						  Adc_Data,
						  Adc_Cs,
						  Adc_Conv,
						  Adc_Mode,
						  Adc_Rd,
						  Position_Data
						  );
input  Reset;
input  En;  //En_in
input  Clk;
input  Adc_Over;
input  [11:0] Adc_Data; //12 bits A/D
output Adc_Cs;//chip_select
output Adc_Conv;//convert_start
output Adc_Mode;//sleep_mode
output Adc_Rd;//Read Adc_Data
output [11:0] Position_Data;//12 bits position

integer cnt;
reg Adc_Cs;
reg Adc_Conv;
reg Adc_Mode;
reg Adc_Rd;
reg [11:0] Position_Data;//12 bits position

always @(posedge Clk)
//always @(En or Reset or Adc_Over or Adc_Data)
begin
  if((Reset == 1'b1) || (En == 1'b1))
  begin
    Adc_Cs   <= 1'b1;
	Adc_Conv <= 1'b1;
	Adc_Mode <= 1'b0;
	Adc_Rd   <= 1'b1;
    //Position_Data <= 12'b0;
  end
  else
  begin
    Adc_Cs   <= 1'b0;
    Adc_Mode <= 1'b1;
    if(Adc_Over == 1'b1)
    //@(negedge Adc_Over)
    begin
	  Adc_Rd   <= 1'b1;
	  Adc_Conv <= 1'b0;
	end
    //Adc_Cs   <= 1'b0;
	//Adc_Conv <= 1'b0;
	//Adc_Mode <= 1'b1;
	//Adc_Rd   <= 1'b1;
	//if(Adc_Over == 1'b0)
	//else
	if(Adc_Over == 1'b0)
    begin
	  Adc_Rd <= 1'b0;
	  //Position_Data <= Adc_Data; //Read Data
	  Adc_Conv <= 1'b1;
    end
  end
end

always @(negedge Adc_Rd)
begin
  Position_Data <= Adc_Data; //Read Data
end

endmodule