{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 08 01:43:07 2006 " "Info: Processing started: Tue Aug 08 01:43:07 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off Slave_Control_Main -c Slave_Control_Main " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Slave_Control_Main -c Slave_Control_Main" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Now_Direction_Disp:inst2\|Direction_Disp_Row1\[1\]~1130 " "Info: Node \"Now_Direction_Disp:inst2\|Direction_Disp_Row1\[1\]~1130\"" {  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } }  } 0}  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Now_Direction_Disp:inst2\|Direction_Disp_Row1\[2\]~1126 " "Info: Node \"Now_Direction_Disp:inst2\|Direction_Disp_Row1\[2\]~1126\"" {  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } }  } 0}  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Now_Direction_Disp:inst2\|Direction_Disp_Row1\[4\]~1122 " "Info: Node \"Now_Direction_Disp:inst2\|Direction_Disp_Row1\[4\]~1122\"" {  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } }  } 0}  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Now_Direction_Disp:inst2\|Direction_Disp_Row1\[5\]~1118 " "Info: Node \"Now_Direction_Disp:inst2\|Direction_Disp_Row1\[5\]~1118\"" {  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } }  } 0}  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Now_Direction_Disp:inst2\|Direction_Disp_Row1\[6\]~1114 " "Info: Node \"Now_Direction_Disp:inst2\|Direction_Disp_Row1\[6\]~1114\"" {  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } }  } 0}  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Slave_Floor_Select:inst\|CNT1\[4\]~15 " "Info: Node \"Slave_Floor_Select:inst\|CNT1\[4\]~15\"" {  } { { "Slave_Floor_Select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Slave_Floor_Select.v" 19 -1 0 } }  } 0}  } { { "Slave_Floor_Select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Slave_Floor_Select.v" 19 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Slave_Floor_Select:inst\|CNT2\[4\]~15 " "Info: Node \"Slave_Floor_Select:inst\|CNT2\[4\]~15\"" {  } { { "Slave_Floor_Select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Slave_Floor_Select.v" 19 -1 0 } }  } 0}  } { { "Slave_Floor_Select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Slave_Floor_Select.v" 19 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clock_1Hz " "Info: Assuming node \"Clock_1Hz\" is an undefined clock" {  } { { "Slave_Control_Main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Slave_Control_Main.bdf" { { 416 24 192 432 "Clock_1Hz" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Clock_1Hz" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clock_1Hz register Now_Direction_Disp:inst2\|Direction_Disp_Row2\[1\] register Now_Direction_Disp:inst2\|Direction_Disp_Row2\[4\] 172.41 MHz 5.8 ns Internal " "Info: Clock \"Clock_1Hz\" has Internal fmax of 172.41 MHz between source register \"Now_Direction_Disp:inst2\|Direction_Disp_Row2\[1\]\" and destination register \"Now_Direction_Disp:inst2\|Direction_Disp_Row2\[4\]\" (period= 5.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns + Longest register register " "Info: + Longest register to register delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Now_Direction_Disp:inst2\|Direction_Disp_Row2\[1\] 1 REG LC34 31 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC34; Fanout = 31; REG Node = 'Now_Direction_Disp:inst2\|Direction_Disp_Row2\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "" { Now_Direction_Disp:inst2|Direction_Disp_Row2[1] } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(2.600 ns) 3.800 ns Now_Direction_Disp:inst2\|Direction_Disp_Row2\[4\] 2 REG LC16 26 " "Info: 2: + IC(1.200 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC16; Fanout = 26; REG Node = 'Now_Direction_Disp:inst2\|Direction_Disp_Row2\[4\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "3.800 ns" { Now_Direction_Disp:inst2|Direction_Disp_Row2[1] Now_Direction_Disp:inst2|Direction_Disp_Row2[4] } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 68.42 % " "Info: Total cell delay = 2.600 ns ( 68.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns 31.58 % " "Info: Total interconnect delay = 1.200 ns ( 31.58 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "3.800 ns" { Now_Direction_Disp:inst2|Direction_Disp_Row2[1] Now_Direction_Disp:inst2|Direction_Disp_Row2[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { Now_Direction_Disp:inst2|Direction_Disp_Row2[1] Now_Direction_Disp:inst2|Direction_Disp_Row2[4] } { 0.000ns 1.200ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_1Hz destination 1.800 ns + Shortest register " "Info: + Shortest clock path from clock \"Clock_1Hz\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clock_1Hz 1 CLK PIN_87 5 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 5; CLK Node = 'Clock_1Hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "" { Clock_1Hz } "NODE_NAME" } "" } } { "Slave_Control_Main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Slave_Control_Main.bdf" { { 416 24 192 432 "Clock_1Hz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns Now_Direction_Disp:inst2\|Direction_Disp_Row2\[4\] 2 REG LC16 26 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC16; Fanout = 26; REG Node = 'Now_Direction_Disp:inst2\|Direction_Disp_Row2\[4\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "0.500 ns" { Clock_1Hz Now_Direction_Disp:inst2|Direction_Disp_Row2[4] } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "1.800 ns" { Clock_1Hz Now_Direction_Disp:inst2|Direction_Disp_Row2[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { Clock_1Hz Clock_1Hz~out Now_Direction_Disp:inst2|Direction_Disp_Row2[4] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_1Hz source 1.800 ns - Longest register " "Info: - Longest clock path from clock \"Clock_1Hz\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clock_1Hz 1 CLK PIN_87 5 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 5; CLK Node = 'Clock_1Hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "" { Clock_1Hz } "NODE_NAME" } "" } } { "Slave_Control_Main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Slave_Control_Main.bdf" { { 416 24 192 432 "Clock_1Hz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns Now_Direction_Disp:inst2\|Direction_Disp_Row2\[1\] 2 REG LC34 31 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC34; Fanout = 31; REG Node = 'Now_Direction_Disp:inst2\|Direction_Disp_Row2\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "0.500 ns" { Clock_1Hz Now_Direction_Disp:inst2|Direction_Disp_Row2[1] } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "1.800 ns" { Clock_1Hz Now_Direction_Disp:inst2|Direction_Disp_Row2[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { Clock_1Hz Clock_1Hz~out Now_Direction_Disp:inst2|Direction_Disp_Row2[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "1.800 ns" { Clock_1Hz Now_Direction_Disp:inst2|Direction_Disp_Row2[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { Clock_1Hz Clock_1Hz~out Now_Direction_Disp:inst2|Direction_Disp_Row2[4] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "1.800 ns" { Clock_1Hz Now_Direction_Disp:inst2|Direction_Disp_Row2[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { Clock_1Hz Clock_1Hz~out Now_Direction_Disp:inst2|Direction_Disp_Row2[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" {  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 14 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "3.800 ns" { Now_Direction_Disp:inst2|Direction_Disp_Row2[1] Now_Direction_Disp:inst2|Direction_Disp_Row2[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { Now_Direction_Disp:inst2|Direction_Disp_Row2[1] Now_Direction_Disp:inst2|Direction_Disp_Row2[4] } { 0.000ns 1.200ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "1.800 ns" { Clock_1Hz Now_Direction_Disp:inst2|Direction_Disp_Row2[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { Clock_1Hz Clock_1Hz~out Now_Direction_Disp:inst2|Direction_Disp_Row2[4] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "1.800 ns" { Clock_1Hz Now_Direction_Disp:inst2|Direction_Disp_Row2[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { Clock_1Hz Clock_1Hz~out Now_Direction_Disp:inst2|Direction_Disp_Row2[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clock_1Hz Direction_Disp_Row1\[0\] Now_Direction_Disp:inst2\|Direction_Disp_Row2\[1\] 18.000 ns register " "Info: tco from clock \"Clock_1Hz\" to destination pin \"Direction_Disp_Row1\[0\]\" through register \"Now_Direction_Disp:inst2\|Direction_Disp_Row2\[1\]\" is 18.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_1Hz source 1.800 ns + Longest register " "Info: + Longest clock path from clock \"Clock_1Hz\" to source register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clock_1Hz 1 CLK PIN_87 5 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 5; CLK Node = 'Clock_1Hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "" { Clock_1Hz } "NODE_NAME" } "" } } { "Slave_Control_Main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Slave_Control_Main.bdf" { { 416 24 192 432 "Clock_1Hz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 1.800 ns Now_Direction_Disp:inst2\|Direction_Disp_Row2\[1\] 2 REG LC34 31 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC34; Fanout = 31; REG Node = 'Now_Direction_Disp:inst2\|Direction_Disp_Row2\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "0.500 ns" { Clock_1Hz Now_Direction_Disp:inst2|Direction_Disp_Row2[1] } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "1.800 ns" { Clock_1Hz Now_Direction_Disp:inst2|Direction_Disp_Row2[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { Clock_1Hz Clock_1Hz~out Now_Direction_Disp:inst2|Direction_Disp_Row2[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" {  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.000 ns + Longest register pin " "Info: + Longest register to pin delay is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Now_Direction_Disp:inst2\|Direction_Disp_Row2\[1\] 1 REG LC34 31 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC34; Fanout = 31; REG Node = 'Now_Direction_Disp:inst2\|Direction_Disp_Row2\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "" { Now_Direction_Disp:inst2|Direction_Disp_Row2[1] } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(2.600 ns) 3.800 ns Now_Direction_Disp:inst2\|Direction_Disp_Row1~1136 2 COMB LC9 1 " "Info: 2: + IC(1.200 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC9; Fanout = 1; COMB Node = 'Now_Direction_Disp:inst2\|Direction_Disp_Row1~1136'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "3.800 ns" { Now_Direction_Disp:inst2|Direction_Disp_Row2[1] Now_Direction_Disp:inst2|Direction_Disp_Row1~1136 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 5.600 ns Now_Direction_Disp:inst2\|Direction_Disp_Row1~1060 3 COMB LC10 3 " "Info: 3: + IC(0.000 ns) + CELL(1.800 ns) = 5.600 ns; Loc. = LC10; Fanout = 3; COMB Node = 'Now_Direction_Disp:inst2\|Direction_Disp_Row1~1060'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "1.800 ns" { Now_Direction_Disp:inst2|Direction_Disp_Row1~1136 Now_Direction_Disp:inst2|Direction_Disp_Row1~1060 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 10.200 ns Now_Direction_Disp:inst2\|Direction_Disp_Row1\[6\]~1114 4 COMB LOOP LC38 5 " "Info: 4: + IC(0.000 ns) + CELL(4.600 ns) = 10.200 ns; Loc. = LC38; Fanout = 5; COMB LOOP Node = 'Now_Direction_Disp:inst2\|Direction_Disp_Row1\[6\]~1114'" { { "Info" "ITDB_PART_OF_SCC" "Now_Direction_Disp:inst2\|Direction_Disp_Row1\[6\]~1114 LC38 " "Info: Loc. = LC38; Node \"Now_Direction_Disp:inst2\|Direction_Disp_Row1\[6\]~1114\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "" { Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1114 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "" { Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1114 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "4.600 ns" { Now_Direction_Disp:inst2|Direction_Disp_Row1~1060 Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1114 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(3.500 ns) 14.800 ns Now_Direction_Disp:inst2\|Direction_Disp_Row1\[6\]~1134 5 COMB LC33 1 " "Info: 5: + IC(1.100 ns) + CELL(3.500 ns) = 14.800 ns; Loc. = LC33; Fanout = 1; COMB Node = 'Now_Direction_Disp:inst2\|Direction_Disp_Row1\[6\]~1134'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "4.600 ns" { Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1114 Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1134 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 15.000 ns Direction_Disp_Row1\[0\] 6 PIN PIN_40 0 " "Info: 6: + IC(0.000 ns) + CELL(0.200 ns) = 15.000 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'Direction_Disp_Row1\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "0.200 ns" { Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1134 Direction_Disp_Row1[0] } "NODE_NAME" } "" } } { "Slave_Control_Main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Slave_Control_Main.bdf" { { 384 536 761 400 "Direction_Disp_Row1\[6..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.700 ns 84.67 % " "Info: Total cell delay = 12.700 ns ( 84.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 15.33 % " "Info: Total interconnect delay = 2.300 ns ( 15.33 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "15.000 ns" { Now_Direction_Disp:inst2|Direction_Disp_Row2[1] Now_Direction_Disp:inst2|Direction_Disp_Row1~1136 Now_Direction_Disp:inst2|Direction_Disp_Row1~1060 Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1114 Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1134 Direction_Disp_Row1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "15.000 ns" { Now_Direction_Disp:inst2|Direction_Disp_Row2[1] Now_Direction_Disp:inst2|Direction_Disp_Row1~1136 Now_Direction_Disp:inst2|Direction_Disp_Row1~1060 Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1114 Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1134 Direction_Disp_Row1[0] } { 0.000ns 1.200ns 0.000ns 0.000ns 1.100ns 0.000ns } { 0.000ns 2.600ns 1.800ns 4.600ns 3.500ns 0.200ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "1.800 ns" { Clock_1Hz Now_Direction_Disp:inst2|Direction_Disp_Row2[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { Clock_1Hz Clock_1Hz~out Now_Direction_Disp:inst2|Direction_Disp_Row2[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.500ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "15.000 ns" { Now_Direction_Disp:inst2|Direction_Disp_Row2[1] Now_Direction_Disp:inst2|Direction_Disp_Row1~1136 Now_Direction_Disp:inst2|Direction_Disp_Row1~1060 Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1114 Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1134 Direction_Disp_Row1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "15.000 ns" { Now_Direction_Disp:inst2|Direction_Disp_Row2[1] Now_Direction_Disp:inst2|Direction_Disp_Row1~1136 Now_Direction_Disp:inst2|Direction_Disp_Row1~1060 Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1114 Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1134 Direction_Disp_Row1[0] } { 0.000ns 1.200ns 0.000ns 0.000ns 1.100ns 0.000ns } { 0.000ns 2.600ns 1.800ns 4.600ns 3.500ns 0.200ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "Reset Direction_Disp_Row1\[0\] 14.300 ns Longest " "Info: Longest tpd from source pin \"Reset\" to destination pin \"Direction_Disp_Row1\[0\]\" is 14.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Reset 1 PIN PIN_61 40 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_61; Fanout = 40; PIN Node = 'Reset'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "" { Reset } "NODE_NAME" } "" } } { "Slave_Control_Main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Slave_Control_Main.bdf" { { 120 24 192 136 "Reset" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(3.500 ns) 4.900 ns Now_Direction_Disp:inst2\|Direction_Disp_Row1~1060 2 COMB LC10 3 " "Info: 2: + IC(1.200 ns) + CELL(3.500 ns) = 4.900 ns; Loc. = LC10; Fanout = 3; COMB Node = 'Now_Direction_Disp:inst2\|Direction_Disp_Row1~1060'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "4.700 ns" { Reset Now_Direction_Disp:inst2|Direction_Disp_Row1~1060 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.500 ns Now_Direction_Disp:inst2\|Direction_Disp_Row1\[6\]~1114 3 COMB LOOP LC38 5 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.500 ns; Loc. = LC38; Fanout = 5; COMB LOOP Node = 'Now_Direction_Disp:inst2\|Direction_Disp_Row1\[6\]~1114'" { { "Info" "ITDB_PART_OF_SCC" "Now_Direction_Disp:inst2\|Direction_Disp_Row1\[6\]~1114 LC38 " "Info: Loc. = LC38; Node \"Now_Direction_Disp:inst2\|Direction_Disp_Row1\[6\]~1114\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "" { Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1114 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "" { Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1114 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "4.600 ns" { Now_Direction_Disp:inst2|Direction_Disp_Row1~1060 Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1114 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(3.500 ns) 14.100 ns Now_Direction_Disp:inst2\|Direction_Disp_Row1\[6\]~1134 4 COMB LC33 1 " "Info: 4: + IC(1.100 ns) + CELL(3.500 ns) = 14.100 ns; Loc. = LC33; Fanout = 1; COMB Node = 'Now_Direction_Disp:inst2\|Direction_Disp_Row1\[6\]~1134'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "4.600 ns" { Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1114 Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1134 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Now_Direction_Disp.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 14.300 ns Direction_Disp_Row1\[0\] 5 PIN PIN_40 0 " "Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 14.300 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'Direction_Disp_Row1\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "0.200 ns" { Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1134 Direction_Disp_Row1[0] } "NODE_NAME" } "" } } { "Slave_Control_Main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/Slave_Control_Main.bdf" { { 384 536 761 400 "Direction_Disp_Row1\[6..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.000 ns 83.92 % " "Info: Total cell delay = 12.000 ns ( 83.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 16.08 % " "Info: Total interconnect delay = 2.300 ns ( 16.08 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main_cmp.qrpt" Compiler "Slave_Control_Main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/db/Slave_Control_Main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Slave_Control_Main/" "" "14.300 ns" { Reset Now_Direction_Disp:inst2|Direction_Disp_Row1~1060 Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1114 Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1134 Direction_Disp_Row1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "14.300 ns" { Reset Reset~out Now_Direction_Disp:inst2|Direction_Disp_Row1~1060 Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1114 Now_Direction_Disp:inst2|Direction_Disp_Row1[6]~1134 Direction_Disp_Row1[0] } { 0.000ns 0.000ns 1.200ns 0.000ns 1.100ns 0.000ns } { 0.000ns 0.200ns 3.500ns 4.600ns 3.500ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 08 01:43:09 2006 " "Info: Processing ended: Tue Aug 08 01:43:09 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}
