module Sample_Ctrl(
					En,
					Reset,
					Adc_Busy,
					//Adc_Conv,
					Sample_Ctrl_out					
					);
input  En;
input  Reset;
input  Adc_Busy;
//output Adc_Conv;
output Sample_Ctrl_out;

//reg Adc_Conv;
reg Sample_Ctrl_out;

always @(En or Reset or Adc_Busy)
begin
  if((Reset == 1'b1) || (En == 1'b1))
  begin
    //Adc_Conv <= 1'b1;
    Sample_Ctrl_out <= 1'b0;
  end
  else
  begin
    if(Adc_Busy == 1'b0)
      Sample_Ctrl_out <= 1'b1;
    else
      Sample_Ctrl_out <= 1'b0;      
  end
end

endmodule 