{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 08 11:09:09 2006 " "Info: Processing started: Tue Aug 08 11:09:09 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off Buffer_3 -c Buffer_3 " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Buffer_3 -c Buffer_3" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "G1_L Y8 10.500 ns Longest " "Info: Longest tpd from source pin \"G1_L\" to destination pin \"Y8\" is 10.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns G1_L 1 PIN PIN_18 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_18; Fanout = 1; PIN Node = 'G1_L'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Buffer_3/db/Buffer_3_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Buffer_3/db/Buffer_3_cmp.qrpt" Compiler "Buffer_3" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Buffer_3/db/Buffer_3.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Buffer_3/" "" "" { G1_L } "NODE_NAME" } "" } } { "Buffer_3.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Buffer_3/Buffer_3.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns always0~14 2 COMB LC14 8 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC14; Fanout = 8; COMB Node = 'always0~14'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Buffer_3/db/Buffer_3_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Buffer_3/db/Buffer_3_cmp.qrpt" Compiler "Buffer_3" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Buffer_3/db/Buffer_3.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Buffer_3/" "" "4.600 ns" { G1_L always0~14 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(4.700 ns) 10.500 ns Y8 3 PIN PIN_6 0 " "Info: 3: + IC(1.000 ns) + CELL(4.700 ns) = 10.500 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'Y8'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Buffer_3/db/Buffer_3_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Buffer_3/db/Buffer_3_cmp.qrpt" Compiler "Buffer_3" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Buffer_3/db/Buffer_3.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Buffer_3/" "" "5.700 ns" { always0~14 Y8 } "NODE_NAME" } "" } } { "Buffer_3.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Buffer_3/Buffer_3.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns 80.95 % " "Info: Total cell delay = 8.500 ns ( 80.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 19.05 % " "Info: Total interconnect delay = 2.000 ns ( 19.05 % )" {  } {  } 0}  } { { "D:/戴仙金/verilog/源代码/第2章/Buffer_3/db/Buffer_3_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Buffer_3/db/Buffer_3_cmp.qrpt" Compiler "Buffer_3" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Buffer_3/db/Buffer_3.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Buffer_3/" "" "10.500 ns" { G1_L always0~14 Y8 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "10.500 ns" { G1_L G1_L~out always0~14 Y8 } { 0.000ns 0.000ns 1.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.700ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 08 11:09:09 2006 " "Info: Processing ended: Tue Aug 08 11:09:09 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}
