{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 08 21:34:50 2006 " "Info: Processing started: Tue Aug 08 21:34:50 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off Fdiv -c Fdiv " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Fdiv -c Fdiv" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Fdiv.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Fdiv.v" { { "Info" "ISGN_ENTITY_NAME" "1 Fdiv " "Info: Found entity 1: Fdiv" {  } { { "Fdiv.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Fdiv/Fdiv.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "CNT\[0\]~4 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"CNT\[0\]~4\"" {  } { { "Fdiv.v" "CNT\[0\]~4" { Text "D:/戴仙金/verilog/源代码/第2章/Fdiv/Fdiv.v" 21 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "Clock_In " "Info: Promoted clock signal driven by pin \"Clock_In\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "7 " "Info: Implemented 7 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "5 " "Info: Implemented 5 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 08 21:34:53 2006 " "Info: Processing ended: Tue Aug 08 21:34:53 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}
