{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Aug 04 16:06:27 2006 " "Info: Processing started: Fri Aug 04 16:06:27 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off Current_Adjust -c Current_Adjust " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Current_Adjust -c Current_Adjust" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "Current_Data\[8\] Current_Adjust_Out 9.600 ns Longest " "Info: Longest tpd from source pin \"Current_Data\[8\]\" to destination pin \"Current_Adjust_Out\" is 9.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Current_Data\[8\] 1 PIN PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 1; PIN Node = 'Current_Data\[8\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/db/Current_Adjust_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/db/Current_Adjust_cmp.qrpt" Compiler "Current_Adjust" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/db/Current_Adjust.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/" "" "" { Current_Data[8] } "NODE_NAME" } "" } } { "Current_Adjust.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/Current_Adjust.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns always0~131 2 COMB LC2 1 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC2; Fanout = 1; COMB Node = 'always0~131'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/db/Current_Adjust_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/db/Current_Adjust_cmp.qrpt" Compiler "Current_Adjust" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/db/Current_Adjust.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/" "" "4.600 ns" { Current_Data[8] always0~131 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 9.400 ns Current_Adjust_Out~10 3 COMB LC1 1 " "Info: 3: + IC(1.000 ns) + CELL(3.600 ns) = 9.400 ns; Loc. = LC1; Fanout = 1; COMB Node = 'Current_Adjust_Out~10'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/db/Current_Adjust_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/db/Current_Adjust_cmp.qrpt" Compiler "Current_Adjust" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/db/Current_Adjust.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/" "" "4.600 ns" { always0~131 Current_Adjust_Out~10 } "NODE_NAME" } "" } } { "Current_Adjust.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/Current_Adjust.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 9.600 ns Current_Adjust_Out 4 PIN PIN_4 0 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 9.600 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'Current_Adjust_Out'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/db/Current_Adjust_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/db/Current_Adjust_cmp.qrpt" Compiler "Current_Adjust" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/db/Current_Adjust.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/" "" "0.200 ns" { Current_Adjust_Out~10 Current_Adjust_Out } "NODE_NAME" } "" } } { "Current_Adjust.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/Current_Adjust.v" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.600 ns 79.17 % " "Info: Total cell delay = 7.600 ns ( 79.17 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.83 % " "Info: Total interconnect delay = 2.000 ns ( 20.83 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/db/Current_Adjust_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/db/Current_Adjust_cmp.qrpt" Compiler "Current_Adjust" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/db/Current_Adjust.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_Adjust/" "" "9.600 ns" { Current_Data[8] always0~131 Current_Adjust_Out~10 Current_Adjust_Out } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "9.600 ns" { Current_Data[8] Current_Data[8]~out always0~131 Current_Adjust_Out~10 Current_Adjust_Out } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Aug 04 16:06:28 2006 " "Info: Processing ended: Fri Aug 04 16:06:28 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}
