--A1L431Q is fifo_out[15]~reg0
--operation mode is normal

A1L431Q_lut_out = A1L42 # B1_q[15] & A1L32 & !A1L07;
A1L431Q = DFFEA(A1L431Q_lut_out, clock, , , , , );


--A1L231Q is fifo_out[14]~reg0
--operation mode is normal

A1L231Q_lut_out = A1L62 # A1L32 & B1_q[14] & !A1L07;
A1L231Q = DFFEA(A1L231Q_lut_out, clock, , , , , );


--A1L031Q is fifo_out[13]~reg0
--operation mode is normal

A1L031Q_lut_out = A1L82 # A1L32 & B1_q[13] & !A1L07;
A1L031Q = DFFEA(A1L031Q_lut_out, clock, , , , , );


--A1L821Q is fifo_out[12]~reg0
--operation mode is normal

A1L821Q_lut_out = A1L03 # A1L32 & B1_q[12] & !A1L07;
A1L821Q = DFFEA(A1L821Q_lut_out, clock, , , , , );


--A1L621Q is fifo_out[11]~reg0
--operation mode is normal

A1L621Q_lut_out = A1L23 # A1L32 & B1_q[11] & !A1L07;
A1L621Q = DFFEA(A1L621Q_lut_out, clock, , , , , );


--A1L421Q is fifo_out[10]~reg0
--operation mode is normal

A1L421Q_lut_out = A1L43 # A1L32 & B1_q[10] & !A1L07;
A1L421Q = DFFEA(A1L421Q_lut_out, clock, , , , , );


--A1L221Q is fifo_out[9]~reg0
--operation mode is normal

A1L221Q_lut_out = A1L63 # A1L32 & B1_q[9] & !A1L07;
A1L221Q = DFFEA(A1L221Q_lut_out, clock, , , , , );


--A1L021Q is fifo_out[8]~reg0
--operation mode is normal

A1L021Q_lut_out = A1L83 # A1L32 & B1_q[8] & !A1L07;
A1L021Q = DFFEA(A1L021Q_lut_out, clock, , , , , );


--A1L811Q is fifo_out[7]~reg0
--operation mode is normal

A1L811Q_lut_out = A1L04 # A1L32 & B1_q[7] & !A1L07;
A1L811Q = DFFEA(A1L811Q_lut_out, clock, , , , , );


--A1L611Q is fifo_out[6]~reg0
--operation mode is normal

A1L611Q_lut_out = A1L24 # A1L32 & B1_q[6] & !A1L07;
A1L611Q = DFFEA(A1L611Q_lut_out, clock, , , , , );


--A1L411Q is fifo_out[5]~reg0
--operation mode is normal

A1L411Q_lut_out = A1L44 # A1L32 & B1_q[5] & !A1L07;
A1L411Q = DFFEA(A1L411Q_lut_out, clock, , , , , );


--A1L211Q is fifo_out[4]~reg0
--operation mode is normal

A1L211Q_lut_out = A1L64 # A1L32 & B1_q[4] & !A1L07;
A1L211Q = DFFEA(A1L211Q_lut_out, clock, , , , , );


--A1L011Q is fifo_out[3]~reg0
--operation mode is normal

A1L011Q_lut_out = A1L84 # A1L32 & B1_q[3] & !A1L07;
A1L011Q = DFFEA(A1L011Q_lut_out, clock, , , , , );


--A1L801Q is fifo_out[2]~reg0
--operation mode is normal

A1L801Q_lut_out = A1L05 # A1L32 & B1_q[2] & !A1L07;
A1L801Q = DFFEA(A1L801Q_lut_out, clock, , , , , );


--A1L601Q is fifo_out[1]~reg0
--operation mode is normal

A1L601Q_lut_out = A1L25 # A1L32 & B1_q[1] & !A1L07;
A1L601Q = DFFEA(A1L601Q_lut_out, clock, , , , , );


--A1L401Q is fifo_out[0]~reg0
--operation mode is normal

A1L401Q_lut_out = A1L45 # A1L32 & B1_q[0] & !A1L07;
A1L401Q = DFFEA(A1L401Q_lut_out, clock, , , , , );


--counter[3] is counter[3]
--operation mode is normal

counter[3]_lut_out = !reset & counter[3] $ (!A1L55 & A1L12);
counter[3] = DFFEA(counter[3]_lut_out, clock, , , , , );


--counter[2] is counter[2]
--operation mode is normal

counter[2]_lut_out = !reset & counter[2] $ (!A1L65 & A1L12);
counter[2] = DFFEA(counter[2]_lut_out, clock, , , , , );


--counter[1] is counter[1]
--operation mode is normal

counter[1]_lut_out = !reset & counter[1] $ (A1L12 & A1L75);
counter[1] = DFFEA(counter[1]_lut_out, clock, , , , , );


--counter[0] is counter[0]
--operation mode is normal

counter[0]_lut_out = !reset & counter[0] $ write $ read;
counter[0] = DFFEA(counter[0]_lut_out, clock, , , , , );


--A1L241 is reduce_nor~0
--operation mode is normal

A1L241 = counter[3] # counter[2] # counter[1] # counter[0];


--A1L441 is reduce_nor~5
--operation mode is normal

A1L441 = counter[2] # counter[1] # counter[0] # !counter[3];


--A1L341 is reduce_nor~4
--operation mode is normal

A1L341 = !counter[0] # !counter[1] # !counter[2] # !counter[3];


--A1L22 is Select~4925
--operation mode is normal

A1L22 = A1L431Q & !reset & !read;


--A1L32 is Select~4926
--operation mode is normal

A1L32 = read & !reset;


--A1L42 is Select~4927
--operation mode is normal

A1L42 = A1L22 # fifo_in[15] & A1L07 & A1L32;


--B1_q[15] is altdpram:ram_rtl_0|q[15]
B1_q[15]_data_in = A1L61;
B1_q[15]_write_enable = A1L85;
B1_q[15]_clock_0 = clock;
B1_q[15]_clock_1 = clock;
B1_q[15]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02);
B1_q[15]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56);
B1_q[15] = MEMORY_SEGMENT(B1_q[15]_data_in, B1_q[15]_write_enable, B1_q[15]_clock_0, B1_q[15]_clock_1, , , , VCC, B1_q[15]_write_address, B1_q[15]_read_address);


--A1L52 is Select~4929
--operation mode is normal

A1L52 = A1L231Q & !reset & !read;


--A1L62 is Select~4930
--operation mode is normal

A1L62 = A1L52 # A1L07 & A1L32 & fifo_in[14];


--B1_q[14] is altdpram:ram_rtl_0|q[14]
B1_q[14]_data_in = A1L51;
B1_q[14]_write_enable = A1L85;
B1_q[14]_clock_0 = clock;
B1_q[14]_clock_1 = clock;
B1_q[14]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02);
B1_q[14]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56);
B1_q[14] = MEMORY_SEGMENT(B1_q[14]_data_in, B1_q[14]_write_enable, B1_q[14]_clock_0, B1_q[14]_clock_1, , , , VCC, B1_q[14]_write_address, B1_q[14]_read_address);


--A1L72 is Select~4932
--operation mode is normal

A1L72 = A1L031Q & !reset & !read;


--A1L82 is Select~4933
--operation mode is normal

A1L82 = A1L72 # A1L07 & A1L32 & fifo_in[13];


--B1_q[13] is altdpram:ram_rtl_0|q[13]
B1_q[13]_data_in = A1L41;
B1_q[13]_write_enable = A1L85;
B1_q[13]_clock_0 = clock;
B1_q[13]_clock_1 = clock;
B1_q[13]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02);
B1_q[13]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56);
B1_q[13] = MEMORY_SEGMENT(B1_q[13]_data_in, B1_q[13]_write_enable, B1_q[13]_clock_0, B1_q[13]_clock_1, , , , VCC, B1_q[13]_write_address, B1_q[13]_read_address);


--A1L92 is Select~4935
--operation mode is normal

A1L92 = A1L821Q & !reset & !read;


--A1L03 is Select~4936
--operation mode is normal

A1L03 = A1L92 # A1L07 & A1L32 & fifo_in[12];


--B1_q[12] is altdpram:ram_rtl_0|q[12]
B1_q[12]_data_in = A1L31;
B1_q[12]_write_enable = A1L85;
B1_q[12]_clock_0 = clock;
B1_q[12]_clock_1 = clock;
B1_q[12]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02);
B1_q[12]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56);
B1_q[12] = MEMORY_SEGMENT(B1_q[12]_data_in, B1_q[12]_write_enable, B1_q[12]_clock_0, B1_q[12]_clock_1, , , , VCC, B1_q[12]_write_address, B1_q[12]_read_address);


--A1L13 is Select~4938
--operation mode is normal

A1L13 = A1L621Q & !reset & !read;


--A1L23 is Select~4939
--operation mode is normal

A1L23 = A1L13 # A1L07 & A1L32 & fifo_in[11];


--B1_q[11] is altdpram:ram_rtl_0|q[11]
B1_q[11]_data_in = A1L21;
B1_q[11]_write_enable = A1L85;
B1_q[11]_clock_0 = clock;
B1_q[11]_clock_1 = clock;
B1_q[11]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02);
B1_q[11]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56);
B1_q[11] = MEMORY_SEGMENT(B1_q[11]_data_in, B1_q[11]_write_enable, B1_q[11]_clock_0, B1_q[11]_clock_1, , , , VCC, B1_q[11]_write_address, B1_q[11]_read_address);


--A1L33 is Select~4941
--operation mode is normal

A1L33 = A1L421Q & !reset & !read;


--A1L43 is Select~4942
--operation mode is normal

A1L43 = A1L33 # A1L07 & A1L32 & fifo_in[10];


--B1_q[10] is altdpram:ram_rtl_0|q[10]
B1_q[10]_data_in = A1L11;
B1_q[10]_write_enable = A1L85;
B1_q[10]_clock_0 = clock;
B1_q[10]_clock_1 = clock;
B1_q[10]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02);
B1_q[10]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56);
B1_q[10] = MEMORY_SEGMENT(B1_q[10]_data_in, B1_q[10]_write_enable, B1_q[10]_clock_0, B1_q[10]_clock_1, , , , VCC, B1_q[10]_write_address, B1_q[10]_read_address);


--A1L53 is Select~4944
--operation mode is normal

A1L53 = A1L221Q & !reset & !read;


--A1L63 is Select~4945
--operation mode is normal

A1L63 = A1L53 # A1L07 & A1L32 & fifo_in[9];


--B1_q[9] is altdpram:ram_rtl_0|q[9]
B1_q[9]_data_in = A1L01;
B1_q[9]_write_enable = A1L85;
B1_q[9]_clock_0 = clock;
B1_q[9]_clock_1 = clock;
B1_q[9]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02);
B1_q[9]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56);
B1_q[9] = MEMORY_SEGMENT(B1_q[9]_data_in, B1_q[9]_write_enable, B1_q[9]_clock_0, B1_q[9]_clock_1, , , , VCC, B1_q[9]_write_address, B1_q[9]_read_address);


--A1L73 is Select~4947
--operation mode is normal

A1L73 = A1L021Q & !reset & !read;


--A1L83 is Select~4948
--operation mode is normal

A1L83 = A1L73 # A1L07 & A1L32 & fifo_in[8];


--B1_q[8] is altdpram:ram_rtl_0|q[8]
B1_q[8]_data_in = A1L9;
B1_q[8]_write_enable = A1L85;
B1_q[8]_clock_0 = clock;
B1_q[8]_clock_1 = clock;
B1_q[8]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02);
B1_q[8]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56);
B1_q[8] = MEMORY_SEGMENT(B1_q[8]_data_in, B1_q[8]_write_enable, B1_q[8]_clock_0, B1_q[8]_clock_1, , , , VCC, B1_q[8]_write_address, B1_q[8]_read_address);


--A1L93 is Select~4950
--operation mode is normal

A1L93 = A1L811Q & !reset & !read;


--A1L04 is Select~4951
--operation mode is normal

A1L04 = A1L93 # A1L07 & A1L32 & fifo_in[7];


--B1_q[7] is altdpram:ram_rtl_0|q[7]
B1_q[7]_data_in = A1L8;
B1_q[7]_write_enable = A1L85;
B1_q[7]_clock_0 = clock;
B1_q[7]_clock_1 = clock;
B1_q[7]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02);
B1_q[7]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56);
B1_q[7] = MEMORY_SEGMENT(B1_q[7]_data_in, B1_q[7]_write_enable, B1_q[7]_clock_0, B1_q[7]_clock_1, , , , VCC, B1_q[7]_write_address, B1_q[7]_read_address);


--A1L14 is Select~4953
--operation mode is normal

A1L14 = A1L611Q & !reset & !read;


--A1L24 is Select~4954
--operation mode is normal

A1L24 = A1L14 # A1L07 & A1L32 & fifo_in[6];


--B1_q[6] is altdpram:ram_rtl_0|q[6]
B1_q[6]_data_in = A1L7;
B1_q[6]_write_enable = A1L85;
B1_q[6]_clock_0 = clock;
B1_q[6]_clock_1 = clock;
B1_q[6]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02);
B1_q[6]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56);
B1_q[6] = MEMORY_SEGMENT(B1_q[6]_data_in, B1_q[6]_write_enable, B1_q[6]_clock_0, B1_q[6]_clock_1, , , , VCC, B1_q[6]_write_address, B1_q[6]_read_address);


--A1L34 is Select~4956
--operation mode is normal

A1L34 = A1L411Q & !reset & !read;


--A1L44 is Select~4957
--operation mode is normal

A1L44 = A1L34 # A1L07 & A1L32 & fifo_in[5];


--B1_q[5] is altdpram:ram_rtl_0|q[5]
B1_q[5]_data_in = A1L6;
B1_q[5]_write_enable = A1L85;
B1_q[5]_clock_0 = clock;
B1_q[5]_clock_1 = clock;
B1_q[5]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02);
B1_q[5]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56);
B1_q[5] = MEMORY_SEGMENT(B1_q[5]_data_in, B1_q[5]_write_enable, B1_q[5]_clock_0, B1_q[5]_clock_1, , , , VCC, B1_q[5]_write_address, B1_q[5]_read_address);


--A1L54 is Select~4959
--operation mode is normal

A1L54 = A1L211Q & !reset & !read;


--A1L64 is Select~4960
--operation mode is normal

A1L64 = A1L54 # A1L07 & A1L32 & fifo_in[4];


--B1_q[4] is altdpram:ram_rtl_0|q[4]
B1_q[4]_data_in = A1L5;
B1_q[4]_write_enable = A1L85;
B1_q[4]_clock_0 = clock;
B1_q[4]_clock_1 = clock;
B1_q[4]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02);
B1_q[4]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56);
B1_q[4] = MEMORY_SEGMENT(B1_q[4]_data_in, B1_q[4]_write_enable, B1_q[4]_clock_0, B1_q[4]_clock_1, , , , VCC, B1_q[4]_write_address, B1_q[4]_read_address);


--A1L74 is Select~4962
--operation mode is normal

A1L74 = A1L011Q & !reset & !read;


--A1L84 is Select~4963
--operation mode is normal

A1L84 = A1L74 # A1L07 & A1L32 & fifo_in[3];


--B1_q[3] is altdpram:ram_rtl_0|q[3]
B1_q[3]_data_in = A1L4;
B1_q[3]_write_enable = A1L85;
B1_q[3]_clock_0 = clock;
B1_q[3]_clock_1 = clock;
B1_q[3]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02);
B1_q[3]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56);
B1_q[3] = MEMORY_SEGMENT(B1_q[3]_data_in, B1_q[3]_write_enable, B1_q[3]_clock_0, B1_q[3]_clock_1, , , , VCC, B1_q[3]_write_address, B1_q[3]_read_address);


--A1L94 is Select~4965
--operation mode is normal

A1L94 = A1L801Q & !reset & !read;


--A1L05 is Select~4966
--operation mode is normal

A1L05 = A1L94 # A1L07 & A1L32 & fifo_in[2];


--B1_q[2] is altdpram:ram_rtl_0|q[2]
B1_q[2]_data_in = A1L3;
B1_q[2]_write_enable = A1L85;
B1_q[2]_clock_0 = clock;
B1_q[2]_clock_1 = clock;
B1_q[2]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02);
B1_q[2]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56);
B1_q[2] = MEMORY_SEGMENT(B1_q[2]_data_in, B1_q[2]_write_enable, B1_q[2]_clock_0, B1_q[2]_clock_1, , , , VCC, B1_q[2]_write_address, B1_q[2]_read_address);


--A1L15 is Select~4968
--operation mode is normal

A1L15 = A1L601Q & !reset & !read;


--A1L25 is Select~4969
--operation mode is normal

A1L25 = A1L15 # A1L07 & A1L32 & fifo_in[1];


--B1_q[1] is altdpram:ram_rtl_0|q[1]
B1_q[1]_data_in = A1L2;
B1_q[1]_write_enable = A1L85;
B1_q[1]_clock_0 = clock;
B1_q[1]_clock_1 = clock;
B1_q[1]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02);
B1_q[1]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56);
B1_q[1] = MEMORY_SEGMENT(B1_q[1]_data_in, B1_q[1]_write_enable, B1_q[1]_clock_0, B1_q[1]_clock_1, , , , VCC, B1_q[1]_write_address, B1_q[1]_read_address);


--A1L35 is Select~4971
--operation mode is normal

A1L35 = A1L401Q & !reset & !read;


--A1L45 is Select~4972
--operation mode is normal

A1L45 = A1L35 # A1L07 & A1L32 & fifo_in[0];


--B1_q[0] is altdpram:ram_rtl_0|q[0]
B1_q[0]_data_in = A1L1;
B1_q[0]_write_enable = A1L85;
B1_q[0]_clock_0 = clock;
B1_q[0]_clock_1 = clock;
B1_q[0]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02);
B1_q[0]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56);
B1_q[0] = MEMORY_SEGMENT(B1_q[0]_data_in, B1_q[0]_write_enable, B1_q[0]_clock_0, B1_q[0]_clock_1, , , , VCC, B1_q[0]_write_address, B1_q[0]_read_address);


--A1L55 is Select~4974
--operation mode is normal

A1L55 = read & counter[2] # counter[1] # counter[0] # !read & !counter[0] # !counter[1] # !counter[2];


--A1L12 is Select~478
--operation mode is normal

A1L12 = write $ read;


--A1L65 is Select~4976
--operation mode is normal

A1L65 = read & counter[1] # counter[0] # !read & !counter[0] # !counter[1];


--A1L75 is Select~4978
--operation mode is normal

A1L75 = counter[0] $ read;


--A1L61 is Select~288
--operation mode is normal

A1L61 = write & fifo_in[15];


--A1L85 is Select~4982
--operation mode is normal

A1L85 = write & !reset & A1L241 # !read;


--write_ptr[0] is write_ptr[0]
--operation mode is normal

write_ptr[0]_lut_out = write_ptr[0] & !write & !reset # !A1L17;
write_ptr[0] = DFFEA(write_ptr[0]_lut_out, clock, , , , , );


--A1L71 is Select~289
--operation mode is normal

A1L71 = write_ptr[0] & write;


--write_ptr[1] is write_ptr[1]
--operation mode is normal

write_ptr[1]_lut_out = write_ptr[1] & A1L86 # A1L85 & !write_ptr[0] # !write_ptr[1] & A1L85 & write_ptr[0];
write_ptr[1] = DFFEA(write_ptr[1]_lut_out, clock, , , , , );


--A1L81 is Select~290
--operation mode is normal

A1L81 = write_ptr[1] & write;


--write_ptr[2] is write_ptr[2]
--operation mode is normal

write_ptr[2]_lut_out = write_ptr[2] & A1L86 # A1L85 & !A1L47 # !write_ptr[2] & A1L85 & A1L47;
write_ptr[2] = DFFEA(write_ptr[2]_lut_out, clock, , , , , );


--A1L91 is Select~291
--operation mode is normal

A1L91 = write_ptr[2] & write;


--write_ptr[3] is write_ptr[3]
--operation mode is normal

write_ptr[3]_lut_out = write_ptr[3] & A1L86 # A1L85 & !A1L57 # !write_ptr[3] & A1L85 & A1L57;
write_ptr[3] = DFFEA(write_ptr[3]_lut_out, clock, , , , , );


--A1L02 is Select~292
--operation mode is normal

A1L02 = write_ptr[3] & write;


--read_ptr[0] is read_ptr[0]
--operation mode is normal

read_ptr[0]_lut_out = A1L95 # read_ptr[0] & !reset & !read;
read_ptr[0] = DFFEA(read_ptr[0]_lut_out, clock, , , , , );


--A1L95 is Select~4983
--operation mode is normal

A1L95 = A1L32 & read_ptr[0] $ (A1L241 # !write);


--A1L06 is Select~4984
--operation mode is normal

A1L06 = A1L95 # read_ptr[0] & !reset & !read;


--A1L16 is Select~4985
--operation mode is normal

A1L16 = !reset & write & !A1L241 # !read;


--A1L26 is Select~4986
--operation mode is normal

A1L26 = read & !reset & A1L241 # !write;


--read_ptr[1] is read_ptr[1]
--operation mode is normal

read_ptr[1]_lut_out = read_ptr[1] & A1L16 # A1L26 & !read_ptr[0] # !read_ptr[1] & A1L26 & read_ptr[0];
read_ptr[1] = DFFEA(read_ptr[1]_lut_out, clock, , , , , );


--A1L36 is Select~4987
--operation mode is normal

A1L36 = read_ptr[1] & A1L16 # A1L26 & !read_ptr[0] # !read_ptr[1] & A1L26 & read_ptr[0];


--read_ptr[2] is read_ptr[2]
--operation mode is normal

read_ptr[2]_lut_out = read_ptr[2] & A1L16 # A1L26 & !A1L27 # !read_ptr[2] & A1L26 & A1L27;
read_ptr[2] = DFFEA(read_ptr[2]_lut_out, clock, , , , , );


--A1L27 is add~12
--operation mode is normal

A1L27 = read_ptr[1] & read_ptr[0];


--A1L46 is Select~4988
--operation mode is normal

A1L46 = read_ptr[2] & A1L16 # A1L26 & !A1L27 # !read_ptr[2] & A1L26 & A1L27;


--read_ptr[3] is read_ptr[3]
--operation mode is normal

read_ptr[3]_lut_out = read_ptr[3] & A1L16 # A1L26 & !A1L37 # !read_ptr[3] & A1L26 & A1L37;
read_ptr[3] = DFFEA(read_ptr[3]_lut_out, clock, , , , , );


--A1L37 is add~17
--operation mode is normal

A1L37 = read_ptr[2] & read_ptr[1] & read_ptr[0];


--A1L56 is Select~4989
--operation mode is normal

A1L56 = read_ptr[3] & A1L16 # A1L26 & !A1L37 # !read_ptr[3] & A1L26 & A1L37;


--A1L51 is Select~287
--operation mode is normal

A1L51 = write & fifo_in[14];


--A1L41 is Select~286
--operation mode is normal

A1L41 = write & fifo_in[13];


--A1L31 is Select~285
--operation mode is normal

A1L31 = write & fifo_in[12];


--A1L21 is Select~284
--operation mode is normal

A1L21 = write & fifo_in[11];


--A1L11 is Select~283
--operation mode is normal

A1L11 = write & fifo_in[10];


--A1L01 is Select~282
--operation mode is normal

A1L01 = write & fifo_in[9];


--A1L9 is Select~281
--operation mode is normal

A1L9 = write & fifo_in[8];


--A1L8 is Select~280
--operation mode is normal

A1L8 = write & fifo_in[7];


--A1L7 is Select~279
--operation mode is normal

A1L7 = write & fifo_in[6];


--A1L6 is Select~278
--operation mode is normal

A1L6 = write & fifo_in[5];


--A1L5 is Select~277
--operation mode is normal

A1L5 = write & fifo_in[4];


--A1L4 is Select~276
--operation mode is normal

A1L4 = write & fifo_in[3];


--A1L3 is Select~275
--operation mode is normal

A1L3 = write & fifo_in[2];


--A1L2 is Select~274
--operation mode is normal

A1L2 = write & fifo_in[1];


--A1L1 is Select~273
--operation mode is normal

A1L1 = write & fifo_in[0];


--A1L531 is fifo_out~0
--operation mode is normal

A1L531 = read_ptr[0] $ write_ptr[0];


--A1L66 is Select~4990
--operation mode is normal

A1L66 = !A1L531 & read_ptr[1] $ !write_ptr[1] # !A1L241;


--A1L76 is Select~4991
--operation mode is normal

A1L76 = A1L66 & read_ptr[3] $ !write_ptr[3] # !A1L241;


--A1L07 is Select~5007
--operation mode is normal

A1L07 = (write & read_ptr[2] $ !write_ptr[2] # !A1L241) & CASCADE(A1L76);


--A1L86 is Select~4995
--operation mode is normal

A1L86 = !reset & read & !A1L241 # !write;


--A1L47 is add~72
--operation mode is normal

A1L47 = write_ptr[1] & write_ptr[0];


--A1L57 is add~77
--operation mode is normal

A1L57 = write_ptr[2] & write_ptr[1] & write_ptr[0];


--A1L96 is Select~5001
--operation mode is normal

A1L96 = reset # read # write_ptr[0] # !write;


--A1L17 is Select~5008
--operation mode is normal

A1L17 = (A1L241 $ !write_ptr[0] # !A1L32 # !write) & CASCADE(A1L96);


--reset is reset
--operation mode is input

reset = INPUT();


--read is read
--operation mode is input

read = INPUT();


--fifo_in[15] is fifo_in[15]
--operation mode is input

fifo_in[15] = INPUT();


--clock is clock
--operation mode is input

clock = INPUT();


--fifo_in[14] is fifo_in[14]
--operation mode is input

fifo_in[14] = INPUT();


--fifo_in[13] is fifo_in[13]
--operation mode is input

fifo_in[13] = INPUT();


--fifo_in[12] is fifo_in[12]
--operation mode is input

fifo_in[12] = INPUT();


--fifo_in[11] is fifo_in[11]
--operation mode is input

fifo_in[11] = INPUT();


--fifo_in[10] is fifo_in[10]
--operation mode is input

fifo_in[10] = INPUT();


--fifo_in[9] is fifo_in[9]
--operation mode is input

fifo_in[9] = INPUT();


--fifo_in[8] is fifo_in[8]
--operation mode is input

fifo_in[8] = INPUT();


--fifo_in[7] is fifo_in[7]
--operation mode is input

fifo_in[7] = INPUT();


--fifo_in[6] is fifo_in[6]
--operation mode is input

fifo_in[6] = INPUT();


--fifo_in[5] is fifo_in[5]
--operation mode is input

fifo_in[5] = INPUT();


--fifo_in[4] is fifo_in[4]
--operation mode is input

fifo_in[4] = INPUT();


--fifo_in[3] is fifo_in[3]
--operation mode is input

fifo_in[3] = INPUT();


--fifo_in[2] is fifo_in[2]
--operation mode is input

fifo_in[2] = INPUT();


--fifo_in[1] is fifo_in[1]
--operation mode is input

fifo_in[1] = INPUT();


--fifo_in[0] is fifo_in[0]
--operation mode is input

fifo_in[0] = INPUT();


--write is write
--operation mode is input

write = INPUT();


--fifo_out[15] is fifo_out[15]
--operation mode is output

fifo_out[15] = OUTPUT(A1L431Q);


--fifo_out[14] is fifo_out[14]
--operation mode is output

fifo_out[14] = OUTPUT(A1L231Q);


--fifo_out[13] is fifo_out[13]
--operation mode is output

fifo_out[13] = OUTPUT(A1L031Q);


--fifo_out[12] is fifo_out[12]
--operation mode is output

fifo_out[12] = OUTPUT(A1L821Q);


--fifo_out[11] is fifo_out[11]
--operation mode is output

fifo_out[11] = OUTPUT(A1L621Q);


--fifo_out[10] is fifo_out[10]
--operation mode is output

fifo_out[10] = OUTPUT(A1L421Q);


--fifo_out[9] is fifo_out[9]
--operation mode is output

fifo_out[9] = OUTPUT(A1L221Q);


--fifo_out[8] is fifo_out[8]
--operation mode is output

fifo_out[8] = OUTPUT(A1L021Q);


--fifo_out[7] is fifo_out[7]
--operation mode is output

fifo_out[7] = OUTPUT(A1L811Q);


--fifo_out[6] is fifo_out[6]
--operation mode is output

fifo_out[6] = OUTPUT(A1L611Q);


--fifo_out[5] is fifo_out[5]
--operation mode is output

fifo_out[5] = OUTPUT(A1L411Q);


--fifo_out[4] is fifo_out[4]
--operation mode is output

fifo_out[4] = OUTPUT(A1L211Q);


--fifo_out[3] is fifo_out[3]
--operation mode is output

fifo_out[3] = OUTPUT(A1L011Q);


--fifo_out[2] is fifo_out[2]
--operation mode is output

fifo_out[2] = OUTPUT(A1L801Q);


--fifo_out[1] is fifo_out[1]
--operation mode is output

fifo_out[1] = OUTPUT(A1L601Q);


--fifo_out[0] is fifo_out[0]
--operation mode is output

fifo_out[0] = OUTPUT(A1L401Q);


--fifo_empty is fifo_empty
--operation mode is output

fifo_empty = OUTPUT(!A1L241);


--fifo_half is fifo_half
--operation mode is output

fifo_half = OUTPUT(!A1L441);


--fifo_full is fifo_full
--operation mode is output

fifo_full = OUTPUT(!A1L341);


