Analysis & Synthesis report for trafficlight
Sun May 28 11:10:03 2006
Version 4.2 Build 157 12/07/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Multiplexer Restructuring Statistics (Restructuring Performed)
  5. WYSIWYG Cells
  6. General Register Statistics
  7. Hierarchy
  8. Analysis & Synthesis Resource Utilization by Entity
  9. Analysis & Synthesis Equations
 10. Analysis & Synthesis Source Files Read
 11. Analysis & Synthesis Resource Usage Summary
 12. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun May 28 11:10:03 2006    ;
; Quartus II Version          ; 4.2 Build 157 12/07/2004 SJ Full Version ;
; Revision Name               ; trafficlight                             ;
; Top-level Entity Name       ; trafficlight                             ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 154                                      ;
; Total pins                  ; 19                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 0                                        ;
; Total PLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                     ;
+--------------------------------------------------------------------+--------------+---------------+
; Option                                                             ; Setting      ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Family name                                                        ; Cyclone      ; Stratix       ;
; Use smart compilation                                              ; Normal       ; Normal        ;
; Restructure Multiplexers                                           ; Auto         ; Auto          ;
; Create Debugging Nodes for IP Cores                                ; off          ; off           ;
; Preserve fewer node names                                          ; On           ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off          ; Off           ;
; Verilog Version                                                    ; Verilog_2001 ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93       ; VHDL93        ;
; Top-level entity name                                              ; trafficlight ; trafficlight  ;
; State Machine Processing                                           ; Auto         ; Auto          ;
; Extract Verilog State Machines                                     ; On           ; On            ;
; Extract VHDL State Machines                                        ; On           ; On            ;
; NOT Gate Push-Back                                                 ; On           ; On            ;
; Power-Up Don't Care                                                ; On           ; On            ;
; Remove Redundant Logic Cells                                       ; Off          ; Off           ;
; Remove Duplicate Registers                                         ; On           ; On            ;
; Ignore CARRY Buffers                                               ; Off          ; Off           ;
; Ignore CASCADE Buffers                                             ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                              ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                                          ; Off          ; Off           ;
; Ignore LCELL Buffers                                               ; Off          ; Off           ;
; Ignore SOFT Buffers                                                ; On           ; On            ;
; Limit AHDL Integers to 32 Bits                                     ; Off          ; Off           ;
; Optimization Technique -- Cyclone                                  ; Balanced     ; Balanced      ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70           ; 70            ;
; Auto Carry Chains                                                  ; On           ; On            ;
; Auto Open-Drain Pins                                               ; On           ; On            ;
; Remove Duplicate Logic                                             ; On           ; On            ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off          ; Off           ;
; Perform gate-level register retiming                               ; Off          ; Off           ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On           ; On            ;
; Auto ROM Replacement                                               ; On           ; On            ;
; Auto RAM Replacement                                               ; On           ; On            ;
; Auto Shift Register Replacement                                    ; On           ; On            ;
; Auto Clock Enable Replacement                                      ; On           ; On            ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On           ; On            ;
; Auto RAM Block Balancing                                           ; On           ; On            ;
; Auto Resource Sharing                                              ; Off          ; Off           ;
; Allow Any RAM Size For Recognition                                 ; Off          ; Off           ;
; Allow Any ROM Size For Recognition                                 ; Off          ; Off           ;
; Allow Any Shift Register Size For Recognition                      ; Off          ; Off           ;
; Enable M512 Memory Blocks                                          ; On           ; On            ;
+--------------------------------------------------------------------+--------------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output              ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+
; 2:1                ; 32 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |trafficlight|fdiv1khz:inst12|cnt[23]   ;
; 2:1                ; 32 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |trafficlight|fdiv1hz:inst11|cnt[16]    ;
; 2:1                ; 2 bits    ; 2 LEs         ; 2 LEs                ; 0 LEs                  ; Yes        ; |trafficlight|dispselect:inst9|D_OUT[0] ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |trafficlight|counter05:inst1|CData0[0] ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |trafficlight|counter55:inst2|CData0[0] ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |trafficlight|counter55:inst2|CData1[0] ;
; 2:1                ; 6 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |trafficlight|control:inst14|Green2     ;
; 9:1                ; 2 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |trafficlight|dispmux:inst8|D_OUT[3]~21 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 83    ;
; Number of synthesis-generated cells                    ; 71    ;
; Number of WYSIWYG LUTs                                 ; 83    ;
; Number of synthesis-generated LUTs                     ; 66    ;
; Number of WYSIWYG registers                            ; 76    ;
; Number of synthesis-generated registers                ; 7     ;
; Number of cells with combinational logic only          ; 71    ;
; Number of cells with registers only                    ; 5     ;
; Number of cells with combinational logic and registers ; 78    ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 83    ;
; Number of registers using Synchronous Clear  ; 76    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 5     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
trafficlight
 |-- scan:inst
 |-- counter05:inst1
      |-- lpm_counter:CData0_rtl_1
           |-- cntr_0b7:auto_generated
 |-- counter55:inst2
      |-- lpm_counter:CData0_rtl_0
           |-- cntr_0b7:auto_generated
      |-- lpm_counter:CData1_rtl_2
           |-- cntr_cv7:auto_generated
 |-- countersel:inst3
 |-- datamux:inst6
 |-- dispdecoder:inst7
 |-- dispmux:inst8
 |-- dispselect:inst9
 |-- fdiv1hz:inst11
      |-- lpm_counter:cnt_rtl_4
           |-- cntr_hc7:auto_generated
 |-- fdiv1khz:inst12
      |-- lpm_counter:cnt_rtl_3
           |-- cntr_hc7:auto_generated
 |-- control:inst14


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                          ;
+------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------+
; Compilation Hierarchy Node         ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                                            ;
+------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------+
; |trafficlight                      ; 154 (0)     ; 83           ; 0           ; 19   ; 0            ; 71 (0)       ; 5 (0)             ; 78 (0)           ; 83 (0)          ; |trafficlight                                                                  ;
;    |control:inst14|                ; 6 (6)       ; 0            ; 0           ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |trafficlight|control:inst14                                                   ;
;    |counter05:inst1|               ; 7 (3)       ; 5            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 5 (1)            ; 4 (0)           ; |trafficlight|counter05:inst1                                                  ;
;       |lpm_counter:CData0_rtl_1|   ; 4 (0)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |trafficlight|counter05:inst1|lpm_counter:CData0_rtl_1                         ;
;          |cntr_0b7:auto_generated| ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |trafficlight|counter05:inst1|lpm_counter:CData0_rtl_1|cntr_0b7:auto_generated ;
;    |counter55:inst2|               ; 25 (16)     ; 9            ; 0           ; 0    ; 0            ; 16 (15)      ; 0 (0)             ; 9 (1)            ; 15 (7)          ; |trafficlight|counter55:inst2                                                  ;
;       |lpm_counter:CData0_rtl_0|   ; 4 (0)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |trafficlight|counter55:inst2|lpm_counter:CData0_rtl_0                         ;
;          |cntr_0b7:auto_generated| ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |trafficlight|counter55:inst2|lpm_counter:CData0_rtl_0|cntr_0b7:auto_generated ;
;       |lpm_counter:CData1_rtl_2|   ; 5 (0)       ; 4            ; 0           ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |trafficlight|counter55:inst2|lpm_counter:CData1_rtl_2                         ;
;          |cntr_cv7:auto_generated| ; 5 (5)       ; 4            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |trafficlight|counter55:inst2|lpm_counter:CData1_rtl_2|cntr_cv7:auto_generated ;
;    |datamux:inst6|                 ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |trafficlight|datamux:inst6                                                    ;
;    |dispdecoder:inst7|             ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |trafficlight|dispdecoder:inst7                                                ;
;    |dispmux:inst8|                 ; 16 (16)     ; 0            ; 0           ; 0    ; 0            ; 16 (16)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |trafficlight|dispmux:inst8                                                    ;
;    |dispselect:inst9|              ; 1 (1)       ; 1            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |trafficlight|dispselect:inst9                                                 ;
;    |fdiv1hz:inst11|                ; 44 (12)     ; 33           ; 0           ; 0    ; 0            ; 11 (11)      ; 1 (1)             ; 32 (0)           ; 32 (0)          ; |trafficlight|fdiv1hz:inst11                                                   ;
;       |lpm_counter:cnt_rtl_4|      ; 32 (0)      ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (0)           ; 32 (0)          ; |trafficlight|fdiv1hz:inst11|lpm_counter:cnt_rtl_4                             ;
;          |cntr_hc7:auto_generated| ; 32 (32)     ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (32)          ; 32 (32)         ; |trafficlight|fdiv1hz:inst11|lpm_counter:cnt_rtl_4|cntr_hc7:auto_generated     ;
;    |fdiv1khz:inst12|               ; 44 (12)     ; 33           ; 0           ; 0    ; 0            ; 11 (11)      ; 1 (1)             ; 32 (0)           ; 32 (0)          ; |trafficlight|fdiv1khz:inst12                                                  ;
;       |lpm_counter:cnt_rtl_3|      ; 32 (0)      ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (0)           ; 32 (0)          ; |trafficlight|fdiv1khz:inst12|lpm_counter:cnt_rtl_3                            ;
;          |cntr_hc7:auto_generated| ; 32 (32)     ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (32)          ; 32 (32)         ; |trafficlight|fdiv1khz:inst12|lpm_counter:cnt_rtl_3|cntr_hc7:auto_generated    ;
;    |scan:inst|                     ; 3 (3)       ; 2            ; 0           ; 0    ; 0            ; 1 (1)        ; 2 (2)             ; 0 (0)            ; 0 (0)           ; |trafficlight|scan:inst                                                        ;
+------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/dolphin/trafficlight/trafficlight.map.eqn.


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                   ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                                        ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; trafficlight.bdf                 ; yes             ; F:/dolphin/trafficlight/trafficlight.bdf                            ;
; control.v                        ; yes             ; F:/dolphin/trafficlight/control.v                                   ;
; scan.v                           ; yes             ; F:/dolphin/trafficlight/scan.v                                      ;
; counter55.v                      ; yes             ; F:/dolphin/trafficlight/counter55.v                                 ;
; fdiv1hz.v                        ; yes             ; F:/dolphin/trafficlight/fdiv1hz.v                                   ;
; fdiv1khz.v                       ; yes             ; F:/dolphin/trafficlight/fdiv1khz.v                                  ;
; countersel.v                     ; yes             ; F:/dolphin/trafficlight/countersel.v                                ;
; counter05.v                      ; yes             ; F:/dolphin/trafficlight/counter05.v                                 ;
; dispdecoder.v                    ; yes             ; F:/dolphin/trafficlight/dispdecoder.v                               ;
; dispmux.v                        ; yes             ; F:/dolphin/trafficlight/dispmux.v                                   ;
; datamux.v                        ; yes             ; F:/dolphin/trafficlight/datamux.v                                   ;
; dispselect.v                     ; yes             ; F:/dolphin/trafficlight/dispselect.v                                ;
; lpm_counter.tdf                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf         ;
; lpm_constant.inc                 ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_constant.inc        ;
; lpm_decode.inc                   ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_decode.inc          ;
; lpm_add_sub.inc                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_add_sub.inc         ;
; cmpconst.inc                     ; yes             ; c:/altera/quartus42/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; c:/altera/quartus42/libraries/megafunctions/dffeea.inc              ;
; alt_synch_counter.inc            ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_synch_counter.inc   ;
; alt_synch_counter_f.inc          ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc            ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.inc   ;
; alt_counter_stratix.inc          ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal42.inc                    ; yes             ; c:/altera/quartus42/libraries/megafunctions/aglobal42.inc           ;
; db/cntr_0b7.tdf                  ; yes             ; F:/dolphin/trafficlight/db/cntr_0b7.tdf                             ;
; db/cntr_cv7.tdf                  ; yes             ; F:/dolphin/trafficlight/db/cntr_cv7.tdf                             ;
; db/cntr_hc7.tdf                  ; yes             ; F:/dolphin/trafficlight/db/cntr_hc7.tdf                             ;
+----------------------------------+-----------------+---------------------------------------------------------------------+


+-------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                 ;
+-----------------------------------+-------------------------+
; Resource                          ; Usage                   ;
+-----------------------------------+-------------------------+
; Logic cells                       ; 154                     ;
; Total combinational functions     ; 149                     ;
; Total 4-input functions           ; 51                      ;
; Total 3-input functions           ; 8                       ;
; Total 2-input functions           ; 7                       ;
; Total 1-input functions           ; 83                      ;
; Total 0-input functions           ; 0                       ;
; Combinational cells for routing   ; 0                       ;
; Total registers                   ; 83                      ;
; Total logic cells in carry chains ; 83                      ;
; I/O pins                          ; 19                      ;
; Maximum fan-out node              ; fdiv1khz:inst12|clk_out ;
; Maximum fan-out                   ; 34                      ;
; Total fan-out                     ; 586                     ;
; Average fan-out                   ; 3.39                    ;
+-----------------------------------+-------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Sun May 28 11:09:56 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off trafficlight -c trafficlight
Info: Found 1 design units, including 1 entities, in source file trafficlight.bdf
    Info: Found entity 1: trafficlight
Info: Found 0 design units, including 0 entities, in source file trafficlight.v
Info: Using design file control.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: control
Info: Using design file scan.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: scan
Info: Using design file counter55.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: counter55
Warning: Verilog HDL assignment warning at counter55.v(37): truncated value with size 5 to match size of target (4)
Warning: Verilog HDL assignment warning at counter55.v(42): truncated value with size 5 to match size of target (4)
Warning: Verilog HDL assignment warning at counter55.v(63): truncated value with size 8 to match size of target (4)
Info: Using design file fdiv1hz.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: fdiv1hz
Info: Using design file fdiv1khz.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: fdiv1khz
Info: Using design file countersel.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: countersel
Info: Using design file counter05.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: counter05
Warning: Verilog HDL assignment warning at counter05.v(32): truncated value with size 5 to match size of target (4)
Info: Using design file dispdecoder.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: dispdecoder
Info: Using design file dispmux.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: dispmux
Info: Using design file datamux.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: datamux
Info: Using design file dispselect.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: dispselect
Warning: Reduced register "counter05:inst1|CData1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "counter05:inst1|CData1[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "counter05:inst1|CData1[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "counter05:inst1|CData1[0]" with stuck data_in port to stuck value GND
Info: Inferred 5 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter55:inst2|CData0[0]~20"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter05:inst1|CData0[0]~15"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter55:inst2|CData1[0]~25"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: "fdiv1khz:inst12|cnt[0]~64"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: "fdiv1hz:inst11|cnt[0]~64"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_0b7.tdf
    Info: Found entity 1: cntr_0b7
Info: Found 1 design units, including 1 entities, in source file db/cntr_cv7.tdf
    Info: Found entity 1: cntr_cv7
Info: Found 1 design units, including 1 entities, in source file db/cntr_hc7.tdf
    Info: Found entity 1: cntr_hc7
Info: Duplicate registers merged to single register
    Info: Duplicate register "dispselect:inst9|D_OUT[1]" merged to single register "dispselect:inst9|D_OUT[0]", power-up level changed
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "SEG_Data[0]" stuck at GND
Info: Implemented 173 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 16 output pins
    Info: Implemented 154 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Processing ended: Sun May 28 11:10:03 2006
    Info: Elapsed time: 00:00:08


