{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 02 16:41:44 2006 " "Info: Processing started: Wed Aug 02 16:41:44 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off main -c main " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off main -c main" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_FOUND_COMB_LATCHES" "" "Warning: Timing Analysis found one or more latches implemented as combinational loops" { { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[3\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[3\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[4\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[4\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[5\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[5\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[6\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[6\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[0\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[0\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[1\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[1\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[2\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[2\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[11\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[11\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[12\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[12\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[13\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[13\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[14\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[14\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[7\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[7\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[8\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[8\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[9\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[9\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[10\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[10\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[6\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[6\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[5\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[5\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[4\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[4\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[3\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[3\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[2\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[2\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[1\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[1\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[0\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[0\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[10\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[10\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[9\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[9\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[8\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[8\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[7\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[7\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[14\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[14\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[13\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[13\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[12\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[12\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[11\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[11\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Reset " "Info: Assuming node \"Reset\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 112 -200 -32 128 "Reset" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Reset" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "Clock_8MHz " "Info: Assuming node \"Clock_8MHz\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 248 -200 -32 264 "Clock_8MHz" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Clock_8MHz" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "71 " "Warning: Found 71 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~23 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~23\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~23" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[11\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[11\]\" as buffer" {  } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[11\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~25 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~25\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~25" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[12\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[12\]\" as buffer" {  } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[12\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~27 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~27\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~27" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[13\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[13\]\" as buffer" {  } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[13\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~425 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~425\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~425" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[14\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[14\]\" as buffer" {  } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[14\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~15 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~15\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~15" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[7\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[7\]\" as buffer" {  } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[7\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~17 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~17\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~17" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[8\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[8\]\" as buffer" {  } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[8\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~19 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~19\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~19" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[9\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[9\]\" as buffer" {  } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[9\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~21 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~21\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~21" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[10\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[10\]\" as buffer" {  } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[10\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[10\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[10\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[10\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[9\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[9\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[9\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[8\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[8\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[8\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[7\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[7\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[7\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~1 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~1\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~1" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[15\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[15\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[15\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[0\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[0\]\" as buffer" {  } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[0\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~3 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~3\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~3" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[14\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[14\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[14\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[1\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[1\]\" as buffer" {  } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[1\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~424 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~424\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~424" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~5 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~5\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~5" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[13\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[13\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[13\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[2\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[2\]\" as buffer" {  } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[2\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~7 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~7\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~7" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[12\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[12\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[12\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[3\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[3\]\" as buffer" {  } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[3\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~423 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~423\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~423" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~9 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~9\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~9" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[11\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[11\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[11\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[4\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[4\]\" as buffer" {  } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[4\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~11 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~11\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~11" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[10\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[10\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[10\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[5\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[5\]\" as buffer" {  } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[5\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~422 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~422\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~422" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~13 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~13\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~13" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[8\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[8\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[8\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[9\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[9\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[9\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] " "Info: Detected ripple clock \"fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "second_pulse_latch:inst3\|second_pulse_out\[6\] " "Info: Detected ripple clock \"second_pulse_latch:inst3\|second_pulse_out\[6\]\" as buffer" {  } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "second_pulse_latch:inst3\|second_pulse_out\[6\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~421 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~421\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~421" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[7\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[7\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[7\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[6\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[6\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[6\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~420 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~420\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~420" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[5\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[5\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[5\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[4\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[4\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[4\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~419 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~419\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~419" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[2\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[2\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[2\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1~418 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1~418\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1~418" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[1\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[1\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[0\] " "Info: Detected ripple clock \"counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[0\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[0\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] " "Info: Detected ripple clock \"fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]\" as buffer" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[14\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[14\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[14\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[13\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[13\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[13\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[12\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[12\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[12\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[11\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[11\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[11\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[2\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[2\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[2\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[1\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[1\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[1\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[0\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[0\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[0\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[6\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[6\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[6\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[5\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[5\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[5\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[4\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[4\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[4\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_1\[3\] " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_1\[3\]\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_1\[3\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "pulse_sum:inst4\|pulse_out~16 " "Info: Detected gated clock \"pulse_sum:inst4\|pulse_out~16\" as buffer" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "pulse_sum:inst4\|pulse_out~16" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Reset register sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] register sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[23\] 87.72 MHz 11.4 ns Internal " "Info: Clock \"Reset\" has Internal fmax of 87.72 MHz between source register \"sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]\" and destination register \"sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[23\]\" (period= 11.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.400 ns + Longest register register " "Info: + Longest register to register delay is 6.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC4_B3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B3; Fanout = 4; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.700 ns) 1.300 ns sum_control:inst5\|reduce_nor~288 2 COMB LC5_B2 1 " "Info: 2: + IC(0.600 ns) + CELL(0.700 ns) = 1.300 ns; Loc. = LC5_B2; Fanout = 1; COMB Node = 'sum_control:inst5\|reduce_nor~288'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.300 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] sum_control:inst5|reduce_nor~288 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.300 ns sum_control:inst5\|reduce_nor~297 3 COMB LC6_B2 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 2.300 ns; Loc. = LC6_B2; Fanout = 1; COMB Node = 'sum_control:inst5\|reduce_nor~297'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.000 ns" { sum_control:inst5|reduce_nor~288 sum_control:inst5|reduce_nor~297 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.100 ns) 4.000 ns sum_control:inst5\|reduce_nor~267 4 COMB LC4_B6 2 " "Info: 4: + IC(0.600 ns) + CELL(1.100 ns) = 4.000 ns; Loc. = LC4_B6; Fanout = 2; COMB Node = 'sum_control:inst5\|reduce_nor~267'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.700 ns" { sum_control:inst5|reduce_nor~297 sum_control:inst5|reduce_nor~267 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.000 ns) 5.100 ns rtl~0 5 COMB LC1_B6 54 " "Info: 5: + IC(0.100 ns) + CELL(1.000 ns) = 5.100 ns; Loc. = LC1_B6; Fanout = 54; COMB Node = 'rtl~0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.100 ns" { sum_control:inst5|reduce_nor~267 rtl~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.700 ns) 6.400 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[23\] 6 REG LC8_B7 3 " "Info: 6: + IC(0.600 ns) + CELL(0.700 ns) = 6.400 ns; Loc. = LC8_B7; Fanout = 3; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[23\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.300 ns" { rtl~0 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 70.31 % " "Info: Total cell delay = 4.500 ns ( 70.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns 29.69 % " "Info: Total interconnect delay = 1.900 ns ( 29.69 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "6.400 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] sum_control:inst5|reduce_nor~288 sum_control:inst5|reduce_nor~297 sum_control:inst5|reduce_nor~267 rtl~0 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.400 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] sum_control:inst5|reduce_nor~288 sum_control:inst5|reduce_nor~297 sum_control:inst5|reduce_nor~267 rtl~0 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } { 0.000ns 0.600ns 0.000ns 0.600ns 0.100ns 0.600ns } { 0.000ns 0.700ns 1.000ns 1.100ns 1.000ns 0.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.300 ns - Smallest " "Info: - Smallest clock skew is -4.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Reset destination 4.500 ns + Shortest register " "Info: + Shortest clock path from clock \"Reset\" to destination register is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Reset 1 CLK PIN_89 51 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 51; CLK Node = 'Reset'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { Reset } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 112 -200 -32 128 "Reset" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.000 ns) 2.400 ns pulse_sum:inst4\|pulse_out~16 2 COMB LC1_A10 28 " "Info: 2: + IC(0.100 ns) + CELL(1.000 ns) = 2.400 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4\|pulse_out~16'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.100 ns" { Reset pulse_sum:inst4|pulse_out~16 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 4.500 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[23\] 3 REG LC8_B7 3 " "Info: 3: + IC(2.100 ns) + CELL(0.000 ns) = 4.500 ns; Loc. = LC8_B7; Fanout = 3; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[23\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "2.100 ns" { pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.300 ns 51.11 % " "Info: Total cell delay = 2.300 ns ( 51.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns 48.89 % " "Info: Total interconnect delay = 2.200 ns ( 48.89 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "4.500 ns" { Reset pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.500 ns" { Reset Reset~out pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } { 0.000ns 0.000ns 0.100ns 2.100ns } { 0.000ns 1.300ns 1.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Reset source 8.800 ns - Longest register " "Info: - Longest clock path from clock \"Reset\" to source register is 8.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Reset 1 CLK PIN_89 51 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 51; CLK Node = 'Reset'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { Reset } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 112 -200 -32 128 "Reset" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.300 ns pulse_sum:inst4\|pulse_1\[5\] 2 COMB LOOP LC8_A9 2 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 2.300 ns; Loc. = LC8_A9; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4\|pulse_1\[5\]'" { { "Info" "ITDB_PART_OF_SCC" "pulse_sum:inst4\|pulse_1\[5\] LC8_A9 " "Info: Loc. = LC8_A9; Node \"pulse_sum:inst4\|pulse_1\[5\]\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[5] } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[5] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.000 ns" { Reset pulse_sum:inst4|pulse_1[5] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(1.000 ns) 4.000 ns pulse_sum:inst4\|pulse_out~126 3 COMB LC3_A1 1 " "Info: 3: + IC(0.700 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC3_A1; Fanout = 1; COMB Node = 'pulse_sum:inst4\|pulse_out~126'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.700 ns" { pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.800 ns) 5.800 ns pulse_sum:inst4\|pulse_out~127 4 COMB LC2_A10 2 " "Info: 4: + IC(1.000 ns) + CELL(0.800 ns) = 5.800 ns; Loc. = LC2_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_out~127'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.800 ns" { pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 6.700 ns pulse_sum:inst4\|pulse_out~16 5 COMB LC1_A10 28 " "Info: 5: + IC(0.100 ns) + CELL(0.800 ns) = 6.700 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4\|pulse_out~16'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 8.800 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 6 REG LC4_B3 4 " "Info: 6: + IC(2.100 ns) + CELL(0.000 ns) = 8.800 ns; Loc. = LC4_B3; Fanout = 4; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "2.100 ns" { pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.900 ns 55.68 % " "Info: Total cell delay = 4.900 ns ( 55.68 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns 44.32 % " "Info: Total interconnect delay = 3.900 ns ( 44.32 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "8.800 ns" { Reset pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.800 ns" { Reset Reset~out pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.000ns 0.700ns 1.000ns 0.100ns 2.100ns } { 0.000ns 1.300ns 1.000ns 1.000ns 0.800ns 0.800ns 0.000ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "4.500 ns" { Reset pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.500 ns" { Reset Reset~out pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } { 0.000ns 0.000ns 0.100ns 2.100ns } { 0.000ns 1.300ns 1.000ns 0.000ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "8.800 ns" { Reset pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.800 ns" { Reset Reset~out pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.000ns 0.700ns 1.000ns 0.100ns 2.100ns } { 0.000ns 1.300ns 1.000ns 1.000ns 0.800ns 0.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "6.400 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] sum_control:inst5|reduce_nor~288 sum_control:inst5|reduce_nor~297 sum_control:inst5|reduce_nor~267 rtl~0 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.400 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] sum_control:inst5|reduce_nor~288 sum_control:inst5|reduce_nor~297 sum_control:inst5|reduce_nor~267 rtl~0 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } { 0.000ns 0.600ns 0.000ns 0.600ns 0.100ns 0.600ns } { 0.000ns 0.700ns 1.000ns 1.100ns 1.000ns 0.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "4.500 ns" { Reset pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.500 ns" { Reset Reset~out pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } { 0.000ns 0.000ns 0.100ns 2.100ns } { 0.000ns 1.300ns 1.000ns 0.000ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "8.800 ns" { Reset pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.800 ns" { Reset Reset~out pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.000ns 0.700ns 1.000ns 0.100ns 2.100ns } { 0.000ns 1.300ns 1.000ns 1.000ns 0.800ns 0.800ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clock_8MHz register sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] register sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[23\] 62.5 MHz 16.0 ns Internal " "Info: Clock \"Clock_8MHz\" has Internal fmax of 62.5 MHz between source register \"sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]\" and destination register \"sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[23\]\" (period= 16.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.400 ns + Longest register register " "Info: + Longest register to register delay is 6.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC4_B3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B3; Fanout = 4; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.700 ns) 1.300 ns sum_control:inst5\|reduce_nor~288 2 COMB LC5_B2 1 " "Info: 2: + IC(0.600 ns) + CELL(0.700 ns) = 1.300 ns; Loc. = LC5_B2; Fanout = 1; COMB Node = 'sum_control:inst5\|reduce_nor~288'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.300 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] sum_control:inst5|reduce_nor~288 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.300 ns sum_control:inst5\|reduce_nor~297 3 COMB LC6_B2 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 2.300 ns; Loc. = LC6_B2; Fanout = 1; COMB Node = 'sum_control:inst5\|reduce_nor~297'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.000 ns" { sum_control:inst5|reduce_nor~288 sum_control:inst5|reduce_nor~297 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.100 ns) 4.000 ns sum_control:inst5\|reduce_nor~267 4 COMB LC4_B6 2 " "Info: 4: + IC(0.600 ns) + CELL(1.100 ns) = 4.000 ns; Loc. = LC4_B6; Fanout = 2; COMB Node = 'sum_control:inst5\|reduce_nor~267'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.700 ns" { sum_control:inst5|reduce_nor~297 sum_control:inst5|reduce_nor~267 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.000 ns) 5.100 ns rtl~0 5 COMB LC1_B6 54 " "Info: 5: + IC(0.100 ns) + CELL(1.000 ns) = 5.100 ns; Loc. = LC1_B6; Fanout = 54; COMB Node = 'rtl~0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.100 ns" { sum_control:inst5|reduce_nor~267 rtl~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.700 ns) 6.400 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[23\] 6 REG LC8_B7 3 " "Info: 6: + IC(0.600 ns) + CELL(0.700 ns) = 6.400 ns; Loc. = LC8_B7; Fanout = 3; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[23\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.300 ns" { rtl~0 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 70.31 % " "Info: Total cell delay = 4.500 ns ( 70.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns 29.69 % " "Info: Total interconnect delay = 1.900 ns ( 29.69 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "6.400 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] sum_control:inst5|reduce_nor~288 sum_control:inst5|reduce_nor~297 sum_control:inst5|reduce_nor~267 rtl~0 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.400 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] sum_control:inst5|reduce_nor~288 sum_control:inst5|reduce_nor~297 sum_control:inst5|reduce_nor~267 rtl~0 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } { 0.000ns 0.600ns 0.000ns 0.600ns 0.100ns 0.600ns } { 0.000ns 0.700ns 1.000ns 1.100ns 1.000ns 0.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-8.900 ns - Smallest " "Info: - Smallest clock skew is -8.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_8MHz destination 9.900 ns + Shortest register " "Info: + Shortest clock path from clock \"Clock_8MHz\" to destination register is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clock_8MHz 1 CLK PIN_39 26 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 26; CLK Node = 'Clock_8MHz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { Clock_8MHz } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 248 -200 -32 264 "Clock_8MHz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.300 ns) 1.800 ns fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] 2 REG LC3_C7 36 " "Info: 2: + IC(0.200 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC3_C7; Fanout = 36; REG Node = 'fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.500 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.800 ns) 3.500 ns pulse_sum:inst4\|pulse_1~425 3 COMB LC4_A2 2 " "Info: 3: + IC(0.900 ns) + CELL(0.800 ns) = 3.500 ns; Loc. = LC4_A2; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_1~425'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.700 ns" { fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~425 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 5.300 ns pulse_sum:inst4\|pulse_1\[14\] 4 COMB LOOP LC6_A12 2 " "Info: 4: + IC(0.000 ns) + CELL(1.800 ns) = 5.300 ns; Loc. = LC6_A12; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4\|pulse_1\[14\]'" { { "Info" "ITDB_PART_OF_SCC" "pulse_sum:inst4\|pulse_1\[14\] LC6_A12 " "Info: Loc. = LC6_A12; Node \"pulse_sum:inst4\|pulse_1\[14\]\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[14] } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[14] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.800 ns" { pulse_sum:inst4|pulse_1~425 pulse_sum:inst4|pulse_1[14] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 6.200 ns pulse_sum:inst4\|pulse_out~133 5 COMB LC5_A12 2 " "Info: 5: + IC(0.100 ns) + CELL(0.800 ns) = 6.200 ns; Loc. = LC5_A12; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_out~133'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_1[14] pulse_sum:inst4|pulse_out~133 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.000 ns) 7.800 ns pulse_sum:inst4\|pulse_out~16 6 COMB LC1_A10 28 " "Info: 6: + IC(0.600 ns) + CELL(1.000 ns) = 7.800 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4\|pulse_out~16'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.600 ns" { pulse_sum:inst4|pulse_out~133 pulse_sum:inst4|pulse_out~16 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 9.900 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[23\] 7 REG LC8_B7 3 " "Info: 7: + IC(2.100 ns) + CELL(0.000 ns) = 9.900 ns; Loc. = LC8_B7; Fanout = 3; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[23\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "2.100 ns" { pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 60.61 % " "Info: Total cell delay = 6.000 ns ( 60.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns 39.39 % " "Info: Total interconnect delay = 3.900 ns ( 39.39 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "9.900 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~425 pulse_sum:inst4|pulse_1[14] pulse_sum:inst4|pulse_out~133 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "9.900 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~425 pulse_sum:inst4|pulse_1[14] pulse_sum:inst4|pulse_out~133 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } { 0.000ns 0.000ns 0.200ns 0.900ns 0.000ns 0.100ns 0.600ns 2.100ns } { 0.000ns 1.300ns 0.300ns 0.800ns 1.800ns 0.800ns 1.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_8MHz source 18.800 ns - Longest register " "Info: - Longest clock path from clock \"Clock_8MHz\" to source register is 18.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clock_8MHz 1 CLK PIN_39 26 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 26; CLK Node = 'Clock_8MHz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { Clock_8MHz } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 248 -200 -32 264 "Clock_8MHz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.300 ns) 1.800 ns fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] 2 REG LC3_C7 36 " "Info: 2: + IC(0.200 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC3_C7; Fanout = 36; REG Node = 'fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.500 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.300 ns) 3.000 ns counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[1\] 3 REG LC2_A3 6 " "Info: 3: + IC(0.900 ns) + CELL(0.300 ns) = 3.000 ns; Loc. = LC2_A3; Fanout = 6; REG Node = 'counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.200 ns" { fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(1.000 ns) 4.500 ns pulse_sum:inst4\|pulse_1~418 4 COMB LC8_A2 3 " "Info: 4: + IC(0.500 ns) + CELL(1.000 ns) = 4.500 ns; Loc. = LC8_A2; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~418'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.500 ns" { counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.800 ns) 6.300 ns pulse_sum:inst4\|pulse_1~419 5 COMB LC3_A11 3 " "Info: 5: + IC(1.000 ns) + CELL(0.800 ns) = 6.300 ns; Loc. = LC3_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~419'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.800 ns" { pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 7.200 ns pulse_sum:inst4\|pulse_1~420 6 COMB LC4_A11 3 " "Info: 6: + IC(0.100 ns) + CELL(0.800 ns) = 7.200 ns; Loc. = LC4_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~420'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 8.100 ns pulse_sum:inst4\|pulse_1~421 7 COMB LC8_A11 3 " "Info: 7: + IC(0.100 ns) + CELL(0.800 ns) = 8.100 ns; Loc. = LC8_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~421'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.800 ns) 9.500 ns pulse_sum:inst4\|pulse_1~422 8 COMB LC3_A9 3 " "Info: 8: + IC(0.600 ns) + CELL(0.800 ns) = 9.500 ns; Loc. = LC3_A9; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~422'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.400 ns" { pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 10.400 ns pulse_sum:inst4\|pulse_1~423 9 COMB LC1_A9 3 " "Info: 9: + IC(0.100 ns) + CELL(0.800 ns) = 10.400 ns; Loc. = LC1_A9; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~423'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(0.800 ns) 11.900 ns pulse_sum:inst4\|pulse_1~424 10 COMB LC4_A1 2 " "Info: 10: + IC(0.700 ns) + CELL(0.800 ns) = 11.900 ns; Loc. = LC4_A1; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_1~424'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.500 ns" { pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.800 ns) 13.700 ns pulse_sum:inst4\|pulse_1~1 11 COMB LC7_A10 2 " "Info: 11: + IC(1.000 ns) + CELL(0.800 ns) = 13.700 ns; Loc. = LC7_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_1~1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.800 ns" { pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 14.600 ns pulse_sum:inst4\|pulse_1\[0\] 12 COMB LOOP LC8_A10 2 " "Info: 12: + IC(0.000 ns) + CELL(0.900 ns) = 14.600 ns; Loc. = LC8_A10; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4\|pulse_1\[0\]'" { { "Info" "ITDB_PART_OF_SCC" "pulse_sum:inst4\|pulse_1\[0\] LC8_A10 " "Info: Loc. = LC8_A10; Node \"pulse_sum:inst4\|pulse_1\[0\]\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[0] } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[0] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.100 ns) 15.800 ns pulse_sum:inst4\|pulse_out~127 13 COMB LC2_A10 2 " "Info: 13: + IC(0.100 ns) + CELL(1.100 ns) = 15.800 ns; Loc. = LC2_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_out~127'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.200 ns" { pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 16.700 ns pulse_sum:inst4\|pulse_out~16 14 COMB LC1_A10 28 " "Info: 14: + IC(0.100 ns) + CELL(0.800 ns) = 16.700 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4\|pulse_out~16'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 18.800 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 15 REG LC4_B3 4 " "Info: 15: + IC(2.100 ns) + CELL(0.000 ns) = 18.800 ns; Loc. = LC4_B3; Fanout = 4; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "2.100 ns" { pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.300 ns 60.11 % " "Info: Total cell delay = 11.300 ns ( 60.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.500 ns 39.89 % " "Info: Total interconnect delay = 7.500 ns ( 39.89 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "18.800 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "18.800 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.200ns 0.900ns 0.500ns 1.000ns 0.100ns 0.100ns 0.600ns 0.100ns 0.700ns 1.000ns 0.000ns 0.100ns 0.100ns 2.100ns } { 0.000ns 1.300ns 0.300ns 0.300ns 1.000ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.900ns 1.100ns 0.800ns 0.000ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "9.900 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~425 pulse_sum:inst4|pulse_1[14] pulse_sum:inst4|pulse_out~133 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "9.900 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~425 pulse_sum:inst4|pulse_1[14] pulse_sum:inst4|pulse_out~133 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } { 0.000ns 0.000ns 0.200ns 0.900ns 0.000ns 0.100ns 0.600ns 2.100ns } { 0.000ns 1.300ns 0.300ns 0.800ns 1.800ns 0.800ns 1.000ns 0.000ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "18.800 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "18.800 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.200ns 0.900ns 0.500ns 1.000ns 0.100ns 0.100ns 0.600ns 0.100ns 0.700ns 1.000ns 0.000ns 0.100ns 0.100ns 2.100ns } { 0.000ns 1.300ns 0.300ns 0.300ns 1.000ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.900ns 1.100ns 0.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "6.400 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] sum_control:inst5|reduce_nor~288 sum_control:inst5|reduce_nor~297 sum_control:inst5|reduce_nor~267 rtl~0 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.400 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] sum_control:inst5|reduce_nor~288 sum_control:inst5|reduce_nor~297 sum_control:inst5|reduce_nor~267 rtl~0 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } { 0.000ns 0.600ns 0.000ns 0.600ns 0.100ns 0.600ns } { 0.000ns 0.700ns 1.000ns 1.100ns 1.000ns 0.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "9.900 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~425 pulse_sum:inst4|pulse_1[14] pulse_sum:inst4|pulse_out~133 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "9.900 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~425 pulse_sum:inst4|pulse_1[14] pulse_sum:inst4|pulse_out~133 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] } { 0.000ns 0.000ns 0.200ns 0.900ns 0.000ns 0.100ns 0.600ns 2.100ns } { 0.000ns 1.300ns 0.300ns 0.800ns 1.800ns 0.800ns 1.000ns 0.000ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "18.800 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "18.800 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.200ns 0.900ns 0.500ns 1.000ns 0.100ns 0.100ns 0.600ns 0.100ns 0.700ns 1.000ns 0.000ns 0.100ns 0.100ns 2.100ns } { 0.000ns 1.300ns 0.300ns 0.300ns 1.000ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.900ns 1.100ns 0.800ns 0.000ns } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "Reset 201 " "Warning: Circuit may not operate. Detected 201 non-operational path(s) clocked by clock \"Reset\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[8\] Reset 3.1 ns " "Info: Found hold time violation between source  pin or register \"sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" and destination pin or register \"sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[8\]\" for clock \"Reset\" (Hold time is 3.1 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.300 ns + Largest " "Info: + Largest clock skew is 4.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Reset destination 8.800 ns + Longest register " "Info: + Longest clock path from clock \"Reset\" to destination register is 8.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Reset 1 CLK PIN_89 51 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 51; CLK Node = 'Reset'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { Reset } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 112 -200 -32 128 "Reset" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.300 ns pulse_sum:inst4\|pulse_1\[5\] 2 COMB LOOP LC8_A9 2 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 2.300 ns; Loc. = LC8_A9; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4\|pulse_1\[5\]'" { { "Info" "ITDB_PART_OF_SCC" "pulse_sum:inst4\|pulse_1\[5\] LC8_A9 " "Info: Loc. = LC8_A9; Node \"pulse_sum:inst4\|pulse_1\[5\]\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[5] } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[5] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.000 ns" { Reset pulse_sum:inst4|pulse_1[5] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(1.000 ns) 4.000 ns pulse_sum:inst4\|pulse_out~126 3 COMB LC3_A1 1 " "Info: 3: + IC(0.700 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC3_A1; Fanout = 1; COMB Node = 'pulse_sum:inst4\|pulse_out~126'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.700 ns" { pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.800 ns) 5.800 ns pulse_sum:inst4\|pulse_out~127 4 COMB LC2_A10 2 " "Info: 4: + IC(1.000 ns) + CELL(0.800 ns) = 5.800 ns; Loc. = LC2_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_out~127'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.800 ns" { pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 6.700 ns pulse_sum:inst4\|pulse_out~16 5 COMB LC1_A10 28 " "Info: 5: + IC(0.100 ns) + CELL(0.800 ns) = 6.700 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4\|pulse_out~16'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 8.800 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[8\] 6 REG LC1_B5 5 " "Info: 6: + IC(2.100 ns) + CELL(0.000 ns) = 8.800 ns; Loc. = LC1_B5; Fanout = 5; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[8\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "2.100 ns" { pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.900 ns 55.68 % " "Info: Total cell delay = 4.900 ns ( 55.68 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns 44.32 % " "Info: Total interconnect delay = 3.900 ns ( 44.32 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "8.800 ns" { Reset pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.800 ns" { Reset Reset~out pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8] } { 0.0ns 0.0ns 0.0ns 0.7ns 1.0ns 0.1ns 2.1ns } { 0.0ns 1.3ns 1.0ns 1.0ns 0.8ns 0.8ns 0.0ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Reset source 4.500 ns - Shortest register " "Info: - Shortest clock path from clock \"Reset\" to source register is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Reset 1 CLK PIN_89 51 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 51; CLK Node = 'Reset'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { Reset } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 112 -200 -32 128 "Reset" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.000 ns) 2.400 ns pulse_sum:inst4\|pulse_out~16 2 COMB LC1_A10 28 " "Info: 2: + IC(0.100 ns) + CELL(1.000 ns) = 2.400 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4\|pulse_out~16'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.100 ns" { Reset pulse_sum:inst4|pulse_out~16 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 4.500 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 3 REG LC1_B3 4 " "Info: 3: + IC(2.100 ns) + CELL(0.000 ns) = 4.500 ns; Loc. = LC1_B3; Fanout = 4; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "2.100 ns" { pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.300 ns 51.11 % " "Info: Total cell delay = 2.300 ns ( 51.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns 48.89 % " "Info: Total interconnect delay = 2.200 ns ( 48.89 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "4.500 ns" { Reset pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.500 ns" { Reset Reset~out pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.0ns 0.0ns 0.1ns 2.1ns } { 0.0ns 1.3ns 1.0ns 0.0ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "8.800 ns" { Reset pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.800 ns" { Reset Reset~out pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8] } { 0.0ns 0.0ns 0.0ns 0.7ns 1.0ns 0.1ns 2.1ns } { 0.0ns 1.3ns 1.0ns 1.0ns 0.8ns 0.8ns 0.0ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "4.500 ns" { Reset pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.500 ns" { Reset Reset~out pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.0ns 0.0ns 0.1ns 2.1ns } { 0.0ns 1.3ns 1.0ns 0.0ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns - " "Info: - Micro clock to output delay of source is 0.300 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.600 ns - Shortest register register " "Info: - Shortest register to register delay is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC1_B3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B3; Fanout = 4; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 0.100 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[0\]~COUT 2 COMB LC1_B3 2 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 0.100 ns; Loc. = LC1_B3; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[0\]~COUT'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 317 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 0.200 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[1\]~COUT 3 COMB LC2_B3 2 " "Info: 3: + IC(0.000 ns) + CELL(0.100 ns) = 0.200 ns; Loc. = LC2_B3; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[1\]~COUT'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 317 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 0.300 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[2\]~COUT 4 COMB LC3_B3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.100 ns) = 0.300 ns; Loc. = LC3_B3; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[2\]~COUT'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 317 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 0.400 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~COUT 5 COMB LC4_B3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.100 ns) = 0.400 ns; Loc. = LC4_B3; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~COUT'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 317 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 0.500 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[4\]~COUT 6 COMB LC5_B3 2 " "Info: 6: + IC(0.000 ns) + CELL(0.100 ns) = 0.500 ns; Loc. = LC5_B3; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[4\]~COUT'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 317 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 0.600 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[5\]~COUT 7 COMB LC6_B3 2 " "Info: 7: + IC(0.000 ns) + CELL(0.100 ns) = 0.600 ns; Loc. = LC6_B3; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[5\]~COUT'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 317 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 0.700 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[6\]~COUT 8 COMB LC7_B3 2 " "Info: 8: + IC(0.000 ns) + CELL(0.100 ns) = 0.700 ns; Loc. = LC7_B3; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[6\]~COUT'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 317 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 0.800 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[7\]~COUT 9 COMB LC8_B3 3 " "Info: 9: + IC(0.000 ns) + CELL(0.100 ns) = 0.800 ns; Loc. = LC8_B3; Fanout = 3; COMB Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[7\]~COUT'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 317 15 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.500 ns) 1.600 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[8\] 10 REG LC1_B5 5 " "Info: 10: + IC(0.300 ns) + CELL(0.500 ns) = 1.600 ns; Loc. = LC1_B5; Fanout = 5; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[8\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.800 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 81.25 % " "Info: Total cell delay = 1.300 ns ( 81.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns 18.75 % " "Info: Total interconnect delay = 0.300 ns ( 18.75 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.600 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.600 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8] } { 0.0ns 0.0ns 0.0ns 0.0ns 0.0ns 0.0ns 0.0ns 0.0ns 0.0ns 0.3ns } { 0.0ns 0.1ns 0.1ns 0.1ns 0.1ns 0.1ns 0.1ns 0.1ns 0.1ns 0.5ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.700 ns + " "Info: + Micro hold delay of destination is 0.700 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "8.800 ns" { Reset pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.800 ns" { Reset Reset~out pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8] } { 0.0ns 0.0ns 0.0ns 0.7ns 1.0ns 0.1ns 2.1ns } { 0.0ns 1.3ns 1.0ns 1.0ns 0.8ns 0.8ns 0.0ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "4.500 ns" { Reset pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.500 ns" { Reset Reset~out pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.0ns 0.0ns 0.1ns 2.1ns } { 0.0ns 1.3ns 1.0ns 0.0ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.600 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.600 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8] } { 0.0ns 0.0ns 0.0ns 0.0ns 0.0ns 0.0ns 0.0ns 0.0ns 0.0ns 0.3ns } { 0.0ns 0.1ns 0.1ns 0.1ns 0.1ns 0.1ns 0.1ns 0.1ns 0.1ns 0.5ns } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "Clock_8MHz 201 " "Warning: Circuit may not operate. Detected 201 non-operational path(s) clocked by clock \"Clock_8MHz\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\] sum_control:inst5\|out_control Clock_8MHz 4.2 ns " "Info: Found hold time violation between source  pin or register \"sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\]\" and destination pin or register \"sum_control:inst5\|out_control\" for clock \"Clock_8MHz\" (Hold time is 4.2 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "8.900 ns + Largest " "Info: + Largest clock skew is 8.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_8MHz destination 18.800 ns + Longest register " "Info: + Longest clock path from clock \"Clock_8MHz\" to destination register is 18.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clock_8MHz 1 CLK PIN_39 26 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 26; CLK Node = 'Clock_8MHz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { Clock_8MHz } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 248 -200 -32 264 "Clock_8MHz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.300 ns) 1.800 ns fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] 2 REG LC3_C7 36 " "Info: 2: + IC(0.200 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC3_C7; Fanout = 36; REG Node = 'fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.500 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.300 ns) 3.000 ns counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[1\] 3 REG LC2_A3 6 " "Info: 3: + IC(0.900 ns) + CELL(0.300 ns) = 3.000 ns; Loc. = LC2_A3; Fanout = 6; REG Node = 'counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.200 ns" { fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(1.000 ns) 4.500 ns pulse_sum:inst4\|pulse_1~418 4 COMB LC8_A2 3 " "Info: 4: + IC(0.500 ns) + CELL(1.000 ns) = 4.500 ns; Loc. = LC8_A2; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~418'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.500 ns" { counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.800 ns) 6.300 ns pulse_sum:inst4\|pulse_1~419 5 COMB LC3_A11 3 " "Info: 5: + IC(1.000 ns) + CELL(0.800 ns) = 6.300 ns; Loc. = LC3_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~419'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.800 ns" { pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 7.200 ns pulse_sum:inst4\|pulse_1~420 6 COMB LC4_A11 3 " "Info: 6: + IC(0.100 ns) + CELL(0.800 ns) = 7.200 ns; Loc. = LC4_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~420'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 8.100 ns pulse_sum:inst4\|pulse_1~421 7 COMB LC8_A11 3 " "Info: 7: + IC(0.100 ns) + CELL(0.800 ns) = 8.100 ns; Loc. = LC8_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~421'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.800 ns) 9.500 ns pulse_sum:inst4\|pulse_1~422 8 COMB LC3_A9 3 " "Info: 8: + IC(0.600 ns) + CELL(0.800 ns) = 9.500 ns; Loc. = LC3_A9; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~422'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.400 ns" { pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 10.400 ns pulse_sum:inst4\|pulse_1~423 9 COMB LC1_A9 3 " "Info: 9: + IC(0.100 ns) + CELL(0.800 ns) = 10.400 ns; Loc. = LC1_A9; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~423'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(0.800 ns) 11.900 ns pulse_sum:inst4\|pulse_1~424 10 COMB LC4_A1 2 " "Info: 10: + IC(0.700 ns) + CELL(0.800 ns) = 11.900 ns; Loc. = LC4_A1; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_1~424'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.500 ns" { pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.800 ns) 13.700 ns pulse_sum:inst4\|pulse_1~1 11 COMB LC7_A10 2 " "Info: 11: + IC(1.000 ns) + CELL(0.800 ns) = 13.700 ns; Loc. = LC7_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_1~1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.800 ns" { pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 14.600 ns pulse_sum:inst4\|pulse_1\[0\] 12 COMB LOOP LC8_A10 2 " "Info: 12: + IC(0.000 ns) + CELL(0.900 ns) = 14.600 ns; Loc. = LC8_A10; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4\|pulse_1\[0\]'" { { "Info" "ITDB_PART_OF_SCC" "pulse_sum:inst4\|pulse_1\[0\] LC8_A10 " "Info: Loc. = LC8_A10; Node \"pulse_sum:inst4\|pulse_1\[0\]\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[0] } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[0] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.100 ns) 15.800 ns pulse_sum:inst4\|pulse_out~127 13 COMB LC2_A10 2 " "Info: 13: + IC(0.100 ns) + CELL(1.100 ns) = 15.800 ns; Loc. = LC2_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_out~127'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.200 ns" { pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 16.700 ns pulse_sum:inst4\|pulse_out~16 14 COMB LC1_A10 28 " "Info: 14: + IC(0.100 ns) + CELL(0.800 ns) = 16.700 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4\|pulse_out~16'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 18.800 ns sum_control:inst5\|out_control 15 REG LC1_B8 2 " "Info: 15: + IC(2.100 ns) + CELL(0.000 ns) = 18.800 ns; Loc. = LC1_B8; Fanout = 2; REG Node = 'sum_control:inst5\|out_control'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "2.100 ns" { pulse_sum:inst4|pulse_out~16 sum_control:inst5|out_control } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/sum_control.v" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.300 ns 60.11 % " "Info: Total cell delay = 11.300 ns ( 60.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.500 ns 39.89 % " "Info: Total interconnect delay = 7.500 ns ( 39.89 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "18.800 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "18.800 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|out_control } { 0.0ns 0.0ns 0.2ns 0.9ns 0.5ns 1.0ns 0.1ns 0.1ns 0.6ns 0.1ns 0.7ns 1.0ns 0.0ns 0.1ns 0.1ns 2.1ns } { 0.0ns 1.3ns 0.3ns 0.3ns 1.0ns 0.8ns 0.8ns 0.8ns 0.8ns 0.8ns 0.8ns 0.8ns 0.9ns 1.1ns 0.8ns 0.0ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_8MHz source 9.900 ns - Shortest register " "Info: - Shortest clock path from clock \"Clock_8MHz\" to source register is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clock_8MHz 1 CLK PIN_39 26 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 26; CLK Node = 'Clock_8MHz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { Clock_8MHz } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 248 -200 -32 264 "Clock_8MHz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.300 ns) 1.800 ns fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] 2 REG LC3_C7 36 " "Info: 2: + IC(0.200 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC3_C7; Fanout = 36; REG Node = 'fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.500 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.800 ns) 3.500 ns pulse_sum:inst4\|pulse_1~425 3 COMB LC4_A2 2 " "Info: 3: + IC(0.900 ns) + CELL(0.800 ns) = 3.500 ns; Loc. = LC4_A2; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_1~425'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.700 ns" { fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~425 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 5.300 ns pulse_sum:inst4\|pulse_1\[14\] 4 COMB LOOP LC6_A12 2 " "Info: 4: + IC(0.000 ns) + CELL(1.800 ns) = 5.300 ns; Loc. = LC6_A12; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4\|pulse_1\[14\]'" { { "Info" "ITDB_PART_OF_SCC" "pulse_sum:inst4\|pulse_1\[14\] LC6_A12 " "Info: Loc. = LC6_A12; Node \"pulse_sum:inst4\|pulse_1\[14\]\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[14] } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[14] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.800 ns" { pulse_sum:inst4|pulse_1~425 pulse_sum:inst4|pulse_1[14] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 6.200 ns pulse_sum:inst4\|pulse_out~133 5 COMB LC5_A12 2 " "Info: 5: + IC(0.100 ns) + CELL(0.800 ns) = 6.200 ns; Loc. = LC5_A12; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_out~133'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_1[14] pulse_sum:inst4|pulse_out~133 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.000 ns) 7.800 ns pulse_sum:inst4\|pulse_out~16 6 COMB LC1_A10 28 " "Info: 6: + IC(0.600 ns) + CELL(1.000 ns) = 7.800 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4\|pulse_out~16'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.600 ns" { pulse_sum:inst4|pulse_out~133 pulse_sum:inst4|pulse_out~16 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 9.900 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\] 7 REG LC3_B3 4 " "Info: 7: + IC(2.100 ns) + CELL(0.000 ns) = 9.900 ns; Loc. = LC3_B3; Fanout = 4; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "2.100 ns" { pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 60.61 % " "Info: Total cell delay = 6.000 ns ( 60.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns 39.39 % " "Info: Total interconnect delay = 3.900 ns ( 39.39 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "9.900 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~425 pulse_sum:inst4|pulse_1[14] pulse_sum:inst4|pulse_out~133 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "9.900 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~425 pulse_sum:inst4|pulse_1[14] pulse_sum:inst4|pulse_out~133 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } { 0.0ns 0.0ns 0.2ns 0.9ns 0.0ns 0.1ns 0.6ns 2.1ns } { 0.0ns 1.3ns 0.3ns 0.8ns 1.8ns 0.8ns 1.0ns 0.0ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "18.800 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "18.800 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|out_control } { 0.0ns 0.0ns 0.2ns 0.9ns 0.5ns 1.0ns 0.1ns 0.1ns 0.6ns 0.1ns 0.7ns 1.0ns 0.0ns 0.1ns 0.1ns 2.1ns } { 0.0ns 1.3ns 0.3ns 0.3ns 1.0ns 0.8ns 0.8ns 0.8ns 0.8ns 0.8ns 0.8ns 0.8ns 0.9ns 1.1ns 0.8ns 0.0ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "9.900 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~425 pulse_sum:inst4|pulse_1[14] pulse_sum:inst4|pulse_out~133 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "9.900 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~425 pulse_sum:inst4|pulse_1[14] pulse_sum:inst4|pulse_out~133 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } { 0.0ns 0.0ns 0.2ns 0.9ns 0.0ns 0.1ns 0.6ns 2.1ns } { 0.0ns 1.3ns 0.3ns 0.8ns 1.8ns 0.8ns 1.0ns 0.0ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns - " "Info: - Micro clock to output delay of source is 0.300 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.100 ns - Shortest register register " "Info: - Shortest register to register delay is 5.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\] 1 REG LC3_B3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B3; Fanout = 4; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(1.000 ns) 1.700 ns sum_control:inst5\|reduce_nor~295 2 COMB LC3_B4 1 " "Info: 2: + IC(0.700 ns) + CELL(1.000 ns) = 1.700 ns; Loc. = LC3_B4; Fanout = 1; COMB Node = 'sum_control:inst5\|reduce_nor~295'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.700 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] sum_control:inst5|reduce_nor~295 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(1.000 ns) 3.200 ns sum_control:inst5\|reduce_nor~267 3 COMB LC4_B6 2 " "Info: 3: + IC(0.500 ns) + CELL(1.000 ns) = 3.200 ns; Loc. = LC4_B6; Fanout = 2; COMB Node = 'sum_control:inst5\|reduce_nor~267'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.500 ns" { sum_control:inst5|reduce_nor~295 sum_control:inst5|reduce_nor~267 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.800 ns) 4.600 ns sum_control:inst5\|out_control~246 4 COMB LC5_B8 1 " "Info: 4: + IC(0.600 ns) + CELL(0.800 ns) = 4.600 ns; Loc. = LC5_B8; Fanout = 1; COMB Node = 'sum_control:inst5\|out_control~246'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.400 ns" { sum_control:inst5|reduce_nor~267 sum_control:inst5|out_control~246 } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/sum_control.v" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.400 ns) 5.100 ns sum_control:inst5\|out_control 5 REG LC1_B8 2 " "Info: 5: + IC(0.100 ns) + CELL(0.400 ns) = 5.100 ns; Loc. = LC1_B8; Fanout = 2; REG Node = 'sum_control:inst5\|out_control'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.500 ns" { sum_control:inst5|out_control~246 sum_control:inst5|out_control } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/sum_control.v" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns 62.75 % " "Info: Total cell delay = 3.200 ns ( 62.75 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns 37.25 % " "Info: Total interconnect delay = 1.900 ns ( 37.25 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "5.100 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] sum_control:inst5|reduce_nor~295 sum_control:inst5|reduce_nor~267 sum_control:inst5|out_control~246 sum_control:inst5|out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.100 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] sum_control:inst5|reduce_nor~295 sum_control:inst5|reduce_nor~267 sum_control:inst5|out_control~246 sum_control:inst5|out_control } { 0.0ns 0.7ns 0.5ns 0.6ns 0.1ns } { 0.0ns 1.0ns 1.0ns 0.8ns 0.4ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.700 ns + " "Info: + Micro hold delay of destination is 0.700 ns" {  } { { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/sum_control.v" 37 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "18.800 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "18.800 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|out_control } { 0.0ns 0.0ns 0.2ns 0.9ns 0.5ns 1.0ns 0.1ns 0.1ns 0.6ns 0.1ns 0.7ns 1.0ns 0.0ns 0.1ns 0.1ns 2.1ns } { 0.0ns 1.3ns 0.3ns 0.3ns 1.0ns 0.8ns 0.8ns 0.8ns 0.8ns 0.8ns 0.8ns 0.8ns 0.9ns 1.1ns 0.8ns 0.0ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "9.900 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~425 pulse_sum:inst4|pulse_1[14] pulse_sum:inst4|pulse_out~133 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "9.900 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~425 pulse_sum:inst4|pulse_1[14] pulse_sum:inst4|pulse_out~133 pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } { 0.0ns 0.0ns 0.2ns 0.9ns 0.0ns 0.1ns 0.6ns 2.1ns } { 0.0ns 1.3ns 0.3ns 0.8ns 1.8ns 0.8ns 1.0ns 0.0ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "5.100 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] sum_control:inst5|reduce_nor~295 sum_control:inst5|reduce_nor~267 sum_control:inst5|out_control~246 sum_control:inst5|out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.100 ns" { sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] sum_control:inst5|reduce_nor~295 sum_control:inst5|reduce_nor~267 sum_control:inst5|out_control~246 sum_control:inst5|out_control } { 0.0ns 0.7ns 0.5ns 0.6ns 0.1ns } { 0.0ns 1.0ns 1.0ns 0.8ns 0.4ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[16\] Step_Sum\[3\] Reset 10.500 ns register " "Info: tsu for register \"sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[16\]\" (data pin = \"Step_Sum\[3\]\", clock pin = \"Reset\") is 10.500 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.600 ns + Longest pin register " "Info: + Longest pin to register delay is 14.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns Step_Sum\[3\] 1 PIN PIN_61 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_61; Fanout = 2; PIN Node = 'Step_Sum\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { Step_Sum[3] } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 392 -200 -32 408 "Step_Sum\[23..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.400 ns) 4.500 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 2 COMB LC4_B15 2 " "Info: 2: + IC(1.300 ns) + CELL(0.400 ns) = 4.500 ns; Loc. = LC4_B15; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.700 ns" { Step_Sum[3] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 4.600 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 3 COMB LC5_B15 2 " "Info: 3: + IC(0.000 ns) + CELL(0.100 ns) = 4.600 ns; Loc. = LC5_B15; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[3] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 4.700 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 4 COMB LC6_B15 2 " "Info: 4: + IC(0.000 ns) + CELL(0.100 ns) = 4.700 ns; Loc. = LC6_B15; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[4] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 4.800 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 5 COMB LC7_B15 2 " "Info: 5: + IC(0.000 ns) + CELL(0.100 ns) = 4.800 ns; Loc. = LC7_B15; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[5] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 4.900 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\] 6 COMB LC8_B15 2 " "Info: 6: + IC(0.000 ns) + CELL(0.100 ns) = 4.900 ns; Loc. = LC8_B15; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[6] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[7] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.100 ns) 5.300 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\] 7 COMB LC1_B17 2 " "Info: 7: + IC(0.300 ns) + CELL(0.100 ns) = 5.300 ns; Loc. = LC1_B17; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.400 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[7] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[8] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 5.400 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\] 8 COMB LC2_B17 2 " "Info: 8: + IC(0.000 ns) + CELL(0.100 ns) = 5.400 ns; Loc. = LC2_B17; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[8] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[9] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 5.500 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\] 9 COMB LC3_B17 2 " "Info: 9: + IC(0.000 ns) + CELL(0.100 ns) = 5.500 ns; Loc. = LC3_B17; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[9] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[10] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 5.600 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\] 10 COMB LC4_B17 2 " "Info: 10: + IC(0.000 ns) + CELL(0.100 ns) = 5.600 ns; Loc. = LC4_B17; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[10] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[11] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 5.700 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[12\] 11 COMB LC5_B17 2 " "Info: 11: + IC(0.000 ns) + CELL(0.100 ns) = 5.700 ns; Loc. = LC5_B17; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[12\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[11] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[12] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 5.800 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[13\] 12 COMB LC6_B17 2 " "Info: 12: + IC(0.000 ns) + CELL(0.100 ns) = 5.800 ns; Loc. = LC6_B17; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[13\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[12] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[13] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 5.900 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[14\] 13 COMB LC7_B17 2 " "Info: 13: + IC(0.000 ns) + CELL(0.100 ns) = 5.900 ns; Loc. = LC7_B17; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[14\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[13] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[14] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 6.000 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[15\] 14 COMB LC8_B17 2 " "Info: 14: + IC(0.000 ns) + CELL(0.100 ns) = 6.000 ns; Loc. = LC8_B17; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[15\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[14] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[15] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.100 ns) 6.400 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[16\] 15 COMB LC1_B19 2 " "Info: 15: + IC(0.300 ns) + CELL(0.100 ns) = 6.400 ns; Loc. = LC1_B19; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[16\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.400 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[15] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[16] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 6.500 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[17\] 16 COMB LC2_B19 2 " "Info: 16: + IC(0.000 ns) + CELL(0.100 ns) = 6.500 ns; Loc. = LC2_B19; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[17\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[16] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[17] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 6.600 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[18\] 17 COMB LC3_B19 2 " "Info: 17: + IC(0.000 ns) + CELL(0.100 ns) = 6.600 ns; Loc. = LC3_B19; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[18\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[17] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[18] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 6.700 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[19\] 18 COMB LC4_B19 2 " "Info: 18: + IC(0.000 ns) + CELL(0.100 ns) = 6.700 ns; Loc. = LC4_B19; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[19\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[18] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[19] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 6.800 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[20\] 19 COMB LC5_B19 2 " "Info: 19: + IC(0.000 ns) + CELL(0.100 ns) = 6.800 ns; Loc. = LC5_B19; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[20\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[19] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[20] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 6.900 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[21\] 20 COMB LC6_B19 2 " "Info: 20: + IC(0.000 ns) + CELL(0.100 ns) = 6.900 ns; Loc. = LC6_B19; Fanout = 2; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[21\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[20] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[21] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 7.000 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[22\] 21 COMB LC7_B19 1 " "Info: 21: + IC(0.000 ns) + CELL(0.100 ns) = 7.000 ns; Loc. = LC7_B19; Fanout = 1; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cout\[22\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.100 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[21] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[22] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 7.900 ns sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|unreg_res_node\[23\] 22 COMB LC8_B19 1 " "Info: 22: + IC(0.000 ns) + CELL(0.900 ns) = 7.900 ns; Loc. = LC8_B19; Fanout = 1; COMB Node = 'sum_control:inst5\|lpm_add_sub:add_rtl_3\|addcore:adder\|unreg_res_node\[23\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[22] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|unreg_res_node[23] } "NODE_NAME" } "" } } { "addcore.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(0.400 ns) 9.500 ns sum_control:inst5\|reduce_nor~288 23 COMB LC5_B2 1 " "Info: 23: + IC(1.200 ns) + CELL(0.400 ns) = 9.500 ns; Loc. = LC5_B2; Fanout = 1; COMB Node = 'sum_control:inst5\|reduce_nor~288'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.600 ns" { sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|unreg_res_node[23] sum_control:inst5|reduce_nor~288 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 10.500 ns sum_control:inst5\|reduce_nor~297 24 COMB LC6_B2 1 " "Info: 24: + IC(0.000 ns) + CELL(1.000 ns) = 10.500 ns; Loc. = LC6_B2; Fanout = 1; COMB Node = 'sum_control:inst5\|reduce_nor~297'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.000 ns" { sum_control:inst5|reduce_nor~288 sum_control:inst5|reduce_nor~297 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.100 ns) 12.200 ns sum_control:inst5\|reduce_nor~267 25 COMB LC4_B6 2 " "Info: 25: + IC(0.600 ns) + CELL(1.100 ns) = 12.200 ns; Loc. = LC4_B6; Fanout = 2; COMB Node = 'sum_control:inst5\|reduce_nor~267'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.700 ns" { sum_control:inst5|reduce_nor~297 sum_control:inst5|reduce_nor~267 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.000 ns) 13.300 ns rtl~0 26 COMB LC1_B6 54 " "Info: 26: + IC(0.100 ns) + CELL(1.000 ns) = 13.300 ns; Loc. = LC1_B6; Fanout = 54; COMB Node = 'rtl~0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.100 ns" { sum_control:inst5|reduce_nor~267 rtl~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.700 ns) 14.600 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[16\] 27 REG LC1_B7 5 " "Info: 27: + IC(0.600 ns) + CELL(0.700 ns) = 14.600 ns; Loc. = LC1_B7; Fanout = 5; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[16\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.300 ns" { rtl~0 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.200 ns 69.86 % " "Info: Total cell delay = 10.200 ns ( 69.86 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.400 ns 30.14 % " "Info: Total interconnect delay = 4.400 ns ( 30.14 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "14.600 ns" { Step_Sum[3] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[3] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[4] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[5] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[6] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[7] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[8] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[9] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[10] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[11] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[12] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[13] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[14] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[15] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[16] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[17] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[18] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[19] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[20] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[21] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[22] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|unreg_res_node[23] sum_control:inst5|reduce_nor~288 sum_control:inst5|reduce_nor~297 sum_control:inst5|reduce_nor~267 rtl~0 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "14.600 ns" { Step_Sum[3] Step_Sum[3]~out sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[3] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[4] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[5] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[6] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[7] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[8] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[9] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[10] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[11] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[12] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[13] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[14] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[15] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[16] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[17] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[18] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[19] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[20] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[21] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[22] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|unreg_res_node[23] sum_control:inst5|reduce_nor~288 sum_control:inst5|reduce_nor~297 sum_control:inst5|reduce_nor~267 rtl~0 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] } { 0.000ns 0.000ns 1.300ns 0.000ns 0.000ns 0.000ns 0.000ns 0.300ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.300ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.200ns 0.000ns 0.600ns 0.100ns 0.600ns } { 0.000ns 2.800ns 0.400ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.900ns 0.400ns 1.000ns 1.100ns 1.000ns 0.700ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Reset destination 4.500 ns - Shortest register " "Info: - Shortest clock path from clock \"Reset\" to destination register is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Reset 1 CLK PIN_89 51 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 51; CLK Node = 'Reset'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { Reset } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 112 -200 -32 128 "Reset" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.000 ns) 2.400 ns pulse_sum:inst4\|pulse_out~16 2 COMB LC1_A10 28 " "Info: 2: + IC(0.100 ns) + CELL(1.000 ns) = 2.400 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4\|pulse_out~16'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.100 ns" { Reset pulse_sum:inst4|pulse_out~16 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 4.500 ns sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[16\] 3 REG LC1_B7 5 " "Info: 3: + IC(2.100 ns) + CELL(0.000 ns) = 4.500 ns; Loc. = LC1_B7; Fanout = 5; REG Node = 'sum_control:inst5\|lpm_counter:step_counter_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[16\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "2.100 ns" { pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.300 ns 51.11 % " "Info: Total cell delay = 2.300 ns ( 51.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns 48.89 % " "Info: Total interconnect delay = 2.200 ns ( 48.89 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "4.500 ns" { Reset pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.500 ns" { Reset Reset~out pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] } { 0.000ns 0.000ns 0.100ns 2.100ns } { 0.000ns 1.300ns 1.000ns 0.000ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "14.600 ns" { Step_Sum[3] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[3] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[4] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[5] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[6] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[7] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[8] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[9] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[10] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[11] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[12] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[13] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[14] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[15] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[16] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[17] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[18] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[19] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[20] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[21] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[22] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|unreg_res_node[23] sum_control:inst5|reduce_nor~288 sum_control:inst5|reduce_nor~297 sum_control:inst5|reduce_nor~267 rtl~0 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "14.600 ns" { Step_Sum[3] Step_Sum[3]~out sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[3] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[4] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[5] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[6] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[7] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[8] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[9] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[10] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[11] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[12] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[13] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[14] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[15] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[16] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[17] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[18] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[19] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[20] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[21] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[22] sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|unreg_res_node[23] sum_control:inst5|reduce_nor~288 sum_control:inst5|reduce_nor~297 sum_control:inst5|reduce_nor~267 rtl~0 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] } { 0.000ns 0.000ns 1.300ns 0.000ns 0.000ns 0.000ns 0.000ns 0.300ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.300ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.200ns 0.000ns 0.600ns 0.100ns 0.600ns } { 0.000ns 2.800ns 0.400ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.900ns 0.400ns 1.000ns 1.100ns 1.000ns 0.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "4.500 ns" { Reset pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.500 ns" { Reset Reset~out pulse_sum:inst4|pulse_out~16 sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] } { 0.000ns 0.000ns 0.100ns 2.100ns } { 0.000ns 1.300ns 1.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clock_8MHz Pulse_Wave sum_control:inst5\|out_control 24.700 ns register " "Info: tco from clock \"Clock_8MHz\" to destination pin \"Pulse_Wave\" through register \"sum_control:inst5\|out_control\" is 24.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_8MHz source 18.800 ns + Longest register " "Info: + Longest clock path from clock \"Clock_8MHz\" to source register is 18.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clock_8MHz 1 CLK PIN_39 26 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 26; CLK Node = 'Clock_8MHz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { Clock_8MHz } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 248 -200 -32 264 "Clock_8MHz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.300 ns) 1.800 ns fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] 2 REG LC3_C7 36 " "Info: 2: + IC(0.200 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC3_C7; Fanout = 36; REG Node = 'fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.500 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.300 ns) 3.000 ns counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[1\] 3 REG LC2_A3 6 " "Info: 3: + IC(0.900 ns) + CELL(0.300 ns) = 3.000 ns; Loc. = LC2_A3; Fanout = 6; REG Node = 'counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.200 ns" { fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(1.000 ns) 4.500 ns pulse_sum:inst4\|pulse_1~418 4 COMB LC8_A2 3 " "Info: 4: + IC(0.500 ns) + CELL(1.000 ns) = 4.500 ns; Loc. = LC8_A2; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~418'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.500 ns" { counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.800 ns) 6.300 ns pulse_sum:inst4\|pulse_1~419 5 COMB LC3_A11 3 " "Info: 5: + IC(1.000 ns) + CELL(0.800 ns) = 6.300 ns; Loc. = LC3_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~419'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.800 ns" { pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 7.200 ns pulse_sum:inst4\|pulse_1~420 6 COMB LC4_A11 3 " "Info: 6: + IC(0.100 ns) + CELL(0.800 ns) = 7.200 ns; Loc. = LC4_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~420'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 8.100 ns pulse_sum:inst4\|pulse_1~421 7 COMB LC8_A11 3 " "Info: 7: + IC(0.100 ns) + CELL(0.800 ns) = 8.100 ns; Loc. = LC8_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~421'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.800 ns) 9.500 ns pulse_sum:inst4\|pulse_1~422 8 COMB LC3_A9 3 " "Info: 8: + IC(0.600 ns) + CELL(0.800 ns) = 9.500 ns; Loc. = LC3_A9; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~422'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.400 ns" { pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 10.400 ns pulse_sum:inst4\|pulse_1~423 9 COMB LC1_A9 3 " "Info: 9: + IC(0.100 ns) + CELL(0.800 ns) = 10.400 ns; Loc. = LC1_A9; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~423'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(0.800 ns) 11.900 ns pulse_sum:inst4\|pulse_1~424 10 COMB LC4_A1 2 " "Info: 10: + IC(0.700 ns) + CELL(0.800 ns) = 11.900 ns; Loc. = LC4_A1; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_1~424'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.500 ns" { pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.800 ns) 13.700 ns pulse_sum:inst4\|pulse_1~1 11 COMB LC7_A10 2 " "Info: 11: + IC(1.000 ns) + CELL(0.800 ns) = 13.700 ns; Loc. = LC7_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_1~1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.800 ns" { pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 14.600 ns pulse_sum:inst4\|pulse_1\[0\] 12 COMB LOOP LC8_A10 2 " "Info: 12: + IC(0.000 ns) + CELL(0.900 ns) = 14.600 ns; Loc. = LC8_A10; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4\|pulse_1\[0\]'" { { "Info" "ITDB_PART_OF_SCC" "pulse_sum:inst4\|pulse_1\[0\] LC8_A10 " "Info: Loc. = LC8_A10; Node \"pulse_sum:inst4\|pulse_1\[0\]\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[0] } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[0] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.100 ns) 15.800 ns pulse_sum:inst4\|pulse_out~127 13 COMB LC2_A10 2 " "Info: 13: + IC(0.100 ns) + CELL(1.100 ns) = 15.800 ns; Loc. = LC2_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_out~127'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.200 ns" { pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 16.700 ns pulse_sum:inst4\|pulse_out~16 14 COMB LC1_A10 28 " "Info: 14: + IC(0.100 ns) + CELL(0.800 ns) = 16.700 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4\|pulse_out~16'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 18.800 ns sum_control:inst5\|out_control 15 REG LC1_B8 2 " "Info: 15: + IC(2.100 ns) + CELL(0.000 ns) = 18.800 ns; Loc. = LC1_B8; Fanout = 2; REG Node = 'sum_control:inst5\|out_control'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "2.100 ns" { pulse_sum:inst4|pulse_out~16 sum_control:inst5|out_control } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/sum_control.v" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.300 ns 60.11 % " "Info: Total cell delay = 11.300 ns ( 60.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.500 ns 39.89 % " "Info: Total interconnect delay = 7.500 ns ( 39.89 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "18.800 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "18.800 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|out_control } { 0.000ns 0.000ns 0.200ns 0.900ns 0.500ns 1.000ns 0.100ns 0.100ns 0.600ns 0.100ns 0.700ns 1.000ns 0.000ns 0.100ns 0.100ns 2.100ns } { 0.000ns 1.300ns 0.300ns 0.300ns 1.000ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.900ns 1.100ns 0.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" {  } { { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/sum_control.v" 37 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.600 ns + Longest register pin " "Info: + Longest register to pin delay is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sum_control:inst5\|out_control 1 REG LC1_B8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B8; Fanout = 2; REG Node = 'sum_control:inst5\|out_control'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { sum_control:inst5|out_control } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/sum_control.v" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.800 ns) 1.700 ns sum_control:inst5\|wave_out 2 COMB LC6_A10 1 " "Info: 2: + IC(0.900 ns) + CELL(0.800 ns) = 1.700 ns; Loc. = LC6_A10; Fanout = 1; COMB Node = 'sum_control:inst5\|wave_out'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.700 ns" { sum_control:inst5|out_control sum_control:inst5|wave_out } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/sum_control.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(3.800 ns) 5.600 ns Pulse_Wave 3 PIN PIN_46 0 " "Info: 3: + IC(0.100 ns) + CELL(3.800 ns) = 5.600 ns; Loc. = PIN_46; Fanout = 0; PIN Node = 'Pulse_Wave'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "3.900 ns" { sum_control:inst5|wave_out Pulse_Wave } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 312 936 1112 328 "Pulse_Wave" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns 82.14 % " "Info: Total cell delay = 4.600 ns ( 82.14 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 17.86 % " "Info: Total interconnect delay = 1.000 ns ( 17.86 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "5.600 ns" { sum_control:inst5|out_control sum_control:inst5|wave_out Pulse_Wave } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { sum_control:inst5|out_control sum_control:inst5|wave_out Pulse_Wave } { 0.000ns 0.900ns 0.100ns } { 0.000ns 0.800ns 3.800ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "18.800 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "18.800 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|out_control } { 0.000ns 0.000ns 0.200ns 0.900ns 0.500ns 1.000ns 0.100ns 0.100ns 0.600ns 0.100ns 0.700ns 1.000ns 0.000ns 0.100ns 0.100ns 2.100ns } { 0.000ns 1.300ns 0.300ns 0.300ns 1.000ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.900ns 1.100ns 0.800ns 0.000ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "5.600 ns" { sum_control:inst5|out_control sum_control:inst5|wave_out Pulse_Wave } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { sum_control:inst5|out_control sum_control:inst5|wave_out Pulse_Wave } { 0.000ns 0.900ns 0.100ns } { 0.000ns 0.800ns 3.800ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "Reset Pulse_Wave 10.800 ns Longest " "Info: Longest tpd from source pin \"Reset\" to destination pin \"Pulse_Wave\" is 10.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Reset 1 CLK PIN_89 51 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 51; CLK Node = 'Reset'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { Reset } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 112 -200 -32 128 "Reset" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.300 ns pulse_sum:inst4\|pulse_1\[5\] 2 COMB LOOP LC8_A9 2 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 2.300 ns; Loc. = LC8_A9; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4\|pulse_1\[5\]'" { { "Info" "ITDB_PART_OF_SCC" "pulse_sum:inst4\|pulse_1\[5\] LC8_A9 " "Info: Loc. = LC8_A9; Node \"pulse_sum:inst4\|pulse_1\[5\]\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[5] } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[5] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.000 ns" { Reset pulse_sum:inst4|pulse_1[5] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(1.000 ns) 4.000 ns pulse_sum:inst4\|pulse_out~126 3 COMB LC3_A1 1 " "Info: 3: + IC(0.700 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC3_A1; Fanout = 1; COMB Node = 'pulse_sum:inst4\|pulse_out~126'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.700 ns" { pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.800 ns) 5.800 ns pulse_sum:inst4\|pulse_out~127 4 COMB LC2_A10 2 " "Info: 4: + IC(1.000 ns) + CELL(0.800 ns) = 5.800 ns; Loc. = LC2_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_out~127'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.800 ns" { pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.000 ns) 6.900 ns sum_control:inst5\|wave_out 5 COMB LC6_A10 1 " "Info: 5: + IC(0.100 ns) + CELL(1.000 ns) = 6.900 ns; Loc. = LC6_A10; Fanout = 1; COMB Node = 'sum_control:inst5\|wave_out'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.100 ns" { pulse_sum:inst4|pulse_out~127 sum_control:inst5|wave_out } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/sum_control.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(3.800 ns) 10.800 ns Pulse_Wave 6 PIN PIN_46 0 " "Info: 6: + IC(0.100 ns) + CELL(3.800 ns) = 10.800 ns; Loc. = PIN_46; Fanout = 0; PIN Node = 'Pulse_Wave'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "3.900 ns" { sum_control:inst5|wave_out Pulse_Wave } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 312 936 1112 328 "Pulse_Wave" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.900 ns 82.41 % " "Info: Total cell delay = 8.900 ns ( 82.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns 17.59 % " "Info: Total interconnect delay = 1.900 ns ( 17.59 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "10.800 ns" { Reset pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 sum_control:inst5|wave_out Pulse_Wave } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "10.800 ns" { Reset Reset~out pulse_sum:inst4|pulse_1[5] pulse_sum:inst4|pulse_out~126 pulse_sum:inst4|pulse_out~127 sum_control:inst5|wave_out Pulse_Wave } { 0.000ns 0.000ns 0.000ns 0.700ns 1.000ns 0.100ns 0.100ns } { 0.000ns 1.300ns 1.000ns 1.000ns 0.800ns 1.000ns 3.800ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "sum_control:inst5\|out_control Reset Clock_8MHz 16.600 ns register " "Info: th for register \"sum_control:inst5\|out_control\" (data pin = \"Reset\", clock pin = \"Clock_8MHz\") is 16.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_8MHz destination 18.800 ns + Longest register " "Info: + Longest clock path from clock \"Clock_8MHz\" to destination register is 18.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clock_8MHz 1 CLK PIN_39 26 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 26; CLK Node = 'Clock_8MHz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { Clock_8MHz } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 248 -200 -32 264 "Clock_8MHz" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.300 ns) 1.800 ns fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] 2 REG LC3_C7 36 " "Info: 2: + IC(0.200 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC3_C7; Fanout = 36; REG Node = 'fdiv:inst\|lpm_counter:CNT_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.500 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.300 ns) 3.000 ns counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[1\] 3 REG LC2_A3 6 " "Info: 3: + IC(0.900 ns) + CELL(0.300 ns) = 3.000 ns; Loc. = LC2_A3; Fanout = 6; REG Node = 'counter_16_bits:inst1\|lpm_counter:counter_out_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.200 ns" { fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(1.000 ns) 4.500 ns pulse_sum:inst4\|pulse_1~418 4 COMB LC8_A2 3 " "Info: 4: + IC(0.500 ns) + CELL(1.000 ns) = 4.500 ns; Loc. = LC8_A2; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~418'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.500 ns" { counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.800 ns) 6.300 ns pulse_sum:inst4\|pulse_1~419 5 COMB LC3_A11 3 " "Info: 5: + IC(1.000 ns) + CELL(0.800 ns) = 6.300 ns; Loc. = LC3_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~419'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.800 ns" { pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 7.200 ns pulse_sum:inst4\|pulse_1~420 6 COMB LC4_A11 3 " "Info: 6: + IC(0.100 ns) + CELL(0.800 ns) = 7.200 ns; Loc. = LC4_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~420'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 8.100 ns pulse_sum:inst4\|pulse_1~421 7 COMB LC8_A11 3 " "Info: 7: + IC(0.100 ns) + CELL(0.800 ns) = 8.100 ns; Loc. = LC8_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~421'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.800 ns) 9.500 ns pulse_sum:inst4\|pulse_1~422 8 COMB LC3_A9 3 " "Info: 8: + IC(0.600 ns) + CELL(0.800 ns) = 9.500 ns; Loc. = LC3_A9; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~422'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.400 ns" { pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 10.400 ns pulse_sum:inst4\|pulse_1~423 9 COMB LC1_A9 3 " "Info: 9: + IC(0.100 ns) + CELL(0.800 ns) = 10.400 ns; Loc. = LC1_A9; Fanout = 3; COMB Node = 'pulse_sum:inst4\|pulse_1~423'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(0.800 ns) 11.900 ns pulse_sum:inst4\|pulse_1~424 10 COMB LC4_A1 2 " "Info: 10: + IC(0.700 ns) + CELL(0.800 ns) = 11.900 ns; Loc. = LC4_A1; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_1~424'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.500 ns" { pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.800 ns) 13.700 ns pulse_sum:inst4\|pulse_1~1 11 COMB LC7_A10 2 " "Info: 11: + IC(1.000 ns) + CELL(0.800 ns) = 13.700 ns; Loc. = LC7_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_1~1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.800 ns" { pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 14.600 ns pulse_sum:inst4\|pulse_1\[0\] 12 COMB LOOP LC8_A10 2 " "Info: 12: + IC(0.000 ns) + CELL(0.900 ns) = 14.600 ns; Loc. = LC8_A10; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4\|pulse_1\[0\]'" { { "Info" "ITDB_PART_OF_SCC" "pulse_sum:inst4\|pulse_1\[0\] LC8_A10 " "Info: Loc. = LC8_A10; Node \"pulse_sum:inst4\|pulse_1\[0\]\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[0] } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { pulse_sum:inst4|pulse_1[0] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.100 ns) 15.800 ns pulse_sum:inst4\|pulse_out~127 13 COMB LC2_A10 2 " "Info: 13: + IC(0.100 ns) + CELL(1.100 ns) = 15.800 ns; Loc. = LC2_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4\|pulse_out~127'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.200 ns" { pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 16.700 ns pulse_sum:inst4\|pulse_out~16 14 COMB LC1_A10 28 " "Info: 14: + IC(0.100 ns) + CELL(0.800 ns) = 16.700 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4\|pulse_out~16'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.900 ns" { pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 18.800 ns sum_control:inst5\|out_control 15 REG LC1_B8 2 " "Info: 15: + IC(2.100 ns) + CELL(0.000 ns) = 18.800 ns; Loc. = LC1_B8; Fanout = 2; REG Node = 'sum_control:inst5\|out_control'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "2.100 ns" { pulse_sum:inst4|pulse_out~16 sum_control:inst5|out_control } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/sum_control.v" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.300 ns 60.11 % " "Info: Total cell delay = 11.300 ns ( 60.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.500 ns 39.89 % " "Info: Total interconnect delay = 7.500 ns ( 39.89 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "18.800 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "18.800 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|out_control } { 0.000ns 0.000ns 0.200ns 0.900ns 0.500ns 1.000ns 0.100ns 0.100ns 0.600ns 0.100ns 0.700ns 1.000ns 0.000ns 0.100ns 0.100ns 2.100ns } { 0.000ns 1.300ns 0.300ns 0.300ns 1.000ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.900ns 1.100ns 0.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.700 ns + " "Info: + Micro hold delay of destination is 0.700 ns" {  } { { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/sum_control.v" 37 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Reset 1 CLK PIN_89 51 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 51; CLK Node = 'Reset'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "" { Reset } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf" { { 112 -200 -32 128 "Reset" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 2.400 ns sum_control:inst5\|out_control~246 2 COMB LC5_B8 1 " "Info: 2: + IC(0.000 ns) + CELL(1.100 ns) = 2.400 ns; Loc. = LC5_B8; Fanout = 1; COMB Node = 'sum_control:inst5\|out_control~246'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "1.100 ns" { Reset sum_control:inst5|out_control~246 } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/sum_control.v" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.400 ns) 2.900 ns sum_control:inst5\|out_control 3 REG LC1_B8 2 " "Info: 3: + IC(0.100 ns) + CELL(0.400 ns) = 2.900 ns; Loc. = LC1_B8; Fanout = 2; REG Node = 'sum_control:inst5\|out_control'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "0.500 ns" { sum_control:inst5|out_control~246 sum_control:inst5|out_control } "NODE_NAME" } "" } } { "sum_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/sum_control.v" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 96.55 % " "Info: Total cell delay = 2.800 ns ( 96.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.100 ns 3.45 % " "Info: Total interconnect delay = 0.100 ns ( 3.45 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "2.900 ns" { Reset sum_control:inst5|out_control~246 sum_control:inst5|out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.900 ns" { Reset Reset~out sum_control:inst5|out_control~246 sum_control:inst5|out_control } { 0.000ns 0.000ns 0.000ns 0.100ns } { 0.000ns 1.300ns 1.100ns 0.400ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "18.800 ns" { Clock_8MHz fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "18.800 ns" { Clock_8MHz Clock_8MHz~out fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1] counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1] pulse_sum:inst4|pulse_1~418 pulse_sum:inst4|pulse_1~419 pulse_sum:inst4|pulse_1~420 pulse_sum:inst4|pulse_1~421 pulse_sum:inst4|pulse_1~422 pulse_sum:inst4|pulse_1~423 pulse_sum:inst4|pulse_1~424 pulse_sum:inst4|pulse_1~1 pulse_sum:inst4|pulse_1[0] pulse_sum:inst4|pulse_out~127 pulse_sum:inst4|pulse_out~16 sum_control:inst5|out_control } { 0.000ns 0.000ns 0.200ns 0.900ns 0.500ns 1.000ns 0.100ns 0.100ns 0.600ns 0.100ns 0.700ns 1.000ns 0.000ns 0.100ns 0.100ns 2.100ns } { 0.000ns 1.300ns 0.300ns 0.300ns 1.000ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.800ns 0.900ns 1.100ns 0.800ns 0.000ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/" "" "2.900 ns" { Reset sum_control:inst5|out_control~246 sum_control:inst5|out_control } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.900 ns" { Reset Reset~out sum_control:inst5|out_control~246 sum_control:inst5|out_control } { 0.000ns 0.000ns 0.000ns 0.100ns } { 0.000ns 1.300ns 1.100ns 0.400ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 20 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 02 16:41:50 2006 " "Info: Processing ended: Wed Aug 02 16:41:50 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}
