{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 08 10:48:07 2006 " "Info: Processing started: Tue Aug 08 10:48:07 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off Coder_8_3 -c Coder_8_3 " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Coder_8_3 -c Coder_8_3" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "EN A1 5.000 ns Longest " "Info: Longest tpd from source pin \"EN\" to destination pin \"A1\" is 5.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns EN 1 PIN PIN_36 5 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_36; Fanout = 5; PIN Node = 'EN'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/db/Coder_8_3_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/db/Coder_8_3_cmp.qrpt" Compiler "Coder_8_3" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/db/Coder_8_3.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/" "" "" { EN } "NODE_NAME" } "" } } { "Coder_8_3.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/Coder_8_3.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns A1~98 2 COMB LC6 1 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC6; Fanout = 1; COMB Node = 'A1~98'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/db/Coder_8_3_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/db/Coder_8_3_cmp.qrpt" Compiler "Coder_8_3" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/db/Coder_8_3.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/" "" "4.600 ns" { EN A1~98 } "NODE_NAME" } "" } } { "Coder_8_3.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/Coder_8_3.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.000 ns A1 3 PIN PIN_9 0 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 5.000 ns; Loc. = PIN_9; Fanout = 0; PIN Node = 'A1'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/db/Coder_8_3_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/db/Coder_8_3_cmp.qrpt" Compiler "Coder_8_3" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/db/Coder_8_3.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/" "" "0.200 ns" { A1~98 A1 } "NODE_NAME" } "" } } { "Coder_8_3.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/Coder_8_3.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 80.00 % " "Info: Total cell delay = 4.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 20.00 % " "Info: Total interconnect delay = 1.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/db/Coder_8_3_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/db/Coder_8_3_cmp.qrpt" Compiler "Coder_8_3" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/db/Coder_8_3.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Coder_8_3/" "" "5.000 ns" { EN A1~98 A1 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "5.000 ns" { EN EN~out A1~98 A1 } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 0.200ns 3.600ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 08 10:48:07 2006 " "Info: Processing ended: Tue Aug 08 10:48:07 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}
