{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 15 23:19:21 2006 " "Info: Processing started: Sat Jul 15 23:19:21 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off main -c main --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off main -c main --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_FOUND_COMB_LATCHES" "" "Warning: Timing Analysis found one or more latches implemented as combinational loops" { { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|Data\[2\] " "Warning: Node \"disp_data_mux:inst8\|Data\[2\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|Data\[3\] " "Warning: Node \"disp_data_mux:inst8\|Data\[3\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|Data\[0\] " "Warning: Node \"disp_data_mux:inst8\|Data\[0\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|Data\[1\] " "Warning: Node \"disp_data_mux:inst8\|Data\[1\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "time_disp_select:inst6\|disp_drive\[1\] " "Warning: Node \"time_disp_select:inst6\|disp_drive\[1\]\" is a latch" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "time_disp_select:inst6\|disp_drive\[0\] " "Warning: Node \"time_disp_select:inst6\|disp_drive\[0\]\" is a latch" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "time_disp_select:inst6\|disp_drive\[2\] " "Warning: Node \"time_disp_select:inst6\|disp_drive\[2\]\" is a latch" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "time_disp_select:inst6\|clk " "Warning: Node \"time_disp_select:inst6\|clk\" is a latch" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|disp_select\[5\] " "Warning: Node \"disp_data_mux:inst8\|disp_select\[5\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|disp_select\[4\] " "Warning: Node \"disp_data_mux:inst8\|disp_select\[4\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|disp_select\[3\] " "Warning: Node \"disp_data_mux:inst8\|disp_select\[3\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|disp_select\[2\] " "Warning: Node \"disp_data_mux:inst8\|disp_select\[2\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|disp_select\[1\] " "Warning: Node \"disp_data_mux:inst8\|disp_select\[1\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "disp_data_mux:inst8\|disp_select\[0\] " "Warning: Node \"disp_data_mux:inst8\|disp_select\[0\]\" is a latch" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_data_mux:inst8\|disp_select\[0\] " "Info: Node \"disp_data_mux:inst8\|disp_select\[0\]\"" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_data_mux:inst8\|disp_select\[1\] " "Info: Node \"disp_data_mux:inst8\|disp_select\[1\]\"" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_data_mux:inst8\|disp_select\[2\] " "Info: Node \"disp_data_mux:inst8\|disp_select\[2\]\"" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_data_mux:inst8\|disp_select\[3\] " "Info: Node \"disp_data_mux:inst8\|disp_select\[3\]\"" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_data_mux:inst8\|disp_select\[4\] " "Info: Node \"disp_data_mux:inst8\|disp_select\[4\]\"" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_data_mux:inst8\|disp_select\[5\] " "Info: Node \"disp_data_mux:inst8\|disp_select\[5\]\"" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 20 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "time_disp_select:inst6\|clk " "Info: Node \"time_disp_select:inst6\|clk\"" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0}  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "time_disp_select:inst6\|disp_drive\[2\] " "Info: Node \"time_disp_select:inst6\|disp_drive\[2\]\"" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0}  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "time_disp_select:inst6\|disp_drive\[0\] " "Info: Node \"time_disp_select:inst6\|disp_drive\[0\]\"" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0}  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "time_disp_select:inst6\|disp_drive\[1\] " "Info: Node \"time_disp_select:inst6\|disp_drive\[1\]\"" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0}  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_data_mux:inst8\|Data\[1\] " "Info: Node \"disp_data_mux:inst8\|Data\[1\]\"" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0}  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_data_mux:inst8\|Data\[0\] " "Info: Node \"disp_data_mux:inst8\|Data\[0\]\"" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0}  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_data_mux:inst8\|Data\[3\] " "Info: Node \"disp_data_mux:inst8\|Data\[3\]\"" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0}  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_data_mux:inst8\|Data\[2\] " "Info: Node \"disp_data_mux:inst8\|Data\[2\]\"" {  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0}  } { { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "SW2 " "Info: Assuming node \"SW2\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 392 -40 128 408 "SW2" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW2" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "Clock " "Info: Assuming node \"Clock\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 128 -40 128 144 "Clock" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Clock" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW3 " "Info: Assuming node \"SW3\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 232 -40 128 248 "SW3" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW3" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW1 " "Info: Assuming node \"SW1\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 408 -40 128 424 "SW1" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW1" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "13 " "Warning: Found 13 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "time_disp_select:inst6\|clk~21 " "Info: Detected gated clock \"time_disp_select:inst6\|clk~21\" as buffer" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "time_disp_select:inst6\|clk~21" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "time_disp_select:inst6\|clk~22 " "Info: Detected gated clock \"time_disp_select:inst6\|clk~22\" as buffer" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "time_disp_select:inst6\|clk~22" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "time_disp_select:inst6\|always1~2 " "Info: Detected gated clock \"time_disp_select:inst6\|always1~2\" as buffer" {  } { { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "time_disp_select:inst6\|always1~2" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO " "Info: Detected ripple clock \"time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO\" as buffer" {  } { { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/hour_counter.v" 4 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst5\|f200hz " "Info: Detected ripple clock \"fdiv:inst5\|f200hz\" as buffer" {  } { { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/fdiv.v" 7 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fdiv:inst5\|f200hz" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "maincontrol:inst3\|Stopwatch_EN " "Info: Detected ripple clock \"maincontrol:inst3\|Stopwatch_EN\" as buffer" {  } { { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/maincontrol.v" 10 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "maincontrol:inst3\|Stopwatch_EN" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst5\|f1hz " "Info: Detected ripple clock \"fdiv:inst5\|f1hz\" as buffer" {  } { { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/fdiv.v" 7 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fdiv:inst5\|f1hz" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst5\|f60hz " "Info: Detected ripple clock \"fdiv:inst5\|f60hz\" as buffer" {  } { { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/fdiv.v" 7 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fdiv:inst5\|f60hz" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "stopwatch:inst2\|F_out~8 " "Info: Detected gated clock \"stopwatch:inst2\|F_out~8\" as buffer" {  } { { "stopwatch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/stopwatch.v" 3 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "stopwatch:inst2\|F_out~8" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO " "Info: Detected ripple clock \"time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO\" as buffer" {  } { { "minute_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/minute_counter.v" 4 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "maincontrol:inst3\|TimeSet_EN " "Info: Detected ripple clock \"maincontrol:inst3\|TimeSet_EN\" as buffer" {  } { { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/maincontrol.v" 10 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "maincontrol:inst3\|TimeSet_EN" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO " "Info: Detected ripple clock \"time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO\" as buffer" {  } { { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/second_counter.v" 4 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "maincontrol:inst3\|Timepiece_EN " "Info: Detected ripple clock \"maincontrol:inst3\|Timepiece_EN\" as buffer" {  } { { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/maincontrol.v" 10 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "maincontrol:inst3\|Timepiece_EN" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW2 register alarmclock:inst11\|lpm_counter:hour_set1_rtl_15\|cntr_e08:auto_generated\|safe_q\[1\] register alarmclock:inst11\|lpm_counter:hour_set0_rtl_12\|cntr_e08:auto_generated\|safe_q\[2\] 286.37 MHz 3.492 ns Internal " "Info: Clock \"SW2\" has Internal fmax of 286.37 MHz between source register \"alarmclock:inst11\|lpm_counter:hour_set1_rtl_15\|cntr_e08:auto_generated\|safe_q\[1\]\" and destination register \"alarmclock:inst11\|lpm_counter:hour_set0_rtl_12\|cntr_e08:auto_generated\|safe_q\[2\]\" (period= 3.492 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.319 ns + Longest register register " "Info: + Longest register to register delay is 3.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns alarmclock:inst11\|lpm_counter:hour_set1_rtl_15\|cntr_e08:auto_generated\|safe_q\[1\] 1 REG LC_X39_Y11_N7 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X39_Y11_N7; Fanout = 6; REG Node = 'alarmclock:inst11\|lpm_counter:hour_set1_rtl_15\|cntr_e08:auto_generated\|safe_q\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.961 ns) + CELL(0.280 ns) 1.241 ns alarmclock:inst11\|LessThan~214 2 COMB LC_X36_Y11_N4 5 " "Info: 2: + IC(0.961 ns) + CELL(0.280 ns) = 1.241 ns; Loc. = LC_X36_Y11_N4; Fanout = 5; COMB Node = 'alarmclock:inst11\|LessThan~214'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.241 ns" { alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] alarmclock:inst11|LessThan~214 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.778 ns) + CELL(0.183 ns) 2.202 ns alarmclock:inst11\|hour_set0\[2\]~118 3 COMB LC_X36_Y11_N0 4 " "Info: 3: + IC(0.778 ns) + CELL(0.183 ns) = 2.202 ns; Loc. = LC_X36_Y11_N0; Fanout = 4; COMB Node = 'alarmclock:inst11\|hour_set0\[2\]~118'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "0.961 ns" { alarmclock:inst11|LessThan~214 alarmclock:inst11|hour_set0[2]~118 } "NODE_NAME" } "" } } { "alarmclock.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/alarmclock.v" 105 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.356 ns) + CELL(0.761 ns) 3.319 ns alarmclock:inst11\|lpm_counter:hour_set0_rtl_12\|cntr_e08:auto_generated\|safe_q\[2\] 4 REG LC_X36_Y11_N8 5 " "Info: 4: + IC(0.356 ns) + CELL(0.761 ns) = 3.319 ns; Loc. = LC_X36_Y11_N8; Fanout = 5; REG Node = 'alarmclock:inst11\|lpm_counter:hour_set0_rtl_12\|cntr_e08:auto_generated\|safe_q\[2\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.117 ns" { alarmclock:inst11|hour_set0[2]~118 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.224 ns 36.88 % " "Info: Total cell delay = 1.224 ns ( 36.88 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.095 ns 63.12 % " "Info: Total interconnect delay = 2.095 ns ( 63.12 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.319 ns" { alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] alarmclock:inst11|LessThan~214 alarmclock:inst11|hour_set0[2]~118 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.319 ns" { alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] alarmclock:inst11|LessThan~214 alarmclock:inst11|hour_set0[2]~118 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } { 0.000ns 0.961ns 0.778ns 0.356ns } { 0.000ns 0.280ns 0.183ns 0.761ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.007 ns - Smallest " "Info: - Smallest clock skew is -0.007 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 destination 2.855 ns + Shortest register " "Info: + Shortest clock path from clock \"SW2\" to destination register is 2.855 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns SW2 1 CLK PIN_L2 64 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 64; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { SW2 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 392 -40 128 408 "SW2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.588 ns) + CELL(0.542 ns) 2.855 ns alarmclock:inst11\|lpm_counter:hour_set0_rtl_12\|cntr_e08:auto_generated\|safe_q\[2\] 2 REG LC_X36_Y11_N8 5 " "Info: 2: + IC(1.588 ns) + CELL(0.542 ns) = 2.855 ns; Loc. = LC_X36_Y11_N8; Fanout = 5; REG Node = 'alarmclock:inst11\|lpm_counter:hour_set0_rtl_12\|cntr_e08:auto_generated\|safe_q\[2\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.130 ns" { SW2 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 44.38 % " "Info: Total cell delay = 1.267 ns ( 44.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.588 ns 55.62 % " "Info: Total interconnect delay = 1.588 ns ( 55.62 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.855 ns" { SW2 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.855 ns" { SW2 SW2~out0 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } { 0.000ns 0.000ns 1.588ns } { 0.000ns 0.725ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 source 2.862 ns - Longest register " "Info: - Longest clock path from clock \"SW2\" to source register is 2.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns SW2 1 CLK PIN_L2 64 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 64; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { SW2 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 392 -40 128 408 "SW2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.595 ns) + CELL(0.542 ns) 2.862 ns alarmclock:inst11\|lpm_counter:hour_set1_rtl_15\|cntr_e08:auto_generated\|safe_q\[1\] 2 REG LC_X39_Y11_N7 6 " "Info: 2: + IC(1.595 ns) + CELL(0.542 ns) = 2.862 ns; Loc. = LC_X39_Y11_N7; Fanout = 6; REG Node = 'alarmclock:inst11\|lpm_counter:hour_set1_rtl_15\|cntr_e08:auto_generated\|safe_q\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.137 ns" { SW2 alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 44.27 % " "Info: Total cell delay = 1.267 ns ( 44.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.595 ns 55.73 % " "Info: Total interconnect delay = 1.595 ns ( 55.73 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.862 ns" { SW2 alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.862 ns" { SW2 SW2~out0 alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] } { 0.000ns 0.000ns 1.595ns } { 0.000ns 0.725ns 0.542ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.855 ns" { SW2 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.855 ns" { SW2 SW2~out0 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } { 0.000ns 0.000ns 1.588ns } { 0.000ns 0.725ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.862 ns" { SW2 alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.862 ns" { SW2 SW2~out0 alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] } { 0.000ns 0.000ns 1.595ns } { 0.000ns 0.725ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.319 ns" { alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] alarmclock:inst11|LessThan~214 alarmclock:inst11|hour_set0[2]~118 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.319 ns" { alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] alarmclock:inst11|LessThan~214 alarmclock:inst11|hour_set0[2]~118 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } { 0.000ns 0.961ns 0.778ns 0.356ns } { 0.000ns 0.280ns 0.183ns 0.761ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.855 ns" { SW2 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.855 ns" { SW2 SW2~out0 alarmclock:inst11|lpm_counter:hour_set0_rtl_12|cntr_e08:auto_generated|safe_q[2] } { 0.000ns 0.000ns 1.588ns } { 0.000ns 0.725ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.862 ns" { SW2 alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.862 ns" { SW2 SW2~out0 alarmclock:inst11|lpm_counter:hour_set1_rtl_15|cntr_e08:auto_generated|safe_q[1] } { 0.000ns 0.000ns 1.595ns } { 0.000ns 0.725ns 0.542ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clock register date_main:inst4\|autodate:b2v_inst\|EO1 register date_main:inst4\|datecontrol:b2v_inst1\|day0\[3\] 45.62 MHz 21.921 ns Internal " "Info: Clock \"Clock\" has Internal fmax of 45.62 MHz between source register \"date_main:inst4\|autodate:b2v_inst\|EO1\" and destination register \"date_main:inst4\|datecontrol:b2v_inst1\|day0\[3\]\" (period= 21.921 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.414 ns + Longest register register " "Info: + Longest register to register delay is 2.414 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns date_main:inst4\|autodate:b2v_inst\|EO1 1 REG LC_X35_Y14_N2 21 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y14_N2; Fanout = 21; REG Node = 'date_main:inst4\|autodate:b2v_inst\|EO1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { date_main:inst4|autodate:b2v_inst|EO1 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/autodate.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.473 ns) + CELL(0.075 ns) 0.548 ns date_main:inst4\|datecontrol:b2v_inst1\|disp_select\[3\]~43 2 COMB LC_X35_Y14_N3 20 " "Info: 2: + IC(0.473 ns) + CELL(0.075 ns) = 0.548 ns; Loc. = LC_X35_Y14_N3; Fanout = 20; COMB Node = 'date_main:inst4\|datecontrol:b2v_inst1\|disp_select\[3\]~43'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "0.548 ns" { date_main:inst4|autodate:b2v_inst|EO1 date_main:inst4|datecontrol:b2v_inst1|disp_select[3]~43 } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/datecontrol.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.161 ns) + CELL(0.705 ns) 2.414 ns date_main:inst4\|datecontrol:b2v_inst1\|day0\[3\] 3 REG LC_X35_Y12_N2 1 " "Info: 3: + IC(1.161 ns) + CELL(0.705 ns) = 2.414 ns; Loc. = LC_X35_Y12_N2; Fanout = 1; REG Node = 'date_main:inst4\|datecontrol:b2v_inst1\|day0\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.866 ns" { date_main:inst4|datecontrol:b2v_inst1|disp_select[3]~43 date_main:inst4|datecontrol:b2v_inst1|day0[3] } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/datecontrol.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.780 ns 32.31 % " "Info: Total cell delay = 0.780 ns ( 32.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.634 ns 67.69 % " "Info: Total interconnect delay = 1.634 ns ( 67.69 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.414 ns" { date_main:inst4|autodate:b2v_inst|EO1 date_main:inst4|datecontrol:b2v_inst1|disp_select[3]~43 date_main:inst4|datecontrol:b2v_inst1|day0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.414 ns" { date_main:inst4|autodate:b2v_inst|EO1 date_main:inst4|datecontrol:b2v_inst1|disp_select[3]~43 date_main:inst4|datecontrol:b2v_inst1|day0[3] } { 0.000ns 0.473ns 1.161ns } { 0.000ns 0.075ns 0.705ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-19.341 ns - Smallest " "Info: - Smallest clock skew is -19.341 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 6.804 ns + Shortest register " "Info: + Shortest clock path from clock \"Clock\" to destination register is 6.804 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns Clock 1 CLK PIN_L3 37 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L3; Fanout = 37; CLK Node = 'Clock'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { Clock } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 128 -40 128 144 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.681 ns) + CELL(0.698 ns) 3.207 ns fdiv:inst5\|f200hz 2 REG LC_X28_Y1_N8 93 " "Info: 2: + IC(1.681 ns) + CELL(0.698 ns) = 3.207 ns; Loc. = LC_X28_Y1_N8; Fanout = 93; REG Node = 'fdiv:inst5\|f200hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.379 ns" { Clock fdiv:inst5|f200hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/fdiv.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.055 ns) + CELL(0.542 ns) 6.804 ns date_main:inst4\|datecontrol:b2v_inst1\|day0\[3\] 3 REG LC_X35_Y12_N2 1 " "Info: 3: + IC(3.055 ns) + CELL(0.542 ns) = 6.804 ns; Loc. = LC_X35_Y12_N2; Fanout = 1; REG Node = 'date_main:inst4\|datecontrol:b2v_inst1\|day0\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.597 ns" { fdiv:inst5|f200hz date_main:inst4|datecontrol:b2v_inst1|day0[3] } "NODE_NAME" } "" } } { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/datecontrol.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.068 ns 30.39 % " "Info: Total cell delay = 2.068 ns ( 30.39 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.736 ns 69.61 % " "Info: Total interconnect delay = 4.736 ns ( 69.61 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "6.804 ns" { Clock fdiv:inst5|f200hz date_main:inst4|datecontrol:b2v_inst1|day0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.804 ns" { Clock Clock~out0 fdiv:inst5|f200hz date_main:inst4|datecontrol:b2v_inst1|day0[3] } { 0.000ns 0.000ns 1.681ns 3.055ns } { 0.000ns 0.828ns 0.698ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 26.145 ns - Longest register " "Info: - Longest clock path from clock \"Clock\" to source register is 26.145 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns Clock 1 CLK PIN_L3 37 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L3; Fanout = 37; CLK Node = 'Clock'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { Clock } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 128 -40 128 144 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.681 ns) + CELL(0.698 ns) 3.207 ns fdiv:inst5\|f200hz 2 REG LC_X28_Y1_N8 93 " "Info: 2: + IC(1.681 ns) + CELL(0.698 ns) = 3.207 ns; Loc. = LC_X28_Y1_N8; Fanout = 93; REG Node = 'fdiv:inst5\|f200hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.379 ns" { Clock fdiv:inst5|f200hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/fdiv.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.076 ns) + CELL(0.698 ns) 6.981 ns fdiv:inst5\|f60hz 3 REG LC_X31_Y1_N7 1 " "Info: 3: + IC(3.076 ns) + CELL(0.698 ns) = 6.981 ns; Loc. = LC_X31_Y1_N7; Fanout = 1; REG Node = 'fdiv:inst5\|f60hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.774 ns" { fdiv:inst5|f200hz fdiv:inst5|f60hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/fdiv.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.047 ns) + CELL(0.280 ns) 8.308 ns stopwatch:inst2\|F_out~8 4 COMB LC_X32_Y5_N9 9 " "Info: 4: + IC(1.047 ns) + CELL(0.280 ns) = 8.308 ns; Loc. = LC_X32_Y5_N9; Fanout = 9; COMB Node = 'stopwatch:inst2\|F_out~8'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.327 ns" { fdiv:inst5|f60hz stopwatch:inst2|F_out~8 } "NODE_NAME" } "" } } { "stopwatch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/stopwatch.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.284 ns) + CELL(0.698 ns) 12.290 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO 5 REG LC_X33_Y9_N8 9 " "Info: 5: + IC(3.284 ns) + CELL(0.698 ns) = 12.290 ns; Loc. = LC_X33_Y9_N8; Fanout = 9; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.982 ns" { stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/second_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.273 ns) + CELL(0.698 ns) 17.261 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO 6 REG LC_X36_Y9_N0 9 " "Info: 6: + IC(4.273 ns) + CELL(0.698 ns) = 17.261 ns; Loc. = LC_X36_Y9_N0; Fanout = 9; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "4.971 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO } "NODE_NAME" } "" } } { "minute_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/minute_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.852 ns) + CELL(0.698 ns) 21.811 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO 7 REG LC_X33_Y13_N4 14 " "Info: 7: + IC(3.852 ns) + CELL(0.698 ns) = 21.811 ns; Loc. = LC_X33_Y13_N4; Fanout = 14; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "4.550 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/hour_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.792 ns) + CELL(0.542 ns) 26.145 ns date_main:inst4\|autodate:b2v_inst\|EO1 8 REG LC_X35_Y14_N2 21 " "Info: 8: + IC(3.792 ns) + CELL(0.542 ns) = 26.145 ns; Loc. = LC_X35_Y14_N2; Fanout = 21; REG Node = 'date_main:inst4\|autodate:b2v_inst\|EO1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "4.334 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/autodate.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.140 ns 19.66 % " "Info: Total cell delay = 5.140 ns ( 19.66 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "21.005 ns 80.34 % " "Info: Total interconnect delay = 21.005 ns ( 80.34 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "26.145 ns" { Clock fdiv:inst5|f200hz fdiv:inst5|f60hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "26.145 ns" { Clock Clock~out0 fdiv:inst5|f200hz fdiv:inst5|f60hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } { 0.000ns 0.000ns 1.681ns 3.076ns 1.047ns 3.284ns 4.273ns 3.852ns 3.792ns } { 0.000ns 0.828ns 0.698ns 0.698ns 0.280ns 0.698ns 0.698ns 0.698ns 0.542ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "6.804 ns" { Clock fdiv:inst5|f200hz date_main:inst4|datecontrol:b2v_inst1|day0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.804 ns" { Clock Clock~out0 fdiv:inst5|f200hz date_main:inst4|datecontrol:b2v_inst1|day0[3] } { 0.000ns 0.000ns 1.681ns 3.055ns } { 0.000ns 0.828ns 0.698ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "26.145 ns" { Clock fdiv:inst5|f200hz fdiv:inst5|f60hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "26.145 ns" { Clock Clock~out0 fdiv:inst5|f200hz fdiv:inst5|f60hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } { 0.000ns 0.000ns 1.681ns 3.076ns 1.047ns 3.284ns 4.273ns 3.852ns 3.792ns } { 0.000ns 0.828ns 0.698ns 0.698ns 0.280ns 0.698ns 0.698ns 0.698ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/autodate.v" 4 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "datecontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/datecontrol.v" 7 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.414 ns" { date_main:inst4|autodate:b2v_inst|EO1 date_main:inst4|datecontrol:b2v_inst1|disp_select[3]~43 date_main:inst4|datecontrol:b2v_inst1|day0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.414 ns" { date_main:inst4|autodate:b2v_inst|EO1 date_main:inst4|datecontrol:b2v_inst1|disp_select[3]~43 date_main:inst4|datecontrol:b2v_inst1|day0[3] } { 0.000ns 0.473ns 1.161ns } { 0.000ns 0.075ns 0.705ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "6.804 ns" { Clock fdiv:inst5|f200hz date_main:inst4|datecontrol:b2v_inst1|day0[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.804 ns" { Clock Clock~out0 fdiv:inst5|f200hz date_main:inst4|datecontrol:b2v_inst1|day0[3] } { 0.000ns 0.000ns 1.681ns 3.055ns } { 0.000ns 0.828ns 0.698ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "26.145 ns" { Clock fdiv:inst5|f200hz fdiv:inst5|f60hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "26.145 ns" { Clock Clock~out0 fdiv:inst5|f200hz fdiv:inst5|f60hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } { 0.000ns 0.000ns 1.681ns 3.076ns 1.047ns 3.284ns 4.273ns 3.852ns 3.792ns } { 0.000ns 0.828ns 0.698ns 0.698ns 0.280ns 0.698ns 0.698ns 0.698ns 0.542ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW3 register date_main:inst4\|autodate:b2v_inst\|lpm_counter:day1_rtl_21\|cntr_e08:auto_generated\|safe_q\[3\] register date_main:inst4\|autodate:b2v_inst\|lpm_counter:month0_rtl_26\|cntr_e08:auto_generated\|safe_q\[3\] 155.79 MHz 6.419 ns Internal " "Info: Clock \"SW3\" has Internal fmax of 155.79 MHz between source register \"date_main:inst4\|autodate:b2v_inst\|lpm_counter:day1_rtl_21\|cntr_e08:auto_generated\|safe_q\[3\]\" and destination register \"date_main:inst4\|autodate:b2v_inst\|lpm_counter:month0_rtl_26\|cntr_e08:auto_generated\|safe_q\[3\]\" (period= 6.419 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.253 ns + Longest register register " "Info: + Longest register to register delay is 6.253 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns date_main:inst4\|autodate:b2v_inst\|lpm_counter:day1_rtl_21\|cntr_e08:auto_generated\|safe_q\[3\] 1 REG LC_X36_Y13_N3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y13_N3; Fanout = 5; REG Node = 'date_main:inst4\|autodate:b2v_inst\|lpm_counter:day1_rtl_21\|cntr_e08:auto_generated\|safe_q\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.045 ns) + CELL(0.280 ns) 1.325 ns date_main:inst4\|autodate:b2v_inst\|always0~575 2 COMB LC_X36_Y12_N6 2 " "Info: 2: + IC(1.045 ns) + CELL(0.280 ns) = 1.325 ns; Loc. = LC_X36_Y12_N6; Fanout = 2; COMB Node = 'date_main:inst4\|autodate:b2v_inst\|always0~575'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.325 ns" { date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated|safe_q[3] date_main:inst4|autodate:b2v_inst|always0~575 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.825 ns) + CELL(0.366 ns) 2.516 ns date_main:inst4\|autodate:b2v_inst\|always0~577 3 COMB LC_X35_Y12_N4 3 " "Info: 3: + IC(0.825 ns) + CELL(0.366 ns) = 2.516 ns; Loc. = LC_X35_Y12_N4; Fanout = 3; COMB Node = 'date_main:inst4\|autodate:b2v_inst\|always0~577'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.191 ns" { date_main:inst4|autodate:b2v_inst|always0~575 date_main:inst4|autodate:b2v_inst|always0~577 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.205 ns) + CELL(0.183 ns) 3.904 ns date_main:inst4\|autodate:b2v_inst\|month1\[0\]~199 4 COMB LC_X34_Y13_N1 2 " "Info: 4: + IC(1.205 ns) + CELL(0.183 ns) = 3.904 ns; Loc. = LC_X34_Y13_N1; Fanout = 2; COMB Node = 'date_main:inst4\|autodate:b2v_inst\|month1\[0\]~199'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.388 ns" { date_main:inst4|autodate:b2v_inst|always0~577 date_main:inst4|autodate:b2v_inst|month1[0]~199 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/autodate.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.533 ns) + CELL(0.366 ns) 4.803 ns date_main:inst4\|autodate:b2v_inst\|month0\[0\]~524 5 COMB LC_X35_Y13_N9 1 " "Info: 5: + IC(0.533 ns) + CELL(0.366 ns) = 4.803 ns; Loc. = LC_X35_Y13_N9; Fanout = 1; COMB Node = 'date_main:inst4\|autodate:b2v_inst\|month0\[0\]~524'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "0.899 ns" { date_main:inst4|autodate:b2v_inst|month1[0]~199 date_main:inst4|autodate:b2v_inst|month0[0]~524 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/autodate.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.322 ns) + CELL(0.075 ns) 5.200 ns date_main:inst4\|autodate:b2v_inst\|month0\[0\]~525 6 COMB LC_X35_Y13_N4 4 " "Info: 6: + IC(0.322 ns) + CELL(0.075 ns) = 5.200 ns; Loc. = LC_X35_Y13_N4; Fanout = 4; COMB Node = 'date_main:inst4\|autodate:b2v_inst\|month0\[0\]~525'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "0.397 ns" { date_main:inst4|autodate:b2v_inst|month0[0]~524 date_main:inst4|autodate:b2v_inst|month0[0]~525 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/autodate.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.348 ns) + CELL(0.705 ns) 6.253 ns date_main:inst4\|autodate:b2v_inst\|lpm_counter:month0_rtl_26\|cntr_e08:auto_generated\|safe_q\[3\] 7 REG LC_X35_Y13_N3 6 " "Info: 7: + IC(0.348 ns) + CELL(0.705 ns) = 6.253 ns; Loc. = LC_X35_Y13_N3; Fanout = 6; REG Node = 'date_main:inst4\|autodate:b2v_inst\|lpm_counter:month0_rtl_26\|cntr_e08:auto_generated\|safe_q\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.053 ns" { date_main:inst4|autodate:b2v_inst|month0[0]~525 date_main:inst4|autodate:b2v_inst|lpm_counter:month0_rtl_26|cntr_e08:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.975 ns 31.58 % " "Info: Total cell delay = 1.975 ns ( 31.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.278 ns 68.42 % " "Info: Total interconnect delay = 4.278 ns ( 68.42 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "6.253 ns" { date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated|safe_q[3] date_main:inst4|autodate:b2v_inst|always0~575 date_main:inst4|autodate:b2v_inst|always0~577 date_main:inst4|autodate:b2v_inst|month1[0]~199 date_main:inst4|autodate:b2v_inst|month0[0]~524 date_main:inst4|autodate:b2v_inst|month0[0]~525 date_main:inst4|autodate:b2v_inst|lpm_counter:month0_rtl_26|cntr_e08:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.253 ns" { date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated|safe_q[3] date_main:inst4|autodate:b2v_inst|always0~575 date_main:inst4|autodate:b2v_inst|always0~577 date_main:inst4|autodate:b2v_inst|month1[0]~199 date_main:inst4|autodate:b2v_inst|month0[0]~524 date_main:inst4|autodate:b2v_inst|month0[0]~525 date_main:inst4|autodate:b2v_inst|lpm_counter:month0_rtl_26|cntr_e08:auto_generated|safe_q[3] } { 0.000ns 1.045ns 0.825ns 1.205ns 0.533ns 0.322ns 0.348ns } { 0.000ns 0.280ns 0.366ns 0.183ns 0.366ns 0.075ns 0.705ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW3 destination 21.931 ns + Shortest register " "Info: + Shortest clock path from clock \"SW3\" to destination register is 21.931 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns SW3 1 CLK PIN_M2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M2; Fanout = 9; CLK Node = 'SW3'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { SW3 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 232 -40 128 248 "SW3" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.591 ns) + CELL(0.698 ns) 3.014 ns maincontrol:inst3\|Stopwatch_EN 2 REG LC_X33_Y8_N9 8 " "Info: 2: + IC(1.591 ns) + CELL(0.698 ns) = 3.014 ns; Loc. = LC_X33_Y8_N9; Fanout = 8; REG Node = 'maincontrol:inst3\|Stopwatch_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.289 ns" { SW3 maincontrol:inst3|Stopwatch_EN } "NODE_NAME" } "" } } { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/maincontrol.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.075 ns) 4.103 ns stopwatch:inst2\|F_out~8 3 COMB LC_X32_Y5_N9 9 " "Info: 3: + IC(1.014 ns) + CELL(0.075 ns) = 4.103 ns; Loc. = LC_X32_Y5_N9; Fanout = 9; COMB Node = 'stopwatch:inst2\|F_out~8'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.089 ns" { maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 } "NODE_NAME" } "" } } { "stopwatch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/stopwatch.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.284 ns) + CELL(0.698 ns) 8.085 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO 4 REG LC_X33_Y9_N8 9 " "Info: 4: + IC(3.284 ns) + CELL(0.698 ns) = 8.085 ns; Loc. = LC_X33_Y9_N8; Fanout = 9; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.982 ns" { stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/second_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.273 ns) + CELL(0.698 ns) 13.056 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO 5 REG LC_X36_Y9_N0 9 " "Info: 5: + IC(4.273 ns) + CELL(0.698 ns) = 13.056 ns; Loc. = LC_X36_Y9_N0; Fanout = 9; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "4.971 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO } "NODE_NAME" } "" } } { "minute_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/minute_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.852 ns) + CELL(0.698 ns) 17.606 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO 6 REG LC_X33_Y13_N4 14 " "Info: 6: + IC(3.852 ns) + CELL(0.698 ns) = 17.606 ns; Loc. = LC_X33_Y13_N4; Fanout = 14; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "4.550 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/hour_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.783 ns) + CELL(0.542 ns) 21.931 ns date_main:inst4\|autodate:b2v_inst\|lpm_counter:month0_rtl_26\|cntr_e08:auto_generated\|safe_q\[3\] 7 REG LC_X35_Y13_N3 6 " "Info: 7: + IC(3.783 ns) + CELL(0.542 ns) = 21.931 ns; Loc. = LC_X35_Y13_N3; Fanout = 6; REG Node = 'date_main:inst4\|autodate:b2v_inst\|lpm_counter:month0_rtl_26\|cntr_e08:auto_generated\|safe_q\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "4.325 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|lpm_counter:month0_rtl_26|cntr_e08:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.134 ns 18.85 % " "Info: Total cell delay = 4.134 ns ( 18.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "17.797 ns 81.15 % " "Info: Total interconnect delay = 17.797 ns ( 81.15 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "21.931 ns" { SW3 maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|lpm_counter:month0_rtl_26|cntr_e08:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "21.931 ns" { SW3 SW3~out0 maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|lpm_counter:month0_rtl_26|cntr_e08:auto_generated|safe_q[3] } { 0.000ns 0.000ns 1.591ns 1.014ns 3.284ns 4.273ns 3.852ns 3.783ns } { 0.000ns 0.725ns 0.698ns 0.075ns 0.698ns 0.698ns 0.698ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW3 source 21.931 ns - Longest register " "Info: - Longest clock path from clock \"SW3\" to source register is 21.931 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns SW3 1 CLK PIN_M2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M2; Fanout = 9; CLK Node = 'SW3'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { SW3 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 232 -40 128 248 "SW3" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.591 ns) + CELL(0.698 ns) 3.014 ns maincontrol:inst3\|Stopwatch_EN 2 REG LC_X33_Y8_N9 8 " "Info: 2: + IC(1.591 ns) + CELL(0.698 ns) = 3.014 ns; Loc. = LC_X33_Y8_N9; Fanout = 8; REG Node = 'maincontrol:inst3\|Stopwatch_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.289 ns" { SW3 maincontrol:inst3|Stopwatch_EN } "NODE_NAME" } "" } } { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/maincontrol.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.075 ns) 4.103 ns stopwatch:inst2\|F_out~8 3 COMB LC_X32_Y5_N9 9 " "Info: 3: + IC(1.014 ns) + CELL(0.075 ns) = 4.103 ns; Loc. = LC_X32_Y5_N9; Fanout = 9; COMB Node = 'stopwatch:inst2\|F_out~8'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.089 ns" { maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 } "NODE_NAME" } "" } } { "stopwatch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/stopwatch.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.284 ns) + CELL(0.698 ns) 8.085 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO 4 REG LC_X33_Y9_N8 9 " "Info: 4: + IC(3.284 ns) + CELL(0.698 ns) = 8.085 ns; Loc. = LC_X33_Y9_N8; Fanout = 9; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.982 ns" { stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/second_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.273 ns) + CELL(0.698 ns) 13.056 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO 5 REG LC_X36_Y9_N0 9 " "Info: 5: + IC(4.273 ns) + CELL(0.698 ns) = 13.056 ns; Loc. = LC_X36_Y9_N0; Fanout = 9; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "4.971 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO } "NODE_NAME" } "" } } { "minute_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/minute_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.852 ns) + CELL(0.698 ns) 17.606 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO 6 REG LC_X33_Y13_N4 14 " "Info: 6: + IC(3.852 ns) + CELL(0.698 ns) = 17.606 ns; Loc. = LC_X33_Y13_N4; Fanout = 14; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "4.550 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/hour_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.783 ns) + CELL(0.542 ns) 21.931 ns date_main:inst4\|autodate:b2v_inst\|lpm_counter:day1_rtl_21\|cntr_e08:auto_generated\|safe_q\[3\] 7 REG LC_X36_Y13_N3 5 " "Info: 7: + IC(3.783 ns) + CELL(0.542 ns) = 21.931 ns; Loc. = LC_X36_Y13_N3; Fanout = 5; REG Node = 'date_main:inst4\|autodate:b2v_inst\|lpm_counter:day1_rtl_21\|cntr_e08:auto_generated\|safe_q\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "4.325 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.134 ns 18.85 % " "Info: Total cell delay = 4.134 ns ( 18.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "17.797 ns 81.15 % " "Info: Total interconnect delay = 17.797 ns ( 81.15 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "21.931 ns" { SW3 maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "21.931 ns" { SW3 SW3~out0 maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated|safe_q[3] } { 0.000ns 0.000ns 1.591ns 1.014ns 3.284ns 4.273ns 3.852ns 3.783ns } { 0.000ns 0.725ns 0.698ns 0.075ns 0.698ns 0.698ns 0.698ns 0.542ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "21.931 ns" { SW3 maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|lpm_counter:month0_rtl_26|cntr_e08:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "21.931 ns" { SW3 SW3~out0 maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|lpm_counter:month0_rtl_26|cntr_e08:auto_generated|safe_q[3] } { 0.000ns 0.000ns 1.591ns 1.014ns 3.284ns 4.273ns 3.852ns 3.783ns } { 0.000ns 0.725ns 0.698ns 0.075ns 0.698ns 0.698ns 0.698ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "21.931 ns" { SW3 maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "21.931 ns" { SW3 SW3~out0 maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated|safe_q[3] } { 0.000ns 0.000ns 1.591ns 1.014ns 3.284ns 4.273ns 3.852ns 3.783ns } { 0.000ns 0.725ns 0.698ns 0.075ns 0.698ns 0.698ns 0.698ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "6.253 ns" { date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated|safe_q[3] date_main:inst4|autodate:b2v_inst|always0~575 date_main:inst4|autodate:b2v_inst|always0~577 date_main:inst4|autodate:b2v_inst|month1[0]~199 date_main:inst4|autodate:b2v_inst|month0[0]~524 date_main:inst4|autodate:b2v_inst|month0[0]~525 date_main:inst4|autodate:b2v_inst|lpm_counter:month0_rtl_26|cntr_e08:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.253 ns" { date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated|safe_q[3] date_main:inst4|autodate:b2v_inst|always0~575 date_main:inst4|autodate:b2v_inst|always0~577 date_main:inst4|autodate:b2v_inst|month1[0]~199 date_main:inst4|autodate:b2v_inst|month0[0]~524 date_main:inst4|autodate:b2v_inst|month0[0]~525 date_main:inst4|autodate:b2v_inst|lpm_counter:month0_rtl_26|cntr_e08:auto_generated|safe_q[3] } { 0.000ns 1.045ns 0.825ns 1.205ns 0.533ns 0.322ns 0.348ns } { 0.000ns 0.280ns 0.366ns 0.183ns 0.366ns 0.075ns 0.705ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "21.931 ns" { SW3 maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|lpm_counter:month0_rtl_26|cntr_e08:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "21.931 ns" { SW3 SW3~out0 maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|lpm_counter:month0_rtl_26|cntr_e08:auto_generated|safe_q[3] } { 0.000ns 0.000ns 1.591ns 1.014ns 3.284ns 4.273ns 3.852ns 3.783ns } { 0.000ns 0.725ns 0.698ns 0.075ns 0.698ns 0.698ns 0.698ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "21.931 ns" { SW3 maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "21.931 ns" { SW3 SW3~out0 maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|lpm_counter:day1_rtl_21|cntr_e08:auto_generated|safe_q[3] } { 0.000ns 0.000ns 1.591ns 1.014ns 3.284ns 4.273ns 3.852ns 3.783ns } { 0.000ns 0.725ns 0.698ns 0.075ns 0.698ns 0.698ns 0.698ns 0.542ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "SW1 register register time_auto_and_set:inst1\|timeset:b2v_inst3\|disp_drive\[0\] time_auto_and_set:inst1\|timeset:b2v_inst3\|disp_drive\[1\] 422.12 MHz Internal " "Info: Clock \"SW1\" Internal fmax is restricted to 422.12 MHz between source register \"time_auto_and_set:inst1\|timeset:b2v_inst3\|disp_drive\[0\]\" and destination register \"time_auto_and_set:inst1\|timeset:b2v_inst3\|disp_drive\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.995 ns + Longest register register " "Info: + Longest register to register delay is 0.995 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns time_auto_and_set:inst1\|timeset:b2v_inst3\|disp_drive\[0\] 1 REG LC_X35_Y7_N2 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y7_N2; Fanout = 10; REG Node = 'time_auto_and_set:inst1\|timeset:b2v_inst3\|disp_drive\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[0] } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/timeset.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.539 ns) 0.995 ns time_auto_and_set:inst1\|timeset:b2v_inst3\|disp_drive\[1\] 2 REG LC_X35_Y7_N9 10 " "Info: 2: + IC(0.456 ns) + CELL(0.539 ns) = 0.995 ns; Loc. = LC_X35_Y7_N9; Fanout = 10; REG Node = 'time_auto_and_set:inst1\|timeset:b2v_inst3\|disp_drive\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "0.995 ns" { time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[0] time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[1] } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/timeset.v" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.539 ns 54.17 % " "Info: Total cell delay = 0.539 ns ( 54.17 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.456 ns 45.83 % " "Info: Total interconnect delay = 0.456 ns ( 45.83 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "0.995 ns" { time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[0] time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.995 ns" { time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[0] time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[1] } { 0.000ns 0.456ns } { 0.000ns 0.539ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 2.990 ns + Shortest register " "Info: + Shortest clock path from clock \"SW1\" to destination register is 2.990 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns SW1 1 CLK PIN_M3 8 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M3; Fanout = 8; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { SW1 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 408 -40 128 424 "SW1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.620 ns) + CELL(0.542 ns) 2.990 ns time_auto_and_set:inst1\|timeset:b2v_inst3\|disp_drive\[1\] 2 REG LC_X35_Y7_N9 10 " "Info: 2: + IC(1.620 ns) + CELL(0.542 ns) = 2.990 ns; Loc. = LC_X35_Y7_N9; Fanout = 10; REG Node = 'time_auto_and_set:inst1\|timeset:b2v_inst3\|disp_drive\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.162 ns" { SW1 time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[1] } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/timeset.v" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns 45.82 % " "Info: Total cell delay = 1.370 ns ( 45.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.620 ns 54.18 % " "Info: Total interconnect delay = 1.620 ns ( 54.18 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.990 ns" { SW1 time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.990 ns" { SW1 SW1~out0 time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[1] } { 0.000ns 0.000ns 1.620ns } { 0.000ns 0.828ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 source 2.990 ns - Longest register " "Info: - Longest clock path from clock \"SW1\" to source register is 2.990 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns SW1 1 CLK PIN_M3 8 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M3; Fanout = 8; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { SW1 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 408 -40 128 424 "SW1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.620 ns) + CELL(0.542 ns) 2.990 ns time_auto_and_set:inst1\|timeset:b2v_inst3\|disp_drive\[0\] 2 REG LC_X35_Y7_N2 10 " "Info: 2: + IC(1.620 ns) + CELL(0.542 ns) = 2.990 ns; Loc. = LC_X35_Y7_N2; Fanout = 10; REG Node = 'time_auto_and_set:inst1\|timeset:b2v_inst3\|disp_drive\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.162 ns" { SW1 time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[0] } "NODE_NAME" } "" } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/timeset.v" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns 45.82 % " "Info: Total cell delay = 1.370 ns ( 45.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.620 ns 54.18 % " "Info: Total interconnect delay = 1.620 ns ( 54.18 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.990 ns" { SW1 time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.990 ns" { SW1 SW1~out0 time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[0] } { 0.000ns 0.000ns 1.620ns } { 0.000ns 0.828ns 0.542ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.990 ns" { SW1 time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.990 ns" { SW1 SW1~out0 time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[1] } { 0.000ns 0.000ns 1.620ns } { 0.000ns 0.828ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.990 ns" { SW1 time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.990 ns" { SW1 SW1~out0 time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[0] } { 0.000ns 0.000ns 1.620ns } { 0.000ns 0.828ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/timeset.v" 15 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/timeset.v" 15 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "0.995 ns" { time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[0] time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.995 ns" { time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[0] time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[1] } { 0.000ns 0.456ns } { 0.000ns 0.539ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.990 ns" { SW1 time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.990 ns" { SW1 SW1~out0 time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[1] } { 0.000ns 0.000ns 1.620ns } { 0.000ns 0.828ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.990 ns" { SW1 time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.990 ns" { SW1 SW1~out0 time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[0] } { 0.000ns 0.000ns 1.620ns } { 0.000ns 0.828ns 0.542ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { time_auto_and_set:inst1|timeset:b2v_inst3|disp_drive[1] } {  } {  } } } { "timeset.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/timeset.v" 15 -1 0 } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "Clock 26 " "Warning: Circuit may not operate. Detected 26 non-operational path(s) clocked by clock \"Clock\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "time_disp_select:inst6\|auto_disp_drive\[1\] time_disp_select:inst6\|time_disp_select\[3\] Clock 3.706 ns " "Info: Found hold time violation between source  pin or register \"time_disp_select:inst6\|auto_disp_drive\[1\]\" and destination pin or register \"time_disp_select:inst6\|time_disp_select\[3\]\" for clock \"Clock\" (Hold time is 3.706 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.090 ns + Largest " "Info: + Largest clock skew is 6.090 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 9.122 ns + Longest register " "Info: + Longest clock path from clock \"Clock\" to destination register is 9.122 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns Clock 1 CLK PIN_L3 37 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L3; Fanout = 37; CLK Node = 'Clock'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { Clock } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 128 -40 128 144 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.681 ns) + CELL(0.698 ns) 3.207 ns fdiv:inst5\|f200hz 2 REG LC_X28_Y1_N8 93 " "Info: 2: + IC(1.681 ns) + CELL(0.698 ns) = 3.207 ns; Loc. = LC_X28_Y1_N8; Fanout = 93; REG Node = 'fdiv:inst5\|f200hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.379 ns" { Clock fdiv:inst5|f200hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/fdiv.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.421 ns) + CELL(0.280 ns) 4.908 ns time_disp_select:inst6\|clk~21 3 COMB LC_X35_Y6_N2 2 " "Info: 3: + IC(1.421 ns) + CELL(0.280 ns) = 4.908 ns; Loc. = LC_X35_Y6_N2; Fanout = 2; COMB Node = 'time_disp_select:inst6\|clk~21'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.701 ns" { fdiv:inst5|f200hz time_disp_select:inst6|clk~21 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 5.117 ns time_disp_select:inst6\|clk 4 COMB LOOP LC_X35_Y6_N3 7 " "Info: 4: + IC(0.000 ns) + CELL(0.209 ns) = 5.117 ns; Loc. = LC_X35_Y6_N3; Fanout = 7; COMB LOOP Node = 'time_disp_select:inst6\|clk'" { { "Info" "ITDB_PART_OF_SCC" "time_disp_select:inst6\|clk LC_X35_Y6_N3 " "Info: Loc. = LC_X35_Y6_N3; Node \"time_disp_select:inst6\|clk\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { time_disp_select:inst6|clk } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { time_disp_select:inst6|clk } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "0.209 ns" { time_disp_select:inst6|clk~21 time_disp_select:inst6|clk } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.463 ns) + CELL(0.542 ns) 9.122 ns time_disp_select:inst6\|time_disp_select\[3\] 5 REG LC_X35_Y6_N4 5 " "Info: 5: + IC(3.463 ns) + CELL(0.542 ns) = 9.122 ns; Loc. = LC_X35_Y6_N4; Fanout = 5; REG Node = 'time_disp_select:inst6\|time_disp_select\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "4.005 ns" { time_disp_select:inst6|clk time_disp_select:inst6|time_disp_select[3] } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.557 ns 28.03 % " "Info: Total cell delay = 2.557 ns ( 28.03 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.565 ns 71.97 % " "Info: Total interconnect delay = 6.565 ns ( 71.97 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "9.122 ns" { Clock fdiv:inst5|f200hz time_disp_select:inst6|clk~21 time_disp_select:inst6|clk time_disp_select:inst6|time_disp_select[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "9.122 ns" { Clock Clock~out0 fdiv:inst5|f200hz time_disp_select:inst6|clk~21 time_disp_select:inst6|clk time_disp_select:inst6|time_disp_select[3] } { 0.0ns 0.0ns 1.681ns 1.421ns 0.0ns 3.463ns } { 0.0ns 0.828ns 0.698ns 0.28ns 0.209ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 3.032 ns - Shortest register " "Info: - Shortest clock path from clock \"Clock\" to source register is 3.032 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns Clock 1 CLK PIN_L3 37 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L3; Fanout = 37; CLK Node = 'Clock'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { Clock } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 128 -40 128 144 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.662 ns) + CELL(0.542 ns) 3.032 ns time_disp_select:inst6\|auto_disp_drive\[1\] 2 REG LC_X36_Y5_N2 4 " "Info: 2: + IC(1.662 ns) + CELL(0.542 ns) = 3.032 ns; Loc. = LC_X36_Y5_N2; Fanout = 4; REG Node = 'time_disp_select:inst6\|auto_disp_drive\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.204 ns" { Clock time_disp_select:inst6|auto_disp_drive[1] } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns 45.18 % " "Info: Total cell delay = 1.370 ns ( 45.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.662 ns 54.82 % " "Info: Total interconnect delay = 1.662 ns ( 54.82 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.032 ns" { Clock time_disp_select:inst6|auto_disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.032 ns" { Clock Clock~out0 time_disp_select:inst6|auto_disp_drive[1] } { 0.0ns 0.0ns 1.662ns } { 0.0ns 0.828ns 0.542ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "9.122 ns" { Clock fdiv:inst5|f200hz time_disp_select:inst6|clk~21 time_disp_select:inst6|clk time_disp_select:inst6|time_disp_select[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "9.122 ns" { Clock Clock~out0 fdiv:inst5|f200hz time_disp_select:inst6|clk~21 time_disp_select:inst6|clk time_disp_select:inst6|time_disp_select[3] } { 0.0ns 0.0ns 1.681ns 1.421ns 0.0ns 3.463ns } { 0.0ns 0.828ns 0.698ns 0.28ns 0.209ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.032 ns" { Clock time_disp_select:inst6|auto_disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.032 ns" { Clock Clock~out0 time_disp_select:inst6|auto_disp_drive[1] } { 0.0ns 0.0ns 1.662ns } { 0.0ns 0.828ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns - " "Info: - Micro clock to output delay of source is 0.156 ns" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 28 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.328 ns - Shortest register register " "Info: - Shortest register to register delay is 2.328 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns time_disp_select:inst6\|auto_disp_drive\[1\] 1 REG LC_X36_Y5_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y5_N2; Fanout = 4; REG Node = 'time_disp_select:inst6\|auto_disp_drive\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { time_disp_select:inst6|auto_disp_drive[1] } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 28 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.996 ns) + CELL(0.075 ns) 1.071 ns time_disp_select:inst6\|disp_drive~68 2 COMB LC_X36_Y6_N7 2 " "Info: 2: + IC(0.996 ns) + CELL(0.075 ns) = 1.071 ns; Loc. = LC_X36_Y6_N7; Fanout = 2; COMB Node = 'time_disp_select:inst6\|disp_drive~68'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.071 ns" { time_disp_select:inst6|auto_disp_drive[1] time_disp_select:inst6|disp_drive~68 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.669 ns) 1.740 ns time_disp_select:inst6\|disp_drive\[1\] 3 COMB LOOP LC_X35_Y6_N0 7 " "Info: 3: + IC(0.000 ns) + CELL(0.669 ns) = 1.740 ns; Loc. = LC_X35_Y6_N0; Fanout = 7; COMB LOOP Node = 'time_disp_select:inst6\|disp_drive\[1\]'" { { "Info" "ITDB_PART_OF_SCC" "time_disp_select:inst6\|disp_drive\[1\] LC_X35_Y6_N0 " "Info: Loc. = LC_X35_Y6_N0; Node \"time_disp_select:inst6\|disp_drive\[1\]\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { time_disp_select:inst6|disp_drive[1] } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { time_disp_select:inst6|disp_drive[1] } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "0.669 ns" { time_disp_select:inst6|disp_drive~68 time_disp_select:inst6|disp_drive[1] } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.223 ns) 2.328 ns time_disp_select:inst6\|time_disp_select\[3\] 4 REG LC_X35_Y6_N4 5 " "Info: 4: + IC(0.365 ns) + CELL(0.223 ns) = 2.328 ns; Loc. = LC_X35_Y6_N4; Fanout = 5; REG Node = 'time_disp_select:inst6\|time_disp_select\[3\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "0.588 ns" { time_disp_select:inst6|disp_drive[1] time_disp_select:inst6|time_disp_select[3] } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.967 ns 41.54 % " "Info: Total cell delay = 0.967 ns ( 41.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.361 ns 58.46 % " "Info: Total interconnect delay = 1.361 ns ( 58.46 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.328 ns" { time_disp_select:inst6|auto_disp_drive[1] time_disp_select:inst6|disp_drive~68 time_disp_select:inst6|disp_drive[1] time_disp_select:inst6|time_disp_select[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.328 ns" { time_disp_select:inst6|auto_disp_drive[1] time_disp_select:inst6|disp_drive~68 time_disp_select:inst6|disp_drive[1] time_disp_select:inst6|time_disp_select[3] } { 0.0ns 0.996ns 0.0ns 0.365ns } { 0.0ns 0.075ns 0.669ns 0.223ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_disp_select.v" 10 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "9.122 ns" { Clock fdiv:inst5|f200hz time_disp_select:inst6|clk~21 time_disp_select:inst6|clk time_disp_select:inst6|time_disp_select[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "9.122 ns" { Clock Clock~out0 fdiv:inst5|f200hz time_disp_select:inst6|clk~21 time_disp_select:inst6|clk time_disp_select:inst6|time_disp_select[3] } { 0.0ns 0.0ns 1.681ns 1.421ns 0.0ns 3.463ns } { 0.0ns 0.828ns 0.698ns 0.28ns 0.209ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.032 ns" { Clock time_disp_select:inst6|auto_disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.032 ns" { Clock Clock~out0 time_disp_select:inst6|auto_disp_drive[1] } { 0.0ns 0.0ns 1.662ns } { 0.0ns 0.828ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.328 ns" { time_disp_select:inst6|auto_disp_drive[1] time_disp_select:inst6|disp_drive~68 time_disp_select:inst6|disp_drive[1] time_disp_select:inst6|time_disp_select[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.328 ns" { time_disp_select:inst6|auto_disp_drive[1] time_disp_select:inst6|disp_drive~68 time_disp_select:inst6|disp_drive[1] time_disp_select:inst6|time_disp_select[3] } { 0.0ns 0.996ns 0.0ns 0.365ns } { 0.0ns 0.075ns 0.669ns 0.223ns } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "SW3 53 " "Warning: Circuit may not operate. Detected 53 non-operational path(s) clocked by clock \"SW3\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "maincontrol:inst3\|DateSet_EN date_main:inst4\|autodate:b2v_inst\|EO1 SW3 17.443 ns " "Info: Found hold time violation between source  pin or register \"maincontrol:inst3\|DateSet_EN\" and destination pin or register \"date_main:inst4\|autodate:b2v_inst\|EO1\" for clock \"SW3\" (Hold time is 17.443 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "19.073 ns + Largest " "Info: + Largest clock skew is 19.073 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW3 destination 21.940 ns + Longest register " "Info: + Longest clock path from clock \"SW3\" to destination register is 21.940 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns SW3 1 CLK PIN_M2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M2; Fanout = 9; CLK Node = 'SW3'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { SW3 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 232 -40 128 248 "SW3" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.591 ns) + CELL(0.698 ns) 3.014 ns maincontrol:inst3\|Stopwatch_EN 2 REG LC_X33_Y8_N9 8 " "Info: 2: + IC(1.591 ns) + CELL(0.698 ns) = 3.014 ns; Loc. = LC_X33_Y8_N9; Fanout = 8; REG Node = 'maincontrol:inst3\|Stopwatch_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.289 ns" { SW3 maincontrol:inst3|Stopwatch_EN } "NODE_NAME" } "" } } { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/maincontrol.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.075 ns) 4.103 ns stopwatch:inst2\|F_out~8 3 COMB LC_X32_Y5_N9 9 " "Info: 3: + IC(1.014 ns) + CELL(0.075 ns) = 4.103 ns; Loc. = LC_X32_Y5_N9; Fanout = 9; COMB Node = 'stopwatch:inst2\|F_out~8'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.089 ns" { maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 } "NODE_NAME" } "" } } { "stopwatch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/stopwatch.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.284 ns) + CELL(0.698 ns) 8.085 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO 4 REG LC_X33_Y9_N8 9 " "Info: 4: + IC(3.284 ns) + CELL(0.698 ns) = 8.085 ns; Loc. = LC_X33_Y9_N8; Fanout = 9; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.982 ns" { stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/second_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.273 ns) + CELL(0.698 ns) 13.056 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO 5 REG LC_X36_Y9_N0 9 " "Info: 5: + IC(4.273 ns) + CELL(0.698 ns) = 13.056 ns; Loc. = LC_X36_Y9_N0; Fanout = 9; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "4.971 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO } "NODE_NAME" } "" } } { "minute_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/minute_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.852 ns) + CELL(0.698 ns) 17.606 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO 6 REG LC_X33_Y13_N4 14 " "Info: 6: + IC(3.852 ns) + CELL(0.698 ns) = 17.606 ns; Loc. = LC_X33_Y13_N4; Fanout = 14; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "4.550 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO } "NODE_NAME" } "" } } { "hour_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/hour_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.792 ns) + CELL(0.542 ns) 21.940 ns date_main:inst4\|autodate:b2v_inst\|EO1 7 REG LC_X35_Y14_N2 21 " "Info: 7: + IC(3.792 ns) + CELL(0.542 ns) = 21.940 ns; Loc. = LC_X35_Y14_N2; Fanout = 21; REG Node = 'date_main:inst4\|autodate:b2v_inst\|EO1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "4.334 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/autodate.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.134 ns 18.84 % " "Info: Total cell delay = 4.134 ns ( 18.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "17.806 ns 81.16 % " "Info: Total interconnect delay = 17.806 ns ( 81.16 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "21.940 ns" { SW3 maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "21.940 ns" { SW3 SW3~out0 maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } { 0.0ns 0.0ns 1.591ns 1.014ns 3.284ns 4.273ns 3.852ns 3.792ns } { 0.0ns 0.725ns 0.698ns 0.075ns 0.698ns 0.698ns 0.698ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW3 source 2.867 ns - Shortest register " "Info: - Shortest clock path from clock \"SW3\" to source register is 2.867 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns SW3 1 CLK PIN_M2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M2; Fanout = 9; CLK Node = 'SW3'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { SW3 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 232 -40 128 248 "SW3" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.542 ns) 2.867 ns maincontrol:inst3\|DateSet_EN 2 REG LC_X34_Y13_N9 8 " "Info: 2: + IC(1.600 ns) + CELL(0.542 ns) = 2.867 ns; Loc. = LC_X34_Y13_N9; Fanout = 8; REG Node = 'maincontrol:inst3\|DateSet_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.142 ns" { SW3 maincontrol:inst3|DateSet_EN } "NODE_NAME" } "" } } { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/maincontrol.v" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 44.19 % " "Info: Total cell delay = 1.267 ns ( 44.19 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 55.81 % " "Info: Total interconnect delay = 1.600 ns ( 55.81 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.867 ns" { SW3 maincontrol:inst3|DateSet_EN } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.867 ns" { SW3 SW3~out0 maincontrol:inst3|DateSet_EN } { 0.0ns 0.0ns 1.6ns } { 0.0ns 0.725ns 0.542ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "21.940 ns" { SW3 maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "21.940 ns" { SW3 SW3~out0 maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } { 0.0ns 0.0ns 1.591ns 1.014ns 3.284ns 4.273ns 3.852ns 3.792ns } { 0.0ns 0.725ns 0.698ns 0.075ns 0.698ns 0.698ns 0.698ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.867 ns" { SW3 maincontrol:inst3|DateSet_EN } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.867 ns" { SW3 SW3~out0 maincontrol:inst3|DateSet_EN } { 0.0ns 0.0ns 1.6ns } { 0.0ns 0.725ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns - " "Info: - Micro clock to output delay of source is 0.156 ns" {  } { { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/maincontrol.v" 10 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.574 ns - Shortest register register " "Info: - Shortest register to register delay is 1.574 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns maincontrol:inst3\|DateSet_EN 1 REG LC_X34_Y13_N9 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y13_N9; Fanout = 8; REG Node = 'maincontrol:inst3\|DateSet_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { maincontrol:inst3|DateSet_EN } "NODE_NAME" } "" } } { "maincontrol.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/maincontrol.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.255 ns) + CELL(0.319 ns) 1.574 ns date_main:inst4\|autodate:b2v_inst\|EO1 2 REG LC_X35_Y14_N2 21 " "Info: 2: + IC(1.255 ns) + CELL(0.319 ns) = 1.574 ns; Loc. = LC_X35_Y14_N2; Fanout = 21; REG Node = 'date_main:inst4\|autodate:b2v_inst\|EO1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.574 ns" { maincontrol:inst3|DateSet_EN date_main:inst4|autodate:b2v_inst|EO1 } "NODE_NAME" } "" } } { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/autodate.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.319 ns 20.27 % " "Info: Total cell delay = 0.319 ns ( 20.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.255 ns 79.73 % " "Info: Total interconnect delay = 1.255 ns ( 79.73 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.574 ns" { maincontrol:inst3|DateSet_EN date_main:inst4|autodate:b2v_inst|EO1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.574 ns" { maincontrol:inst3|DateSet_EN date_main:inst4|autodate:b2v_inst|EO1 } { 0.0ns 1.255ns } { 0.0ns 0.319ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "autodate.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/autodate.v" 4 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "21.940 ns" { SW3 maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "21.940 ns" { SW3 SW3~out0 maincontrol:inst3|Stopwatch_EN stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|EO date_main:inst4|autodate:b2v_inst|EO1 } { 0.0ns 0.0ns 1.591ns 1.014ns 3.284ns 4.273ns 3.852ns 3.792ns } { 0.0ns 0.725ns 0.698ns 0.075ns 0.698ns 0.698ns 0.698ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.867 ns" { SW3 maincontrol:inst3|DateSet_EN } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.867 ns" { SW3 SW3~out0 maincontrol:inst3|DateSet_EN } { 0.0ns 0.0ns 1.6ns } { 0.0ns 0.725ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.574 ns" { maincontrol:inst3|DateSet_EN date_main:inst4|autodate:b2v_inst|EO1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.574 ns" { maincontrol:inst3|DateSet_EN date_main:inst4|autodate:b2v_inst|EO1 } { 0.0ns 1.255ns } { 0.0ns 0.319ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clock disp_data\[6\] time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_13\|cntr_e08:auto_generated\|safe_q\[1\] 32.524 ns register " "Info: tco from clock \"Clock\" to destination pin \"disp_data\[6\]\" through register \"time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_13\|cntr_e08:auto_generated\|safe_q\[1\]\" is 32.524 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 21.634 ns + Longest register " "Info: + Longest clock path from clock \"Clock\" to source register is 21.634 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns Clock 1 CLK PIN_L3 37 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L3; Fanout = 37; CLK Node = 'Clock'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { Clock } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 128 -40 128 144 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.681 ns) + CELL(0.698 ns) 3.207 ns fdiv:inst5\|f200hz 2 REG LC_X28_Y1_N8 93 " "Info: 2: + IC(1.681 ns) + CELL(0.698 ns) = 3.207 ns; Loc. = LC_X28_Y1_N8; Fanout = 93; REG Node = 'fdiv:inst5\|f200hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "2.379 ns" { Clock fdiv:inst5|f200hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/fdiv.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.076 ns) + CELL(0.698 ns) 6.981 ns fdiv:inst5\|f60hz 3 REG LC_X31_Y1_N7 1 " "Info: 3: + IC(3.076 ns) + CELL(0.698 ns) = 6.981 ns; Loc. = LC_X31_Y1_N7; Fanout = 1; REG Node = 'fdiv:inst5\|f60hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.774 ns" { fdiv:inst5|f200hz fdiv:inst5|f60hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/fdiv.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.047 ns) + CELL(0.280 ns) 8.308 ns stopwatch:inst2\|F_out~8 4 COMB LC_X32_Y5_N9 9 " "Info: 4: + IC(1.047 ns) + CELL(0.280 ns) = 8.308 ns; Loc. = LC_X32_Y5_N9; Fanout = 9; COMB Node = 'stopwatch:inst2\|F_out~8'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.327 ns" { fdiv:inst5|f60hz stopwatch:inst2|F_out~8 } "NODE_NAME" } "" } } { "stopwatch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/stopwatch.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.284 ns) + CELL(0.698 ns) 12.290 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO 5 REG LC_X33_Y9_N8 9 " "Info: 5: + IC(3.284 ns) + CELL(0.698 ns) = 12.290 ns; Loc. = LC_X33_Y9_N8; Fanout = 9; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|second_counter:b2v_inst2\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.982 ns" { stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO } "NODE_NAME" } "" } } { "second_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/second_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.273 ns) + CELL(0.698 ns) 17.261 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO 6 REG LC_X36_Y9_N0 9 " "Info: 6: + IC(4.273 ns) + CELL(0.698 ns) = 17.261 ns; Loc. = LC_X36_Y9_N0; Fanout = 9; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|minute_counter:b2v_inst1\|EO'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "4.971 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO } "NODE_NAME" } "" } } { "minute_counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/minute_counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.831 ns) + CELL(0.542 ns) 21.634 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_13\|cntr_e08:auto_generated\|safe_q\[1\] 7 REG LC_X33_Y11_N6 5 " "Info: 7: + IC(3.831 ns) + CELL(0.542 ns) = 21.634 ns; Loc. = LC_X33_Y11_N6; Fanout = 5; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_13\|cntr_e08:auto_generated\|safe_q\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "4.373 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_13|cntr_e08:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.442 ns 20.53 % " "Info: Total cell delay = 4.442 ns ( 20.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "17.192 ns 79.47 % " "Info: Total interconnect delay = 17.192 ns ( 79.47 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "21.634 ns" { Clock fdiv:inst5|f200hz fdiv:inst5|f60hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_13|cntr_e08:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "21.634 ns" { Clock Clock~out0 fdiv:inst5|f200hz fdiv:inst5|f60hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_13|cntr_e08:auto_generated|safe_q[1] } { 0.000ns 0.000ns 1.681ns 3.076ns 1.047ns 3.284ns 4.273ns 3.831ns } { 0.000ns 0.828ns 0.698ns 0.698ns 0.280ns 0.698ns 0.698ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.734 ns + Longest register pin " "Info: + Longest register to pin delay is 10.734 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_13\|cntr_e08:auto_generated\|safe_q\[1\] 1 REG LC_X33_Y11_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y11_N6; Fanout = 5; REG Node = 'time_auto_and_set:inst1\|timepiece_main:b2v_inst1\|hour_counter:b2v_inst\|lpm_counter:hour_data0_rtl_13\|cntr_e08:auto_generated\|safe_q\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_13|cntr_e08:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_e08.tdf" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/cntr_e08.tdf" 77 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.386 ns) + CELL(0.280 ns) 0.666 ns time_auto_and_set:inst1\|time_mux:b2v_inst2\|hour_0\[1\]~37 2 COMB LC_X33_Y11_N3 2 " "Info: 2: + IC(0.386 ns) + CELL(0.280 ns) = 0.666 ns; Loc. = LC_X33_Y11_N3; Fanout = 2; COMB Node = 'time_auto_and_set:inst1\|time_mux:b2v_inst2\|hour_0\[1\]~37'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "0.666 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_13|cntr_e08:auto_generated|safe_q[1] time_auto_and_set:inst1|time_mux:b2v_inst2|hour_0[1]~37 } "NODE_NAME" } "" } } { "time_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/time_mux.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.937 ns) + CELL(0.183 ns) 1.786 ns disp_data_mux:inst8\|Data~6adv_mux_opt_ptn_435 3 COMB LC_X34_Y10_N7 1 " "Info: 3: + IC(0.937 ns) + CELL(0.183 ns) = 1.786 ns; Loc. = LC_X34_Y10_N7; Fanout = 1; COMB Node = 'disp_data_mux:inst8\|Data~6adv_mux_opt_ptn_435'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.120 ns" { time_auto_and_set:inst1|time_mux:b2v_inst2|hour_0[1]~37 disp_data_mux:inst8|Data~6adv_mux_opt_ptn_435 } "NODE_NAME" } "" } } { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.959 ns) + CELL(0.075 ns) 2.820 ns disp_data_mux:inst8\|Data~6adv_mux_opt_ptn_436 4 COMB LC_X34_Y11_N5 1 " "Info: 4: + IC(0.959 ns) + CELL(0.075 ns) = 2.820 ns; Loc. = LC_X34_Y11_N5; Fanout = 1; COMB Node = 'disp_data_mux:inst8\|Data~6adv_mux_opt_ptn_436'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.034 ns" { disp_data_mux:inst8|Data~6adv_mux_opt_ptn_435 disp_data_mux:inst8|Data~6adv_mux_opt_ptn_436 } "NODE_NAME" } "" } } { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.119 ns) + CELL(0.366 ns) 4.305 ns disp_data_mux:inst8\|Data~409 5 COMB LC_X35_Y8_N6 1 " "Info: 5: + IC(1.119 ns) + CELL(0.366 ns) = 4.305 ns; Loc. = LC_X35_Y8_N6; Fanout = 1; COMB Node = 'disp_data_mux:inst8\|Data~409'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.485 ns" { disp_data_mux:inst8|Data~6adv_mux_opt_ptn_436 disp_data_mux:inst8|Data~409 } "NODE_NAME" } "" } } { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.342 ns) + CELL(0.280 ns) 4.927 ns disp_data_mux:inst8\|Data~410 6 COMB LC_X35_Y8_N3 2 " "Info: 6: + IC(0.342 ns) + CELL(0.280 ns) = 4.927 ns; Loc. = LC_X35_Y8_N3; Fanout = 2; COMB Node = 'disp_data_mux:inst8\|Data~410'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "0.622 ns" { disp_data_mux:inst8|Data~409 disp_data_mux:inst8|Data~410 } "NODE_NAME" } "" } } { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.537 ns) 6.464 ns disp_data_mux:inst8\|Data\[1\] 7 COMB LOOP LC_X36_Y1_N9 8 " "Info: 7: + IC(0.000 ns) + CELL(1.537 ns) = 6.464 ns; Loc. = LC_X36_Y1_N9; Fanout = 8; COMB LOOP Node = 'disp_data_mux:inst8\|Data\[1\]'" { { "Info" "ITDB_PART_OF_SCC" "disp_data_mux:inst8\|Data\[1\] LC_X36_Y1_N9 " "Info: Loc. = LC_X36_Y1_N9; Node \"disp_data_mux:inst8\|Data\[1\]\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { disp_data_mux:inst8|Data[1] } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "" { disp_data_mux:inst8|Data[1] } "NODE_NAME" } "" } } { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "1.537 ns" { disp_data_mux:inst8|Data~410 disp_data_mux:inst8|Data[1] } "NODE_NAME" } "" } } { "disp_data_mux.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/disp_data_mux.v" 57 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.075 ns) 6.939 ns disp_data_mux:inst8\|reduce_or~38 8 COMB LC_X36_Y1_N3 1 " "Info: 8: + IC(0.400 ns) + CELL(0.075 ns) = 6.939 ns; Loc. = LC_X36_Y1_N3; Fanout = 1; COMB Node = 'disp_data_mux:inst8\|reduce_or~38'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "0.475 ns" { disp_data_mux:inst8|Data[1] disp_data_mux:inst8|reduce_or~38 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.391 ns) + CELL(2.404 ns) 10.734 ns disp_data\[6\] 9 PIN PIN_W9 0 " "Info: 9: + IC(1.391 ns) + CELL(2.404 ns) = 10.734 ns; Loc. = PIN_W9; Fanout = 0; PIN Node = 'disp_data\[6\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "3.795 ns" { disp_data_mux:inst8|reduce_or~38 disp_data[6] } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/main.bdf" { { 496 1280 1456 512 "disp_data\[6..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.200 ns 48.44 % " "Info: Total cell delay = 5.200 ns ( 48.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.534 ns 51.56 % " "Info: Total interconnect delay = 5.534 ns ( 51.56 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "10.734 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_13|cntr_e08:auto_generated|safe_q[1] time_auto_and_set:inst1|time_mux:b2v_inst2|hour_0[1]~37 disp_data_mux:inst8|Data~6adv_mux_opt_ptn_435 disp_data_mux:inst8|Data~6adv_mux_opt_ptn_436 disp_data_mux:inst8|Data~409 disp_data_mux:inst8|Data~410 disp_data_mux:inst8|Data[1] disp_data_mux:inst8|reduce_or~38 disp_data[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "10.734 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_13|cntr_e08:auto_generated|safe_q[1] time_auto_and_set:inst1|time_mux:b2v_inst2|hour_0[1]~37 disp_data_mux:inst8|Data~6adv_mux_opt_ptn_435 disp_data_mux:inst8|Data~6adv_mux_opt_ptn_436 disp_data_mux:inst8|Data~409 disp_data_mux:inst8|Data~410 disp_data_mux:inst8|Data[1] disp_data_mux:inst8|reduce_or~38 disp_data[6] } { 0.000ns 0.386ns 0.937ns 0.959ns 1.119ns 0.342ns 0.000ns 0.400ns 1.391ns } { 0.000ns 0.280ns 0.183ns 0.075ns 0.366ns 0.280ns 1.537ns 0.075ns 2.404ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "21.634 ns" { Clock fdiv:inst5|f200hz fdiv:inst5|f60hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_13|cntr_e08:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "21.634 ns" { Clock Clock~out0 fdiv:inst5|f200hz fdiv:inst5|f60hz stopwatch:inst2|F_out~8 time_auto_and_set:inst1|timepiece_main:b2v_inst1|second_counter:b2v_inst2|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|minute_counter:b2v_inst1|EO time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_13|cntr_e08:auto_generated|safe_q[1] } { 0.000ns 0.000ns 1.681ns 3.076ns 1.047ns 3.284ns 4.273ns 3.831ns } { 0.000ns 0.828ns 0.698ns 0.698ns 0.280ns 0.698ns 0.698ns 0.542ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/main/" "" "10.734 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_13|cntr_e08:auto_generated|safe_q[1] time_auto_and_set:inst1|time_mux:b2v_inst2|hour_0[1]~37 disp_data_mux:inst8|Data~6adv_mux_opt_ptn_435 disp_data_mux:inst8|Data~6adv_mux_opt_ptn_436 disp_data_mux:inst8|Data~409 disp_data_mux:inst8|Data~410 disp_data_mux:inst8|Data[1] disp_data_mux:inst8|reduce_or~38 disp_data[6] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "10.734 ns" { time_auto_and_set:inst1|timepiece_main:b2v_inst1|hour_counter:b2v_inst|lpm_counter:hour_data0_rtl_13|cntr_e08:auto_generated|safe_q[1] time_auto_and_set:inst1|time_mux:b2v_inst2|hour_0[1]~37 disp_data_mux:inst8|Data~6adv_mux_opt_ptn_435 disp_data_mux:inst8|Data~6adv_mux_opt_ptn_436 disp_data_mux:inst8|Data~409 disp_data_mux:inst8|Data~410 disp_data_mux:inst8|Data[1] disp_data_mux:inst8|reduce_or~38 disp_data[6] } { 0.000ns 0.386ns 0.937ns 0.959ns 1.119ns 0.342ns 0.000ns 0.400ns 1.391ns } { 0.000ns 0.280ns 0.183ns 0.075ns 0.366ns 0.280ns 1.537ns 0.075ns 2.404ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 19 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 15 23:19:24 2006 " "Info: Processing ended: Sat Jul 15 23:19:24 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}
