{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Aug 04 19:13:02 2006 " "Info: Processing started: Fri Aug 04 19:13:02 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --import_settings_files=on --export_settings_files=off DC_Motor_Main -c DC_Motor_Main " "Info: Command: quartus_sim --import_settings_files=on --export_settings_files=off DC_Motor_Main -c DC_Motor_Main" {  } {  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Current\[11\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"Current\[11\]\" in design." {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "" { Waveform "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "Current\[11\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Current\[10\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"Current\[10\]\" in design." {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "" { Waveform "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "Current\[10\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Current\[9\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"Current\[9\]\" in design." {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "" { Waveform "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "Current\[9\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Current\[8\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"Current\[8\]\" in design." {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "" { Waveform "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "Current\[8\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Current\[7\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"Current\[7\]\" in design." {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "" { Waveform "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "Current\[7\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Current\[6\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"Current\[6\]\" in design." {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "" { Waveform "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "Current\[6\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Current\[5\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"Current\[5\]\" in design." {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "" { Waveform "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "Current\[5\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Current\[4\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"Current\[4\]\" in design." {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "" { Waveform "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "Current\[4\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Current\[3\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"Current\[3\]\" in design." {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "" { Waveform "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "Current\[3\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Current\[2\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"Current\[2\]\" in design." {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "" { Waveform "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "Current\[2\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Current\[1\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"Current\[1\]\" in design." {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "" { Waveform "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "Current\[1\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "Current\[0\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"Current\[0\]\" in design." {  } { { "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "" { Waveform "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/DC_Motor_Main/DC_Motor_Main.vwf" "Current\[0\]" "0 ps" "0 ps" "" } }  } 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|DC_Motor_Main\|Current_Set\[11\] " "Warning: Can't find signal in vector source file for input pin \"\|DC_Motor_Main\|Current_Set\[11\]\"" {  } {  } 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|DC_Motor_Main\|Current_Set\[10\] " "Warning: Can't find signal in vector source file for input pin \"\|DC_Motor_Main\|Current_Set\[10\]\"" {  } {  } 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|DC_Motor_Main\|Current_Set\[9\] " "Warning: Can't find signal in vector source file for input pin \"\|DC_Motor_Main\|Current_Set\[9\]\"" {  } {  } 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|DC_Motor_Main\|Current_Set\[8\] " "Warning: Can't find signal in vector source file for input pin \"\|DC_Motor_Main\|Current_Set\[8\]\"" {  } {  } 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|DC_Motor_Main\|Current_Set\[7\] " "Warning: Can't find signal in vector source file for input pin \"\|DC_Motor_Main\|Current_Set\[7\]\"" {  } {  } 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|DC_Motor_Main\|Current_Set\[6\] " "Warning: Can't find signal in vector source file for input pin \"\|DC_Motor_Main\|Current_Set\[6\]\"" {  } {  } 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|DC_Motor_Main\|Current_Set\[5\] " "Warning: Can't find signal in vector source file for input pin \"\|DC_Motor_Main\|Current_Set\[5\]\"" {  } {  } 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|DC_Motor_Main\|Current_Set\[4\] " "Warning: Can't find signal in vector source file for input pin \"\|DC_Motor_Main\|Current_Set\[4\]\"" {  } {  } 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|DC_Motor_Main\|Current_Set\[3\] " "Warning: Can't find signal in vector source file for input pin \"\|DC_Motor_Main\|Current_Set\[3\]\"" {  } {  } 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|DC_Motor_Main\|Current_Set\[2\] " "Warning: Can't find signal in vector source file for input pin \"\|DC_Motor_Main\|Current_Set\[2\]\"" {  } {  } 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|DC_Motor_Main\|Current_Set\[1\] " "Warning: Can't find signal in vector source file for input pin \"\|DC_Motor_Main\|Current_Set\[1\]\"" {  } {  } 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|DC_Motor_Main\|Current_Set\[0\] " "Warning: Can't find signal in vector source file for input pin \"\|DC_Motor_Main\|Current_Set\[0\]\"" {  } {  } 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     34.25 % " "Info: Simulation coverage is      34.25 %" {  } {  } 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "37143 " "Info: Number of transitions in simulation is 37143" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 24 s " "Info: Quartus II Simulator was successful. 0 errors, 24 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Aug 04 19:13:06 2006 " "Info: Processing ended: Fri Aug 04 19:13:06 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}
