{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 09 02:35:02 2006 " "Info: Processing started: Wed Aug 09 02:35:02 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off FIFO_16_16 -c FIFO_16_16 " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off FIFO_16_16 -c FIFO_16_16" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FIFO_16_16.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file FIFO_16_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 FIFO_16_16 " "Info: Found entity 1: FIFO_16_16" {  } { { "FIFO_16_16.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/第2章/FIFO_16_16/FIFO_16_16.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 FIFO_16_16.v(30) " "Warning: Verilog HDL assignment warning at FIFO_16_16.v(30): truncated value with size 5 to match size of target (4)" {  } { { "FIFO_16_16.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/第2章/FIFO_16_16/FIFO_16_16.v" 30 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 FIFO_16_16.v(31) " "Warning: Verilog HDL assignment warning at FIFO_16_16.v(31): truncated value with size 6 to match size of target (4)" {  } { { "FIFO_16_16.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/第2章/FIFO_16_16/FIFO_16_16.v" 31 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 FIFO_16_16.v(35) " "Warning: Verilog HDL assignment warning at FIFO_16_16.v(35): truncated value with size 32 to match size of target (4)" {  } { { "FIFO_16_16.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/第2章/FIFO_16_16/FIFO_16_16.v" 35 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 FIFO_16_16.v(36) " "Warning: Verilog HDL assignment warning at FIFO_16_16.v(36): truncated value with size 6 to match size of target (4)" {  } { { "FIFO_16_16.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/第2章/FIFO_16_16/FIFO_16_16.v" 36 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 FIFO_16_16.v(45) " "Warning: Verilog HDL assignment warning at FIFO_16_16.v(45): truncated value with size 6 to match size of target (4)" {  } { { "FIFO_16_16.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/第2章/FIFO_16_16/FIFO_16_16.v" 45 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 FIFO_16_16.v(46) " "Warning: Verilog HDL assignment warning at FIFO_16_16.v(46): truncated value with size 6 to match size of target (4)" {  } { { "FIFO_16_16.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/第2章/FIFO_16_16/FIFO_16_16.v" 46 0 0 } }  } 0}
{ "Warning" "WOPT_RAM_FUNCTIONALITY_CHANGED_IN_ESB" "ram~3 " "Warning: Created node \"ram~3\" as a RAM by generating altdpram megafunction to implement register logic with Embedded System Block. Functionality differs from the original design." {  } { { "FIFO_16_16.v" "ram~3" { Text "E:/戴仙金/资料/Verilog书/源代码/第2章/FIFO_16_16/FIFO_16_16.v" 13 -1 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTDPRAM_INFERRED" "ram~3 16 16 " "Info: Inferred altdpram megafunction (NUMWORDS=16, WIDTH=16) from the following logic: \"ram~3\"" {  } { { "FIFO_16_16.v" "ram~3" { Text "E:/戴仙金/资料/Verilog书/源代码/第2章/FIFO_16_16/FIFO_16_16.v" 13 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus42/libraries/megafunctions/altdpram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/altdpram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altdpram " "Info: Found entity 1: altdpram" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altdpram.tdf" 170 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_ELABORATION_HEADER" "altdpram:ram_rtl_0 " "Info: Issued messages during elaboration of megafunction \"altdpram:ram_rtl_0\"" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_TOP_EMPTY_CONTENT_FILENAME" "" "Warning: Memory Initialization File or Hexadecimal (Intel-Format) File for RAM is not specified -- setting initial contents to 0" { { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[15\] " "Warning: RAM name is \"segment\[0\]\[15\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altdpram.tdf" 284 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[14\] " "Warning: RAM name is \"segment\[0\]\[14\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altdpram.tdf" 284 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[13\] " "Warning: RAM name is \"segment\[0\]\[13\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altdpram.tdf" 284 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[12\] " "Warning: RAM name is \"segment\[0\]\[12\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altdpram.tdf" 284 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[11\] " "Warning: RAM name is \"segment\[0\]\[11\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altdpram.tdf" 284 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[10\] " "Warning: RAM name is \"segment\[0\]\[10\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altdpram.tdf" 284 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[9\] " "Warning: RAM name is \"segment\[0\]\[9\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altdpram.tdf" 284 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[8\] " "Warning: RAM name is \"segment\[0\]\[8\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altdpram.tdf" 284 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[7\] " "Warning: RAM name is \"segment\[0\]\[7\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altdpram.tdf" 284 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[6\] " "Warning: RAM name is \"segment\[0\]\[6\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altdpram.tdf" 284 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[5\] " "Warning: RAM name is \"segment\[0\]\[5\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altdpram.tdf" 284 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[4\] " "Warning: RAM name is \"segment\[0\]\[4\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altdpram.tdf" 284 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[3\] " "Warning: RAM name is \"segment\[0\]\[3\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altdpram.tdf" 284 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[2\] " "Warning: RAM name is \"segment\[0\]\[2\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altdpram.tdf" 284 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[1\] " "Warning: RAM name is \"segment\[0\]\[1\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altdpram.tdf" 284 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[0\] " "Warning: RAM name is \"segment\[0\]\[0\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/altdpram.tdf" 284 14 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "162 " "Info: Implemented 162 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "20 " "Info: Implemented 20 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "19 " "Info: Implemented 19 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "107 " "Info: Implemented 107 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "16 " "Info: Implemented 16 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 24 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 09 02:35:09 2006 " "Info: Processing ended: Wed Aug 09 02:35:09 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}
