Timing Analyzer report for main
Mon Jul 17 23:30:19 2006
Version 4.2 Build 157 12/07/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'Clock'
  6. Clock Setup: 'SW2'
  7. Clock Setup: 'SW1'
  8. Clock Setup: 'SW0'
  9. Clock Setup: 'F_in'
 10. Clock Hold: 'Clock'
 11. Clock Hold: 'SW2'
 12. Clock Hold: 'SW1'
 13. tco
 14. tpd
 15. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                   ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------------------------+-------------------------------------------+------------+----------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                      ; From                                      ; To                                        ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------------------------+-------------------------------------------+------------+----------+--------------+
; Worst-case tco               ; N/A                                      ; None          ; 82.300 ns                        ; flip_latch:inst2|Q5[2]                    ; disp_data[5]                              ; Clock      ;          ; 0            ;
; Worst-case tpd               ; N/A                                      ; None          ; 21.000 ns                        ; SW0                                       ; disp_data[5]                              ;            ;          ; 0            ;
; Clock Setup: 'Clock'         ; N/A                                      ; None          ; 17.12 MHz ( period = 58.400 ns ) ; gate_control:inst3|wire_1                 ; gate_control:inst3|wire_2                 ; Clock      ; Clock    ; 0            ;
; Clock Setup: 'SW1'           ; N/A                                      ; None          ; 23.15 MHz ( period = 43.200 ns ) ; gate_control:inst3|wire_1                 ; gate_control:inst3|wire_2                 ; SW1        ; SW1      ; 0            ;
; Clock Setup: 'SW2'           ; N/A                                      ; None          ; 33.56 MHz ( period = 29.800 ns ) ; gate_control:inst3|wire_1                 ; gate_control:inst3|wire_2                 ; SW2        ; SW2      ; 0            ;
; Clock Setup: 'SW0'           ; N/A                                      ; None          ; 41.32 MHz ( period = 24.200 ns ) ; gate_control:inst3|wire_1                 ; gate_control:inst3|wire_2                 ; SW0        ; SW0      ; 0            ;
; Clock Setup: 'F_in'          ; N/A                                      ; None          ; 53.48 MHz ( period = 18.700 ns ) ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[0] ; F_in       ; F_in     ; 0            ;
; Clock Hold: 'Clock'          ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; gate_control:inst3|wire_1                 ; gate_control:inst3|wire_1                 ; Clock      ; Clock    ; 2            ;
; Clock Hold: 'SW1'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; gate_control:inst3|wire_1                 ; gate_control:inst3|wire_1                 ; SW1        ; SW1      ; 2            ;
; Clock Hold: 'SW2'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; gate_control:inst3|wire_1                 ; gate_control:inst3|wire_1                 ; SW2        ; SW2      ; 2            ;
; Total number of failed paths ;                                          ;               ;                                  ;                                           ;                                           ;            ;          ; 6            ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------------------------+-------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM7256SQC208-7    ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock           ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; SW2             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; SW1             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; SW0             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; F_in            ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Clock'                                                                                                                                                                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------+--------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                       ; To                                         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------+--------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 17.12 MHz ( period = 58.400 ns )                    ; gate_control:inst3|wire_1                  ; gate_control:inst3|wire_2                  ; Clock      ; Clock    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 34.72 MHz ( period = 28.800 ns )                    ; gate_control:inst3|wire_1                  ; gate_control:inst3|wire_1                  ; Clock      ; Clock    ; None                        ; None                      ; 5.600 ns                ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[3]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[2]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[3]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[2]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[3]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[2]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[3]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[2]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[3]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[2]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[3]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[2]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[3]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[2]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[3]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[2]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[3]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[2]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[3]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[2]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[3]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[2]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[3]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[2]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[3]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[2]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[3]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[2]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[14] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[9]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[8]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[7]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[6]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[29] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[28] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[14] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[9]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[8]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[7]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[6]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[29] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[28] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[14] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[9]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[8]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[7]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[6]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[29] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[28] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[14] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[9]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[8]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[7]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[6]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[29] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[28] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[14] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[9]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[8]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[7]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[6]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[29] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[28] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[14] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[9]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[8]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[7]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[6]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[29] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[28] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[14] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[9]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[8]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[7]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[6]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[29] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[28] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[3]  ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[2]  ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[3]  ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[2]  ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[3]  ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[2]  ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[3]  ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[2]  ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[3]  ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[2]  ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[3]  ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[2]  ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[3]  ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[2]  ; fdiv:inst1|lpm_counter:cnt3_rtl_9|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[14] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[9]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[8]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[7]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[6]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[29] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[28] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[27] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[14] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[9]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[8]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[7]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[6]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[29] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[28] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[27] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[14] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[9]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[8]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[7]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[6]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[29] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[28] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[27] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[14] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[9]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[8]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[7]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[6]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[29] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[28] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[27] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[14] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[9]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[8]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[7]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[6]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[29] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[28] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[27] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[14] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[9]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[8]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[7]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[6]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[29] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[28] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[27] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[14] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[9]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[8]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[7]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[6]  ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[29] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[28] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.51 MHz ( period = 21.500 ns )                    ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[27] ; fdiv:inst1|lpm_counter:cnt2_rtl_7|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.300 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[14] ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[9]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[8]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[7]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[6]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[3]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[2]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[29] ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[28] ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[29] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[14] ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[9]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[8]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[7]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[6]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[3]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[2]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[29] ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[28] ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[30] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[14] ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[9]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[8]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[7]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[6]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[3]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[2]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[29] ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[28] ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[0]  ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[14] ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[9]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[8]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[7]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[6]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[3]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[2]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[29] ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[28] ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[1]  ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[14] ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[9]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[8]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[7]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[6]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[3]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[2]  ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; N/A                                     ; 46.73 MHz ( period = 21.400 ns )                    ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[29] ; fdiv:inst1|lpm_counter:cnt1_rtl_6|dffs[31] ; Clock      ; Clock    ; None                        ; None                      ; 19.200 ns               ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                            ;                                            ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------+--------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'SW2'                                                                                                                                                                                           ;
+-------+----------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)             ; From                      ; To                        ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 33.56 MHz ( period = 29.800 ns ) ; gate_control:inst3|wire_1 ; gate_control:inst3|wire_2 ; SW2        ; SW2      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 68.97 MHz ( period = 14.500 ns ) ; gate_control:inst3|wire_1 ; gate_control:inst3|wire_1 ; SW2        ; SW2      ; None                        ; None                      ; 5.600 ns                ;
+-------+----------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'SW1'                                                                                                                                                                                           ;
+-------+----------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)             ; From                      ; To                        ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 23.15 MHz ( period = 43.200 ns ) ; gate_control:inst3|wire_1 ; gate_control:inst3|wire_2 ; SW1        ; SW1      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 47.17 MHz ( period = 21.200 ns ) ; gate_control:inst3|wire_1 ; gate_control:inst3|wire_1 ; SW1        ; SW1      ; None                        ; None                      ; 5.600 ns                ;
+-------+----------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'SW0'                                                                                                                                                                                           ;
+-------+----------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)             ; From                      ; To                        ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 41.32 MHz ( period = 24.200 ns ) ; gate_control:inst3|wire_1 ; gate_control:inst3|wire_2 ; SW0        ; SW0      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 85.47 MHz ( period = 11.700 ns ) ; gate_control:inst3|wire_1 ; gate_control:inst3|wire_1 ; SW0        ; SW0      ; None                        ; None                      ; 5.600 ns                ;
+-------+----------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'F_in'                                                                                                                                                                                                                                                                               ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------+-------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                      ; To                                        ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------+-------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|F_OUT                        ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[0] ; counter:inst|F_OUT                        ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; counter:inst|F_OUT                        ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; counter:inst|F_OUT                        ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|F_OUT                        ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[0] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[0] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[0] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[0] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[0] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[0] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[0] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[0] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[0] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.48 MHz ( period = 18.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.500 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[3] ; counter:inst|F_OUT                        ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|F_OUT                        ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|F_OUT                        ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; counter:inst|F_OUT                        ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; counter:inst|F_OUT                        ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; counter:inst|F_OUT                        ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; counter:inst|F_OUT                        ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[3] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[3] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[3] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[3] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; counter:inst|lpm_counter:Q5_rtl_0|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[3] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[3] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[3] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[3] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[3] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[0] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 53.76 MHz ( period = 18.600 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.400 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[3] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.300 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.300 ns               ;
; N/A                                     ; 54.05 MHz ( period = 18.500 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 16.300 ns               ;
; N/A                                     ; 67.57 MHz ( period = 14.800 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.600 ns               ;
; N/A                                     ; 67.57 MHz ( period = 14.800 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[0] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.600 ns               ;
; N/A                                     ; 67.57 MHz ( period = 14.800 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.600 ns               ;
; N/A                                     ; 67.57 MHz ( period = 14.800 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.600 ns               ;
; N/A                                     ; 67.57 MHz ( period = 14.800 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.600 ns               ;
; N/A                                     ; 67.57 MHz ( period = 14.800 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.600 ns               ;
; N/A                                     ; 67.57 MHz ( period = 14.800 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[0] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.600 ns               ;
; N/A                                     ; 67.57 MHz ( period = 14.800 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.600 ns               ;
; N/A                                     ; 67.57 MHz ( period = 14.800 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.600 ns               ;
; N/A                                     ; 67.57 MHz ( period = 14.800 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.600 ns               ;
; N/A                                     ; 67.57 MHz ( period = 14.800 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.600 ns               ;
; N/A                                     ; 67.57 MHz ( period = 14.800 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[0] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.600 ns               ;
; N/A                                     ; 67.57 MHz ( period = 14.800 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.600 ns               ;
; N/A                                     ; 67.57 MHz ( period = 14.800 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.600 ns               ;
; N/A                                     ; 67.57 MHz ( period = 14.800 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.600 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[3] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[3] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[3] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[0] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[0] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[0] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[0] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.03 MHz ( period = 14.700 ns )                    ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.500 ns               ;
; N/A                                     ; 68.49 MHz ( period = 14.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[3] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.400 ns               ;
; N/A                                     ; 68.49 MHz ( period = 14.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.400 ns               ;
; N/A                                     ; 68.49 MHz ( period = 14.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 12.400 ns               ;
; N/A                                     ; 68.49 MHz ( period = 14.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[3] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.400 ns               ;
; N/A                                     ; 68.49 MHz ( period = 14.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.400 ns               ;
; N/A                                     ; 68.49 MHz ( period = 14.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 12.400 ns               ;
; N/A                                     ; 68.49 MHz ( period = 14.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[3] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.400 ns               ;
; N/A                                     ; 68.49 MHz ( period = 14.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.400 ns               ;
; N/A                                     ; 68.49 MHz ( period = 14.600 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|lpm_counter:Q2_rtl_3|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 12.400 ns               ;
; N/A                                     ; 84.03 MHz ( period = 11.900 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 9.700 ns                ;
; N/A                                     ; 84.03 MHz ( period = 11.900 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 9.700 ns                ;
; N/A                                     ; 84.03 MHz ( period = 11.900 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[0] ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 9.700 ns                ;
; N/A                                     ; 84.75 MHz ( period = 11.800 ns )                    ; counter:inst|lpm_counter:Q3_rtl_4|dffs[3] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 9.600 ns                ;
; N/A                                     ; 84.75 MHz ( period = 11.800 ns )                    ; counter:inst|lpm_counter:Q3_rtl_4|dffs[2] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 9.600 ns                ;
; N/A                                     ; 84.75 MHz ( period = 11.800 ns )                    ; counter:inst|lpm_counter:Q3_rtl_4|dffs[1] ; counter:inst|lpm_counter:Q4_rtl_5|dffs[0] ; F_in       ; F_in     ; None                        ; None                      ; 9.600 ns                ;
; N/A                                     ; 84.75 MHz ( period = 11.800 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 9.600 ns                ;
; N/A                                     ; 84.75 MHz ( period = 11.800 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; F_in       ; F_in     ; None                        ; None                      ; 9.600 ns                ;
; N/A                                     ; 84.75 MHz ( period = 11.800 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 9.600 ns                ;
; N/A                                     ; 84.75 MHz ( period = 11.800 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[1] ; counter:inst|lpm_counter:Q1_rtl_2|dffs[3] ; F_in       ; F_in     ; None                        ; None                      ; 9.600 ns                ;
; N/A                                     ; 84.75 MHz ( period = 11.800 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[3] ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 9.600 ns                ;
; N/A                                     ; 84.75 MHz ( period = 11.800 ns )                    ; counter:inst|lpm_counter:Q0_rtl_1|dffs[2] ; counter:inst|lpm_counter:Q1_rtl_2|dffs[2] ; F_in       ; F_in     ; None                        ; None                      ; 9.600 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                           ;                                           ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------+-------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'Clock'                                                                                                                                                                                           ;
+------------------------------------------+---------------------------+---------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                            ; From                      ; To                        ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+---------------------------+---------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; gate_control:inst3|wire_1 ; gate_control:inst3|wire_1 ; Clock      ; Clock    ; None                       ; None                       ; 5.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; gate_control:inst3|wire_1 ; gate_control:inst3|wire_2 ; Clock      ; Clock    ; None                       ; None                       ; 6.000 ns                 ;
+------------------------------------------+---------------------------+---------------------------+------------+----------+----------------------------+----------------------------+--------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'SW2'                                                                                                                                                                                             ;
+------------------------------------------+---------------------------+---------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                            ; From                      ; To                        ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+---------------------------+---------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; gate_control:inst3|wire_1 ; gate_control:inst3|wire_1 ; SW2        ; SW2      ; None                       ; None                       ; 5.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; gate_control:inst3|wire_1 ; gate_control:inst3|wire_2 ; SW2        ; SW2      ; None                       ; None                       ; 6.000 ns                 ;
+------------------------------------------+---------------------------+---------------------------+------------+----------+----------------------------+----------------------------+--------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'SW1'                                                                                                                                                                                             ;
+------------------------------------------+---------------------------+---------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                            ; From                      ; To                        ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+---------------------------+---------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; gate_control:inst3|wire_1 ; gate_control:inst3|wire_1 ; SW1        ; SW1      ; None                       ; None                       ; 5.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; gate_control:inst3|wire_1 ; gate_control:inst3|wire_2 ; SW1        ; SW1      ; None                       ; None                       ; 6.000 ns                 ;
+------------------------------------------+---------------------------+---------------------------+------------+----------+----------------------------+----------------------------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                                             ;
+-----------------------------------------+-----------------------------------------------------+------------+------------------------+--------------+------------+
; Slack                                   ; Required tco                                        ; Actual tco ; From                   ; To           ; From Clock ;
+-----------------------------------------+-----------------------------------------------------+------------+------------------------+--------------+------------+
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q1[2] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q3[2] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q4[2] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q5[2] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q1[2] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q3[2] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q4[2] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q5[2] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q3[2] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q4[2] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q5[2] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q1[2] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q3[2] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q4[2] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q5[2] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q1[2] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q4[2] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q5[2] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q3[2] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q4[2] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 82.300 ns  ; flip_latch:inst2|Q5[2] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q1[0] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q1[1] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q1[3] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q3[0] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q5[0] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q5[1] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q5[3] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q1[0] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q1[1] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q1[3] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q3[0] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q5[0] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q5[1] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q5[3] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q3[0] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q5[0] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q5[1] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q5[3] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q1[0] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q1[1] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q1[3] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q3[0] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q5[0] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q5[1] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q5[3] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q1[0] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q1[1] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q1[3] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q5[0] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q5[1] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q5[3] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q3[0] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q5[0] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q5[1] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 82.200 ns  ; flip_latch:inst2|Q5[3] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 81.200 ns  ; flip_latch:inst2|Q0[2] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 81.200 ns  ; flip_latch:inst2|Q2[2] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 81.200 ns  ; flip_latch:inst2|Q0[2] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 81.200 ns  ; flip_latch:inst2|Q2[2] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 81.200 ns  ; flip_latch:inst2|Q0[2] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 81.200 ns  ; flip_latch:inst2|Q1[2] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 81.200 ns  ; flip_latch:inst2|Q2[2] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 81.200 ns  ; flip_latch:inst2|Q0[2] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 81.200 ns  ; flip_latch:inst2|Q2[2] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 81.200 ns  ; flip_latch:inst2|Q0[2] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 81.200 ns  ; flip_latch:inst2|Q2[2] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 81.200 ns  ; flip_latch:inst2|Q3[2] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 81.200 ns  ; flip_latch:inst2|Q0[2] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 81.200 ns  ; flip_latch:inst2|Q1[2] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 81.200 ns  ; flip_latch:inst2|Q2[2] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q0[0] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q0[1] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q0[3] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q2[0] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q2[1] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q2[3] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q3[1] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q3[3] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q4[0] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q4[1] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q4[3] ; disp_data[2] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q0[0] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q0[1] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q0[3] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q2[0] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q2[1] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q2[3] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q3[1] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q3[3] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q4[0] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q4[1] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q4[3] ; disp_data[3] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q0[0] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q0[1] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q0[3] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q1[0] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q1[1] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q1[3] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q2[0] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q2[1] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q2[3] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q3[1] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q3[3] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q4[0] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q4[1] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q4[3] ; disp_data[1] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q0[0] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q0[1] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q0[3] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q2[0] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q2[1] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q2[3] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q3[1] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q3[3] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q4[0] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q4[1] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q4[3] ; disp_data[6] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q0[0] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q0[1] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q0[3] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q2[0] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q2[1] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q2[3] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q3[0] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q3[1] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q3[3] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q4[0] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q4[1] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q4[3] ; disp_data[0] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q0[0] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q0[1] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q0[3] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q1[0] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q1[1] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q1[3] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q2[0] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q2[1] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q2[3] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q3[1] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q3[3] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q4[0] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q4[1] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 81.100 ns  ; flip_latch:inst2|Q4[3] ; disp_data[5] ; Clock      ;
; N/A                                     ; None                                                ; 79.500 ns  ; flip_latch:inst2|Q3[2] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 79.500 ns  ; flip_latch:inst2|Q4[2] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 79.500 ns  ; flip_latch:inst2|Q5[2] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 79.400 ns  ; flip_latch:inst2|Q3[0] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 79.400 ns  ; flip_latch:inst2|Q5[0] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 79.400 ns  ; flip_latch:inst2|Q5[1] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 79.400 ns  ; flip_latch:inst2|Q5[3] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 78.400 ns  ; flip_latch:inst2|Q0[2] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 78.400 ns  ; flip_latch:inst2|Q1[2] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 78.400 ns  ; flip_latch:inst2|Q2[2] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 78.300 ns  ; flip_latch:inst2|Q0[0] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 78.300 ns  ; flip_latch:inst2|Q0[1] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 78.300 ns  ; flip_latch:inst2|Q0[3] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 78.300 ns  ; flip_latch:inst2|Q1[0] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 78.300 ns  ; flip_latch:inst2|Q1[1] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 78.300 ns  ; flip_latch:inst2|Q1[3] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 78.300 ns  ; flip_latch:inst2|Q2[0] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 78.300 ns  ; flip_latch:inst2|Q2[1] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 78.300 ns  ; flip_latch:inst2|Q2[3] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 78.300 ns  ; flip_latch:inst2|Q3[1] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 78.300 ns  ; flip_latch:inst2|Q3[3] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 78.300 ns  ; flip_latch:inst2|Q4[0] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 78.300 ns  ; flip_latch:inst2|Q4[1] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 78.300 ns  ; flip_latch:inst2|Q4[3] ; disp_data[4] ; Clock      ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q1[2] ; disp_data[2] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q3[2] ; disp_data[2] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q4[2] ; disp_data[2] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q5[2] ; disp_data[2] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q1[2] ; disp_data[3] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q3[2] ; disp_data[3] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q4[2] ; disp_data[3] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q5[2] ; disp_data[3] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q3[2] ; disp_data[1] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q4[2] ; disp_data[1] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q5[2] ; disp_data[1] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q1[2] ; disp_data[6] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q3[2] ; disp_data[6] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q4[2] ; disp_data[6] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q5[2] ; disp_data[6] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q1[2] ; disp_data[0] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q4[2] ; disp_data[0] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q5[2] ; disp_data[0] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q3[2] ; disp_data[5] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q4[2] ; disp_data[5] ; SW1        ;
; N/A                                     ; None                                                ; 56.700 ns  ; flip_latch:inst2|Q5[2] ; disp_data[5] ; SW1        ;
; N/A                                     ; None                                                ; 56.600 ns  ; flip_latch:inst2|Q1[0] ; disp_data[2] ; SW1        ;
; N/A                                     ; None                                                ; 56.600 ns  ; flip_latch:inst2|Q1[1] ; disp_data[2] ; SW1        ;
; N/A                                     ; None                                                ; 56.600 ns  ; flip_latch:inst2|Q1[3] ; disp_data[2] ; SW1        ;
; N/A                                     ; None                                                ; 56.600 ns  ; flip_latch:inst2|Q3[0] ; disp_data[2] ; SW1        ;
; N/A                                     ; None                                                ; 56.600 ns  ; flip_latch:inst2|Q5[0] ; disp_data[2] ; SW1        ;
; N/A                                     ; None                                                ; 56.600 ns  ; flip_latch:inst2|Q5[1] ; disp_data[2] ; SW1        ;
; N/A                                     ; None                                                ; 56.600 ns  ; flip_latch:inst2|Q5[3] ; disp_data[2] ; SW1        ;
; N/A                                     ; None                                                ; 56.600 ns  ; flip_latch:inst2|Q1[0] ; disp_data[3] ; SW1        ;
; N/A                                     ; None                                                ; 56.600 ns  ; flip_latch:inst2|Q1[1] ; disp_data[3] ; SW1        ;
; N/A                                     ; None                                                ; 56.600 ns  ; flip_latch:inst2|Q1[3] ; disp_data[3] ; SW1        ;
; N/A                                     ; None                                                ; 56.600 ns  ; flip_latch:inst2|Q3[0] ; disp_data[3] ; SW1        ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;            ;                        ;              ;            ;
+-----------------------------------------+-----------------------------------------------------+------------+------------------------+--------------+------------+


+-------------------------------------------------------------------+
; tpd                                                               ;
+-------+-------------------+-----------------+------+--------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To           ;
+-------+-------------------+-----------------+------+--------------+
; N/A   ; None              ; 21.000 ns       ; SW2  ; disp_data[2] ;
; N/A   ; None              ; 21.000 ns       ; SW1  ; disp_data[2] ;
; N/A   ; None              ; 21.000 ns       ; SW0  ; disp_data[2] ;
; N/A   ; None              ; 21.000 ns       ; SW2  ; disp_data[3] ;
; N/A   ; None              ; 21.000 ns       ; SW1  ; disp_data[3] ;
; N/A   ; None              ; 21.000 ns       ; SW0  ; disp_data[3] ;
; N/A   ; None              ; 21.000 ns       ; SW2  ; disp_data[1] ;
; N/A   ; None              ; 21.000 ns       ; SW1  ; disp_data[1] ;
; N/A   ; None              ; 21.000 ns       ; SW0  ; disp_data[1] ;
; N/A   ; None              ; 21.000 ns       ; SW2  ; disp_data[6] ;
; N/A   ; None              ; 21.000 ns       ; SW1  ; disp_data[6] ;
; N/A   ; None              ; 21.000 ns       ; SW0  ; disp_data[6] ;
; N/A   ; None              ; 21.000 ns       ; SW2  ; disp_data[0] ;
; N/A   ; None              ; 21.000 ns       ; SW1  ; disp_data[0] ;
; N/A   ; None              ; 21.000 ns       ; SW0  ; disp_data[0] ;
; N/A   ; None              ; 21.000 ns       ; SW2  ; disp_data[4] ;
; N/A   ; None              ; 21.000 ns       ; SW1  ; disp_data[4] ;
; N/A   ; None              ; 21.000 ns       ; SW0  ; disp_data[4] ;
; N/A   ; None              ; 21.000 ns       ; SW2  ; disp_data[5] ;
; N/A   ; None              ; 21.000 ns       ; SW1  ; disp_data[5] ;
; N/A   ; None              ; 21.000 ns       ; SW0  ; disp_data[5] ;
; N/A   ; None              ; 18.200 ns       ; SW2  ; dp           ;
; N/A   ; None              ; 18.200 ns       ; SW1  ; dp           ;
; N/A   ; None              ; 18.200 ns       ; SW0  ; dp           ;
+-------+-------------------+-----------------+------+--------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Mon Jul 17 23:30:15 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off main -c main
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Found combinational loop of 1 nodes
    Info: Node "dispdecoder:inst5|data_out[2]~166"
Info: Found combinational loop of 1 nodes
    Info: Node "dispdecoder:inst5|data_out[3]~162"
Info: Found combinational loop of 1 nodes
    Info: Node "dispdecoder:inst5|data_out[1]~158"
Info: Found combinational loop of 1 nodes
    Info: Node "dispdecoder:inst5|data_out[6]~154"
Info: Found combinational loop of 1 nodes
    Info: Node "dispdecoder:inst5|data_out[0]~150"
Info: Found combinational loop of 1 nodes
    Info: Node "dispdecoder:inst5|data_out[4]~146"
Info: Found combinational loop of 1 nodes
    Info: Node "dispdecoder:inst5|data_out[5]~142"
Info: Found combinational loop of 1 nodes
    Info: Node "gate_control:inst3|fref~126"
Info: Found combinational loop of 1 nodes
    Info: Node "gate_control:inst3|dp_s100hz~25"
Info: Found combinational loop of 1 nodes
    Info: Node "gate_control:inst3|dp_s1hz~24"
Info: Found combinational loop of 1 nodes
    Info: Node "gate_control:inst3|dp_s10hz~40"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "Clock" is an undefined clock
    Info: Assuming node "SW2" is an undefined clock
    Info: Assuming node "SW1" is an undefined clock
    Info: Assuming node "SW0" is an undefined clock
    Info: Assuming node "F_in" is an undefined clock
Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "gate_control:inst3|wire_2" as buffer
    Info: Detected ripple clock "gate_control:inst3|wire_1" as buffer
    Info: Detected gated clock "gate_control:inst3|always0~44" as buffer
    Info: Detected gated clock "gate_control:inst3|fref~126" as buffer
    Info: Detected gated clock "gate_control:inst3|fref~114" as buffer
    Info: Detected gated clock "gate_control:inst3|fref~120" as buffer
    Info: Detected ripple clock "fdiv:inst1|f1hz" as buffer
    Info: Detected ripple clock "fdiv:inst1|f10hz" as buffer
    Info: Detected ripple clock "fdiv:inst1|f100hz" as buffer
    Info: Detected ripple clock "fdiv:inst1|f1khz" as buffer
Info: Clock "Clock" has Internal fmax of 17.12 MHz between source register "gate_control:inst3|wire_1" and destination register "gate_control:inst3|wire_2" (period= 58.4 ns)
    Info: + Longest register to register delay is 6.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
        Info: 2: + IC(3.400 ns) + CELL(2.600 ns) = 6.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3|wire_2'
        Info: Total cell delay = 2.600 ns ( 43.33 % )
        Info: Total interconnect delay = 3.400 ns ( 56.67 % )
    Info: - Smallest clock skew is -21.000 ns
        Info: + Shortest clock path from clock "Clock" to destination register is 31.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_181; Fanout = 33; CLK Node = 'Clock'
            Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 4.200 ns; Loc. = LC225; Fanout = 42; REG Node = 'fdiv:inst1|f1khz'
            Info: 3: + IC(3.300 ns) + CELL(4.000 ns) = 11.500 ns; Loc. = LC115; Fanout = 34; REG Node = 'fdiv:inst1|f100hz'
            Info: 4: + IC(3.200 ns) + CELL(3.700 ns) = 18.400 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3|fref~114'
            Info: 5: + IC(0.000 ns) + CELL(6.700 ns) = 25.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3|fref~126'
                Info: Loc. = LC205; Node "gate_control:inst3|fref~126"
            Info: 6: + IC(3.000 ns) + CELL(2.900 ns) = 31.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3|wire_2'
            Info: Total cell delay = 21.500 ns ( 69.35 % )
            Info: Total interconnect delay = 9.500 ns ( 30.65 % )
        Info: - Longest clock path from clock "Clock" to source register is 52.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_181; Fanout = 33; CLK Node = 'Clock'
            Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 4.200 ns; Loc. = LC225; Fanout = 42; REG Node = 'fdiv:inst1|f1khz'
            Info: 3: + IC(3.300 ns) + CELL(4.000 ns) = 11.500 ns; Loc. = LC115; Fanout = 34; REG Node = 'fdiv:inst1|f100hz'
            Info: 4: + IC(3.200 ns) + CELL(4.000 ns) = 18.700 ns; Loc. = LC129; Fanout = 34; REG Node = 'fdiv:inst1|f10hz'
            Info: 5: + IC(3.300 ns) + CELL(4.000 ns) = 26.000 ns; Loc. = LC145; Fanout = 1; REG Node = 'fdiv:inst1|f1hz'
            Info: 6: + IC(3.000 ns) + CELL(3.700 ns) = 32.700 ns; Loc. = LC195; Fanout = 1; COMB Node = 'gate_control:inst3|fref~120'
            Info: 7: + IC(3.000 ns) + CELL(3.700 ns) = 39.400 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3|fref~114'
            Info: 8: + IC(0.000 ns) + CELL(6.700 ns) = 46.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3|fref~126'
                Info: Loc. = LC205; Node "gate_control:inst3|fref~126"
            Info: 9: + IC(3.000 ns) + CELL(2.900 ns) = 52.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
            Info: Total cell delay = 33.200 ns ( 63.85 % )
            Info: Total interconnect delay = 18.800 ns ( 36.15 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 1.100 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: Clock "SW2" has Internal fmax of 33.56 MHz between source register "gate_control:inst3|wire_1" and destination register "gate_control:inst3|wire_2" (period= 29.8 ns)
    Info: + Longest register to register delay is 6.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
        Info: 2: + IC(3.400 ns) + CELL(2.600 ns) = 6.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3|wire_2'
        Info: Total cell delay = 2.600 ns ( 43.33 % )
        Info: Total interconnect delay = 3.400 ns ( 56.67 % )
    Info: - Smallest clock skew is -6.700 ns
        Info: + Shortest clock path from clock "SW2" to destination register is 13.000 ns
            Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_129; Fanout = 21; CLK Node = 'SW2'
            Info: 2: + IC(0.000 ns) + CELL(6.800 ns) = 7.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3|fref~126'
                Info: Loc. = LC205; Node "gate_control:inst3|fref~126"
            Info: 3: + IC(3.000 ns) + CELL(2.900 ns) = 13.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3|wire_2'
            Info: Total cell delay = 10.000 ns ( 76.92 % )
            Info: Total interconnect delay = 3.000 ns ( 23.08 % )
        Info: - Longest clock path from clock "SW2" to source register is 19.700 ns
            Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_129; Fanout = 21; CLK Node = 'SW2'
            Info: 2: + IC(3.100 ns) + CELL(3.700 ns) = 7.100 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3|fref~114'
            Info: 3: + IC(0.000 ns) + CELL(6.700 ns) = 13.800 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3|fref~126'
                Info: Loc. = LC205; Node "gate_control:inst3|fref~126"
            Info: 4: + IC(3.000 ns) + CELL(2.900 ns) = 19.700 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
            Info: Total cell delay = 13.600 ns ( 69.04 % )
            Info: Total interconnect delay = 6.100 ns ( 30.96 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 1.100 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: Clock "SW1" has Internal fmax of 23.15 MHz between source register "gate_control:inst3|wire_1" and destination register "gate_control:inst3|wire_2" (period= 43.2 ns)
    Info: + Longest register to register delay is 6.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
        Info: 2: + IC(3.400 ns) + CELL(2.600 ns) = 6.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3|wire_2'
        Info: Total cell delay = 2.600 ns ( 43.33 % )
        Info: Total interconnect delay = 3.400 ns ( 56.67 % )
    Info: - Smallest clock skew is -13.400 ns
        Info: + Shortest clock path from clock "SW1" to destination register is 13.000 ns
            Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_145; Fanout = 18; CLK Node = 'SW1'
            Info: 2: + IC(0.000 ns) + CELL(6.800 ns) = 7.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3|fref~126'
                Info: Loc. = LC205; Node "gate_control:inst3|fref~126"
            Info: 3: + IC(3.000 ns) + CELL(2.900 ns) = 13.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3|wire_2'
            Info: Total cell delay = 10.000 ns ( 76.92 % )
            Info: Total interconnect delay = 3.000 ns ( 23.08 % )
        Info: - Longest clock path from clock "SW1" to source register is 26.400 ns
            Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_145; Fanout = 18; CLK Node = 'SW1'
            Info: 2: + IC(3.100 ns) + CELL(3.700 ns) = 7.100 ns; Loc. = LC195; Fanout = 1; COMB Node = 'gate_control:inst3|fref~120'
            Info: 3: + IC(3.000 ns) + CELL(3.700 ns) = 13.800 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3|fref~114'
            Info: 4: + IC(0.000 ns) + CELL(6.700 ns) = 20.500 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3|fref~126'
                Info: Loc. = LC205; Node "gate_control:inst3|fref~126"
            Info: 5: + IC(3.000 ns) + CELL(2.900 ns) = 26.400 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
            Info: Total cell delay = 17.300 ns ( 65.53 % )
            Info: Total interconnect delay = 9.100 ns ( 34.47 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 1.100 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: Clock "SW0" has Internal fmax of 41.32 MHz between source register "gate_control:inst3|wire_1" and destination register "gate_control:inst3|wire_2" (period= 24.2 ns)
    Info: + Longest register to register delay is 6.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
        Info: 2: + IC(3.400 ns) + CELL(2.600 ns) = 6.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3|wire_2'
        Info: Total cell delay = 2.600 ns ( 43.33 % )
        Info: Total interconnect delay = 3.400 ns ( 56.67 % )
    Info: - Smallest clock skew is -3.900 ns
        Info: + Shortest clock path from clock "SW0" to destination register is 13.000 ns
            Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_135; Fanout = 12; CLK Node = 'SW0'
            Info: 2: + IC(0.000 ns) + CELL(6.800 ns) = 7.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3|fref~126'
                Info: Loc. = LC205; Node "gate_control:inst3|fref~126"
            Info: 3: + IC(3.000 ns) + CELL(2.900 ns) = 13.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3|wire_2'
            Info: Total cell delay = 10.000 ns ( 76.92 % )
            Info: Total interconnect delay = 3.000 ns ( 23.08 % )
        Info: - Longest clock path from clock "SW0" to source register is 16.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_135; Fanout = 12; CLK Node = 'SW0'
            Info: 2: + IC(3.100 ns) + CELL(3.900 ns) = 7.300 ns; Loc. = SEXP193; Fanout = 2; COMB Node = 'gate_control:inst3|always0~44'
            Info: 3: + IC(0.000 ns) + CELL(3.700 ns) = 11.000 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3|fref~126'
                Info: Loc. = LC205; Node "gate_control:inst3|fref~126"
            Info: 4: + IC(3.000 ns) + CELL(2.900 ns) = 16.900 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
            Info: Total cell delay = 10.800 ns ( 63.91 % )
            Info: Total interconnect delay = 6.100 ns ( 36.09 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 1.100 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: Clock "F_in" has Internal fmax of 53.48 MHz between source register "counter:inst|lpm_counter:Q0_rtl_1|dffs[0]" and destination register "counter:inst|F_OUT" (period= 18.7 ns)
    Info: + Longest register to register delay is 16.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC211; Fanout = 16; REG Node = 'counter:inst|lpm_counter:Q0_rtl_1|dffs[0]'
        Info: 2: + IC(3.200 ns) + CELL(3.700 ns) = 6.900 ns; Loc. = LC103; Fanout = 19; COMB Node = 'counter:inst|F_OUT~201'
        Info: 3: + IC(3.100 ns) + CELL(3.900 ns) = 13.900 ns; Loc. = SEXP95; Fanout = 1; COMB Node = 'counter:inst|F_OUT~204'
        Info: 4: + IC(0.000 ns) + CELL(2.600 ns) = 16.500 ns; Loc. = LC81; Fanout = 5; REG Node = 'counter:inst|F_OUT'
        Info: Total cell delay = 10.200 ns ( 61.82 % )
        Info: Total interconnect delay = 6.300 ns ( 38.18 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "F_in" to destination register is 3.100 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_184; Fanout = 25; CLK Node = 'F_in'
            Info: 2: + IC(0.000 ns) + CELL(0.300 ns) = 3.100 ns; Loc. = LC81; Fanout = 5; REG Node = 'counter:inst|F_OUT'
            Info: Total cell delay = 3.100 ns ( 100.00 % )
        Info: - Longest clock path from clock "F_in" to source register is 3.100 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_184; Fanout = 25; CLK Node = 'F_in'
            Info: 2: + IC(0.000 ns) + CELL(0.300 ns) = 3.100 ns; Loc. = LC211; Fanout = 16; REG Node = 'counter:inst|lpm_counter:Q0_rtl_1|dffs[0]'
            Info: Total cell delay = 3.100 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 1.100 ns
Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock "Clock" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "gate_control:inst3|wire_1" and destination pin or register "gate_control:inst3|wire_1" for clock "Clock" (Hold time is 15.9 ns)
    Info: + Largest clock skew is 21.000 ns
        Info: + Longest clock path from clock "Clock" to destination register is 52.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_181; Fanout = 33; CLK Node = 'Clock'
            Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 4.200 ns; Loc. = LC225; Fanout = 42; REG Node = 'fdiv:inst1|f1khz'
            Info: 3: + IC(3.300 ns) + CELL(4.000 ns) = 11.500 ns; Loc. = LC115; Fanout = 34; REG Node = 'fdiv:inst1|f100hz'
            Info: 4: + IC(3.200 ns) + CELL(4.000 ns) = 18.700 ns; Loc. = LC129; Fanout = 34; REG Node = 'fdiv:inst1|f10hz'
            Info: 5: + IC(3.300 ns) + CELL(4.000 ns) = 26.000 ns; Loc. = LC145; Fanout = 1; REG Node = 'fdiv:inst1|f1hz'
            Info: 6: + IC(3.000 ns) + CELL(3.700 ns) = 32.700 ns; Loc. = LC195; Fanout = 1; COMB Node = 'gate_control:inst3|fref~120'
            Info: 7: + IC(3.000 ns) + CELL(3.700 ns) = 39.400 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3|fref~114'
            Info: 8: + IC(0.000 ns) + CELL(6.700 ns) = 46.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3|fref~126'
                Info: Loc. = LC205; Node "gate_control:inst3|fref~126"
            Info: 9: + IC(3.000 ns) + CELL(2.900 ns) = 52.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
            Info: Total cell delay = 33.200 ns ( 63.85 % )
            Info: Total interconnect delay = 18.800 ns ( 36.15 % )
        Info: - Shortest clock path from clock "Clock" to source register is 31.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_181; Fanout = 33; CLK Node = 'Clock'
            Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 4.200 ns; Loc. = LC225; Fanout = 42; REG Node = 'fdiv:inst1|f1khz'
            Info: 3: + IC(3.300 ns) + CELL(4.000 ns) = 11.500 ns; Loc. = LC115; Fanout = 34; REG Node = 'fdiv:inst1|f100hz'
            Info: 4: + IC(3.200 ns) + CELL(3.700 ns) = 18.400 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3|fref~114'
            Info: 5: + IC(0.000 ns) + CELL(6.700 ns) = 25.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3|fref~126'
                Info: Loc. = LC205; Node "gate_control:inst3|fref~126"
            Info: 6: + IC(3.000 ns) + CELL(2.900 ns) = 31.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
            Info: Total cell delay = 21.500 ns ( 69.35 % )
            Info: Total interconnect delay = 9.500 ns ( 30.65 % )
    Info: - Micro clock to output delay of source is 1.100 ns
    Info: - Shortest register to register delay is 5.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
        Info: 2: + IC(0.000 ns) + CELL(5.600 ns) = 5.600 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
        Info: Total cell delay = 5.600 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.600 ns
Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock "SW2" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "gate_control:inst3|wire_1" and destination pin or register "gate_control:inst3|wire_1" for clock "SW2" (Hold time is 1.6 ns)
    Info: + Largest clock skew is 6.700 ns
        Info: + Longest clock path from clock "SW2" to destination register is 19.700 ns
            Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_129; Fanout = 21; CLK Node = 'SW2'
            Info: 2: + IC(3.100 ns) + CELL(3.700 ns) = 7.100 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3|fref~114'
            Info: 3: + IC(0.000 ns) + CELL(6.700 ns) = 13.800 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3|fref~126'
                Info: Loc. = LC205; Node "gate_control:inst3|fref~126"
            Info: 4: + IC(3.000 ns) + CELL(2.900 ns) = 19.700 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
            Info: Total cell delay = 13.600 ns ( 69.04 % )
            Info: Total interconnect delay = 6.100 ns ( 30.96 % )
        Info: - Shortest clock path from clock "SW2" to source register is 13.000 ns
            Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_129; Fanout = 21; CLK Node = 'SW2'
            Info: 2: + IC(0.000 ns) + CELL(6.800 ns) = 7.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3|fref~126'
                Info: Loc. = LC205; Node "gate_control:inst3|fref~126"
            Info: 3: + IC(3.000 ns) + CELL(2.900 ns) = 13.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
            Info: Total cell delay = 10.000 ns ( 76.92 % )
            Info: Total interconnect delay = 3.000 ns ( 23.08 % )
    Info: - Micro clock to output delay of source is 1.100 ns
    Info: - Shortest register to register delay is 5.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
        Info: 2: + IC(0.000 ns) + CELL(5.600 ns) = 5.600 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
        Info: Total cell delay = 5.600 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.600 ns
Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock "SW1" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "gate_control:inst3|wire_1" and destination pin or register "gate_control:inst3|wire_1" for clock "SW1" (Hold time is 8.3 ns)
    Info: + Largest clock skew is 13.400 ns
        Info: + Longest clock path from clock "SW1" to destination register is 26.400 ns
            Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_145; Fanout = 18; CLK Node = 'SW1'
            Info: 2: + IC(3.100 ns) + CELL(3.700 ns) = 7.100 ns; Loc. = LC195; Fanout = 1; COMB Node = 'gate_control:inst3|fref~120'
            Info: 3: + IC(3.000 ns) + CELL(3.700 ns) = 13.800 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3|fref~114'
            Info: 4: + IC(0.000 ns) + CELL(6.700 ns) = 20.500 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3|fref~126'
                Info: Loc. = LC205; Node "gate_control:inst3|fref~126"
            Info: 5: + IC(3.000 ns) + CELL(2.900 ns) = 26.400 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
            Info: Total cell delay = 17.300 ns ( 65.53 % )
            Info: Total interconnect delay = 9.100 ns ( 34.47 % )
        Info: - Shortest clock path from clock "SW1" to source register is 13.000 ns
            Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_145; Fanout = 18; CLK Node = 'SW1'
            Info: 2: + IC(0.000 ns) + CELL(6.800 ns) = 7.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3|fref~126'
                Info: Loc. = LC205; Node "gate_control:inst3|fref~126"
            Info: 3: + IC(3.000 ns) + CELL(2.900 ns) = 13.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
            Info: Total cell delay = 10.000 ns ( 76.92 % )
            Info: Total interconnect delay = 3.000 ns ( 23.08 % )
    Info: - Micro clock to output delay of source is 1.100 ns
    Info: - Shortest register to register delay is 5.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
        Info: 2: + IC(0.000 ns) + CELL(5.600 ns) = 5.600 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
        Info: Total cell delay = 5.600 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.600 ns
Info: tco from clock "Clock" to destination pin "disp_data[2]" through register "flip_latch:inst2|Q1[2]" is 82.300 ns
    Info: + Longest clock path from clock "Clock" to source register is 59.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_181; Fanout = 33; CLK Node = 'Clock'
        Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 4.200 ns; Loc. = LC225; Fanout = 42; REG Node = 'fdiv:inst1|f1khz'
        Info: 3: + IC(3.300 ns) + CELL(4.000 ns) = 11.500 ns; Loc. = LC115; Fanout = 34; REG Node = 'fdiv:inst1|f100hz'
        Info: 4: + IC(3.200 ns) + CELL(4.000 ns) = 18.700 ns; Loc. = LC129; Fanout = 34; REG Node = 'fdiv:inst1|f10hz'
        Info: 5: + IC(3.300 ns) + CELL(4.000 ns) = 26.000 ns; Loc. = LC145; Fanout = 1; REG Node = 'fdiv:inst1|f1hz'
        Info: 6: + IC(3.000 ns) + CELL(3.700 ns) = 32.700 ns; Loc. = LC195; Fanout = 1; COMB Node = 'gate_control:inst3|fref~120'
        Info: 7: + IC(3.000 ns) + CELL(3.700 ns) = 39.400 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3|fref~114'
        Info: 8: + IC(0.000 ns) + CELL(6.700 ns) = 46.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3|fref~126'
            Info: Loc. = LC205; Node "gate_control:inst3|fref~126"
        Info: 9: + IC(3.000 ns) + CELL(4.000 ns) = 53.100 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3|wire_1'
        Info: 10: + IC(3.400 ns) + CELL(2.900 ns) = 59.400 ns; Loc. = LC227; Fanout = 6; REG Node = 'flip_latch:inst2|Q1[2]'
        Info: Total cell delay = 37.200 ns ( 62.63 % )
        Info: Total interconnect delay = 22.200 ns ( 37.37 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 21.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC227; Fanout = 6; REG Node = 'flip_latch:inst2|Q1[2]'
        Info: 2: + IC(3.100 ns) + CELL(2.600 ns) = 5.700 ns; Loc. = LC79; Fanout = 1; COMB Node = 'dispdecoder:inst5|reduce_or~1916'
        Info: 3: + IC(0.000 ns) + CELL(2.200 ns) = 7.900 ns; Loc. = LC80; Fanout = 6; COMB Node = 'dispdecoder:inst5|reduce_or~1859'
        Info: 4: + IC(3.000 ns) + CELL(3.700 ns) = 14.600 ns; Loc. = LC250; Fanout = 9; COMB Node = 'dispdecoder:inst5|reduce_or~1835'
        Info: 5: + IC(0.000 ns) + CELL(6.700 ns) = 21.300 ns; Loc. = LC246; Fanout = 3; COMB LOOP Node = 'dispdecoder:inst5|data_out[2]~166'
            Info: Loc. = LC246; Node "dispdecoder:inst5|data_out[2]~166"
        Info: 6: + IC(0.000 ns) + CELL(0.500 ns) = 21.800 ns; Loc. = PIN_61; Fanout = 0; PIN Node = 'disp_data[2]'
        Info: Total cell delay = 15.700 ns ( 72.02 % )
        Info: Total interconnect delay = 6.100 ns ( 27.98 % )
Info: Longest tpd from source pin "SW2" to destination pin "disp_data[2]" is 21.000 ns
    Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_129; Fanout = 21; CLK Node = 'SW2'
    Info: 2: + IC(0.000 ns) + CELL(6.800 ns) = 7.100 ns; Loc. = LC92; Fanout = 6; COMB LOOP Node = 'gate_control:inst3|dp_s100hz~25'
        Info: Loc. = LC92; Node "gate_control:inst3|dp_s100hz~25"
    Info: 3: + IC(3.000 ns) + CELL(3.700 ns) = 13.800 ns; Loc. = LC85; Fanout = 21; COMB Node = 'dispdecoder:inst5|hide~386'
    Info: 4: + IC(0.000 ns) + CELL(6.700 ns) = 20.500 ns; Loc. = LC246; Fanout = 3; COMB LOOP Node = 'dispdecoder:inst5|data_out[2]~166'
        Info: Loc. = LC246; Node "dispdecoder:inst5|data_out[2]~166"
    Info: 5: + IC(0.000 ns) + CELL(0.500 ns) = 21.000 ns; Loc. = PIN_61; Fanout = 0; PIN Node = 'disp_data[2]'
    Info: Total cell delay = 18.000 ns ( 85.71 % )
    Info: Total interconnect delay = 3.000 ns ( 14.29 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 5 warnings
    Info: Processing ended: Mon Jul 17 23:30:19 2006
    Info: Elapsed time: 00:00:05


