Timing Analyzer report for main
Wed Aug 02 16:41:50 2006
Version 4.2 Build 157 12/07/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'Reset'
  6. Clock Setup: 'Clock_8MHz'
  7. Clock Hold: 'Reset'
  8. Clock Hold: 'Clock_8MHz'
  9. tsu
 10. tco
 11. tpd
 12. th
 13. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                             ;
+------------------------------+------------------------------------------+---------------+----------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+------------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                      ; From                                                                                  ; To                                                                                    ; From Clock ; To Clock   ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+------------+--------------+
; Worst-case tsu               ; N/A                                      ; None          ; 10.500 ns                        ; Step_Sum[3]                                                                           ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ;            ; Reset      ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 24.700 ns                        ; sum_control:inst5|out_control                                                         ; Pulse_Wave                                                                            ; Clock_8MHz ;            ; 0            ;
; Worst-case tpd               ; N/A                                      ; None          ; 10.800 ns                        ; Reset                                                                                 ; Pulse_Wave                                                                            ;            ;            ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 16.600 ns                        ; Reset                                                                                 ; sum_control:inst5|out_control                                                         ;            ; Clock_8MHz ; 0            ;
; Clock Setup: 'Clock_8MHz'    ; N/A                                      ; None          ; 62.50 MHz ( period = 16.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; 0            ;
; Clock Setup: 'Reset'         ; N/A                                      ; None          ; 87.72 MHz ( period = 11.400 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset      ; 0            ;
; Clock Hold: 'Clock_8MHz'     ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Clock_8MHz ; Clock_8MHz ; 601          ;
; Clock Hold: 'Reset'          ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset      ; 376          ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                                                       ;                                                                                       ;            ;            ; 977          ;
+------------------------------+------------------------------------------+---------------+----------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1K10TC100-1      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Reset           ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; Clock_8MHz      ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Reset'                                                                                                                                                                                                                                                                                                                                                                      ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                  ; To                                                                                    ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 87.72 MHz ( period = 11.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 87.72 MHz ( period = 11.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset      ; Reset    ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 87.72 MHz ( period = 11.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset      ; Reset    ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 87.72 MHz ( period = 11.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 87.72 MHz ( period = 11.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 87.72 MHz ( period = 11.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 87.72 MHz ( period = 11.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 87.72 MHz ( period = 11.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 88.50 MHz ( period = 11.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset      ; Reset    ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 88.50 MHz ( period = 11.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset      ; Reset    ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 88.50 MHz ( period = 11.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset      ; Reset    ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 88.50 MHz ( period = 11.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset      ; Reset    ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 88.50 MHz ( period = 11.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset      ; Reset    ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 88.50 MHz ( period = 11.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset      ; Reset    ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 88.50 MHz ( period = 11.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset      ; Reset    ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 88.50 MHz ( period = 11.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset      ; Reset    ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 88.50 MHz ( period = 11.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset      ; Reset    ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 88.50 MHz ( period = 11.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset      ; Reset    ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 88.50 MHz ( period = 11.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset      ; Reset    ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 88.50 MHz ( period = 11.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset      ; Reset    ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 88.50 MHz ( period = 11.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset      ; Reset    ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 88.50 MHz ( period = 11.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset      ; Reset    ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 88.50 MHz ( period = 11.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset      ; Reset    ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 88.50 MHz ( period = 11.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset      ; Reset    ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 89.29 MHz ( period = 11.200 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset      ; Reset    ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 90.91 MHz ( period = 11.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset      ; Reset    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 92.59 MHz ( period = 10.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset      ; Reset    ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 92.59 MHz ( period = 10.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset      ; Reset    ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 92.59 MHz ( period = 10.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset      ; Reset    ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 92.59 MHz ( period = 10.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset      ; Reset    ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 92.59 MHz ( period = 10.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset      ; Reset    ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 92.59 MHz ( period = 10.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset      ; Reset    ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 92.59 MHz ( period = 10.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset      ; Reset    ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 92.59 MHz ( period = 10.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset      ; Reset    ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 92.59 MHz ( period = 10.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset      ; Reset    ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 92.59 MHz ( period = 10.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset      ; Reset    ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 92.59 MHz ( period = 10.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset      ; Reset    ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 92.59 MHz ( period = 10.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset      ; Reset    ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 92.59 MHz ( period = 10.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset      ; Reset    ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 92.59 MHz ( period = 10.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset      ; Reset    ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 92.59 MHz ( period = 10.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset      ; Reset    ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 92.59 MHz ( period = 10.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset      ; Reset    ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 93.46 MHz ( period = 10.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                        ; None                      ; 5.700 ns                ;
; N/A                                     ; 93.46 MHz ( period = 10.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                        ; None                      ; 5.700 ns                ;
; N/A                                     ; 93.46 MHz ( period = 10.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                        ; None                      ; 5.700 ns                ;
; N/A                                     ; 93.46 MHz ( period = 10.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                        ; None                      ; 5.700 ns                ;
; N/A                                     ; 93.46 MHz ( period = 10.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                        ; None                      ; 5.700 ns                ;
; N/A                                     ; 93.46 MHz ( period = 10.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                        ; None                      ; 5.700 ns                ;
; N/A                                     ; 93.46 MHz ( period = 10.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                        ; None                      ; 5.700 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                       ;                                                                                       ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Clock_8MHz'                                                                                                                                                                                                                                                                                                                                                                   ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                  ; To                                                                                    ; From Clock ; To Clock   ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+------------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 62.50 MHz ( period = 16.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 62.50 MHz ( period = 16.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 62.50 MHz ( period = 16.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 62.50 MHz ( period = 16.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 62.50 MHz ( period = 16.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 62.50 MHz ( period = 16.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 62.50 MHz ( period = 16.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 62.50 MHz ( period = 16.000 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.400 ns                ;
; N/A                                     ; 62.89 MHz ( period = 15.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 62.89 MHz ( period = 15.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 62.89 MHz ( period = 15.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 62.89 MHz ( period = 15.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 62.89 MHz ( period = 15.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 62.89 MHz ( period = 15.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 62.89 MHz ( period = 15.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 62.89 MHz ( period = 15.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 62.89 MHz ( period = 15.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 62.89 MHz ( period = 15.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 62.89 MHz ( period = 15.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 62.89 MHz ( period = 15.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 62.89 MHz ( period = 15.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 62.89 MHz ( period = 15.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 62.89 MHz ( period = 15.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 62.89 MHz ( period = 15.900 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.300 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.29 MHz ( period = 15.800 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.200 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 63.69 MHz ( period = 15.700 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.100 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.10 MHz ( period = 15.600 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.52 MHz ( period = 15.500 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|out_control                                                         ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.900 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 64.94 MHz ( period = 15.400 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.800 ns                ;
; N/A                                     ; 65.36 MHz ( period = 15.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.700 ns                ;
; N/A                                     ; 65.36 MHz ( period = 15.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.700 ns                ;
; N/A                                     ; 65.36 MHz ( period = 15.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.700 ns                ;
; N/A                                     ; 65.36 MHz ( period = 15.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.700 ns                ;
; N/A                                     ; 65.36 MHz ( period = 15.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.700 ns                ;
; N/A                                     ; 65.36 MHz ( period = 15.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|out_control                                                         ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.700 ns                ;
; N/A                                     ; 65.36 MHz ( period = 15.300 ns )                    ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|out_control                                                         ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 5.700 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                       ;                                                                                       ;            ;            ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+------------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'Reset'                                                                                                                                                                                                                                                                                                                   ;
+------------------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                            ; From                                                                                  ; To                                                                                    ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset      ; Reset    ; None                       ; None                       ; 1.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                       ; None                       ; 1.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset      ; Reset    ; None                       ; None                       ; 1.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset      ; Reset    ; None                       ; None                       ; 1.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset      ; Reset    ; None                       ; None                       ; 1.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset      ; Reset    ; None                       ; None                       ; 1.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset      ; Reset    ; None                       ; None                       ; 1.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset      ; Reset    ; None                       ; None                       ; 1.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset      ; Reset    ; None                       ; None                       ; 1.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset      ; Reset    ; None                       ; None                       ; 1.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset      ; Reset    ; None                       ; None                       ; 1.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset      ; Reset    ; None                       ; None                       ; 1.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                       ; None                       ; 1.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                       ; None                       ; 1.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                       ; None                       ; 1.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                       ; None                       ; 1.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset      ; Reset    ; None                       ; None                       ; 1.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset      ; Reset    ; None                       ; None                       ; 1.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                       ; None                       ; 1.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset      ; Reset    ; None                       ; None                       ; 1.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset      ; Reset    ; None                       ; None                       ; 1.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset      ; Reset    ; None                       ; None                       ; 1.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset      ; Reset    ; None                       ; None                       ; 1.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset      ; Reset    ; None                       ; None                       ; 1.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset      ; Reset    ; None                       ; None                       ; 1.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                       ; None                       ; 1.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                       ; None                       ; 1.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                       ; None                       ; 1.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                       ; None                       ; 1.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset      ; Reset    ; None                       ; None                       ; 1.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                       ; None                       ; 1.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset      ; Reset    ; None                       ; None                       ; 1.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset      ; Reset    ; None                       ; None                       ; 1.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset      ; Reset    ; None                       ; None                       ; 1.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset      ; Reset    ; None                       ; None                       ; 1.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset      ; Reset    ; None                       ; None                       ; 1.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                       ; None                       ; 1.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                       ; None                       ; 1.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                       ; None                       ; 1.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                       ; None                       ; 1.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                       ; None                       ; 1.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                       ; None                       ; 2.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset      ; Reset    ; None                       ; None                       ; 2.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset      ; Reset    ; None                       ; None                       ; 2.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset      ; Reset    ; None                       ; None                       ; 2.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset      ; Reset    ; None                       ; None                       ; 2.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                       ; None                       ; 2.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                       ; None                       ; 2.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                       ; None                       ; 2.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                       ; None                       ; 2.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                       ; None                       ; 2.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset      ; Reset    ; None                       ; None                       ; 2.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset      ; Reset    ; None                       ; None                       ; 2.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset      ; Reset    ; None                       ; None                       ; 2.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                       ; None                       ; 2.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                       ; None                       ; 2.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset      ; Reset    ; None                       ; None                       ; 2.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                       ; None                       ; 2.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                       ; None                       ; 2.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset      ; Reset    ; None                       ; None                       ; 2.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset      ; Reset    ; None                       ; None                       ; 2.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                       ; None                       ; 2.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset      ; Reset    ; None                       ; None                       ; 2.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset      ; Reset    ; None                       ; None                       ; 2.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                       ; None                       ; 2.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                       ; None                       ; 2.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset      ; Reset    ; None                       ; None                       ; 2.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                       ; None                       ; 2.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset      ; Reset    ; None                       ; None                       ; 2.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset      ; Reset    ; None                       ; None                       ; 2.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                       ; None                       ; 2.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                       ; None                       ; 2.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                       ; None                       ; 2.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                       ; None                       ; 2.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset      ; Reset    ; None                       ; None                       ; 2.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset      ; Reset    ; None                       ; None                       ; 2.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                       ; None                       ; 2.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                       ; None                       ; 2.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                       ; None                       ; 2.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                       ; None                       ; 2.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset      ; Reset    ; None                       ; None                       ; 2.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset      ; Reset    ; None                       ; None                       ; 2.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                       ; None                       ; 2.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                       ; None                       ; 2.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                       ; None                       ; 2.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                       ; None                       ; 2.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                       ; None                       ; 2.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset      ; Reset    ; None                       ; None                       ; 2.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset      ; Reset    ; None                       ; None                       ; 2.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset    ; None                       ; None                       ; 2.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                       ; None                       ; 2.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                       ; None                       ; 2.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                       ; None                       ; 2.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                       ; None                       ; 2.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset      ; Reset    ; None                       ; None                       ; 2.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset      ; Reset    ; None                       ; None                       ; 2.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                       ; None                       ; 2.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                       ; None                       ; 2.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                       ; None                       ; 2.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                       ; None                       ; 2.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                       ; None                       ; 2.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset      ; Reset    ; None                       ; None                       ; 2.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset      ; Reset    ; None                       ; None                       ; 2.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                       ; None                       ; 2.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                       ; None                       ; 2.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                       ; None                       ; 2.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                       ; None                       ; 2.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                       ; None                       ; 2.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset      ; Reset    ; None                       ; None                       ; 2.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                       ; None                       ; 2.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                       ; None                       ; 3.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                       ; None                       ; 3.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                       ; None                       ; 3.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset      ; Reset    ; None                       ; None                       ; 3.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                       ; None                       ; 3.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 3.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                       ; None                       ; 3.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                       ; None                       ; 3.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset      ; Reset    ; None                       ; None                       ; 3.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                       ; None                       ; 3.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                       ; None                       ; 3.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset      ; Reset    ; None                       ; None                       ; 3.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                       ; None                       ; 3.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset      ; Reset    ; None                       ; None                       ; 3.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                       ; None                       ; 3.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset    ; None                       ; None                       ; 3.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 3.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 3.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 3.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 3.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|out_control                                                         ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 3.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset      ; Reset    ; None                       ; None                       ; 3.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset      ; Reset    ; None                       ; None                       ; 3.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset      ; Reset    ; None                       ; None                       ; 3.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset      ; Reset    ; None                       ; None                       ; 3.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset      ; Reset    ; None                       ; None                       ; 3.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset      ; Reset    ; None                       ; None                       ; 3.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset      ; Reset    ; None                       ; None                       ; 3.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset      ; Reset    ; None                       ; None                       ; 3.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset      ; Reset    ; None                       ; None                       ; 3.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset      ; Reset    ; None                       ; None                       ; 3.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset      ; Reset    ; None                       ; None                       ; 3.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset      ; Reset    ; None                       ; None                       ; 3.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset      ; Reset    ; None                       ; None                       ; 3.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset      ; Reset    ; None                       ; None                       ; 3.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset      ; Reset    ; None                       ; None                       ; 3.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset      ; Reset    ; None                       ; None                       ; 3.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 3.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 3.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset      ; Reset    ; None                       ; None                       ; 3.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset      ; Reset    ; None                       ; None                       ; 3.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset      ; Reset    ; None                       ; None                       ; 3.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset      ; Reset    ; None                       ; None                       ; 3.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset      ; Reset    ; None                       ; None                       ; 3.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset      ; Reset    ; None                       ; None                       ; 3.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset      ; Reset    ; None                       ; None                       ; 3.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset      ; Reset    ; None                       ; None                       ; 3.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 4.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 4.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 4.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 4.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 4.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 4.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 4.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset      ; Reset    ; None                       ; None                       ; 4.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 4.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset      ; Reset    ; None                       ; None                       ; 4.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset      ; Reset    ; None                       ; None                       ; 4.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset      ; Reset    ; None                       ; None                       ; 4.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset      ; Reset    ; None                       ; None                       ; 4.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset      ; Reset    ; None                       ; None                       ; 4.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset      ; Reset    ; None                       ; None                       ; 4.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset      ; Reset    ; None                       ; None                       ; 4.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset      ; Reset    ; None                       ; None                       ; 4.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset      ; Reset    ; None                       ; None                       ; 4.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 4.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; sum_control:inst5|out_control                                                         ; Reset      ; Reset    ; None                       ; None                       ; 4.600 ns                 ;
; Timing analysis restricted to 200 rows.  ; To change the limit use Settings (Assignments menu)                                   ;                                                                                       ;            ;          ;                            ;                            ;                          ;
+------------------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'Clock_8MHz'                                                                                                                                                                                                                                                                                                                ;
+------------------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+------------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                            ; From                                                                                  ; To                                                                                    ; From Clock ; To Clock   ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+------------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; sum_control:inst5|out_control                                                         ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|out_control                                                         ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.300 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.400 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.500 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.600 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.700 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.800 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 5.900 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.100 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.200 ns                 ;
; Not operational: Clock Skew > Data Delay ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ; Clock_8MHz ; None                       ; None                       ; 6.200 ns                 ;
; Timing analysis restricted to 200 rows.  ; To change the limit use Settings (Assignments menu)                                   ;                                                                                       ;            ;            ;                            ;                            ;                          ;
+------------------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+------------+----------------------------+----------------------------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tsu                                                                                                                                                                                                                         ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------+---------------------------------------------------------------------------------------+----------+
; Slack                                   ; Required tsu                                        ; Actual tsu ; From        ; To                                                                                    ; To Clock ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------+---------------------------------------------------------------------------------------+----------+
; N/A                                     ; None                                                ; 10.500 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset    ;
; N/A                                     ; None                                                ; 10.500 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset    ;
; N/A                                     ; None                                                ; 10.500 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset    ;
; N/A                                     ; None                                                ; 10.500 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset    ;
; N/A                                     ; None                                                ; 10.500 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset    ;
; N/A                                     ; None                                                ; 10.500 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset    ;
; N/A                                     ; None                                                ; 10.500 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset    ;
; N/A                                     ; None                                                ; 10.500 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset    ;
; N/A                                     ; None                                                ; 10.400 ns  ; Step_Sum[3] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[0] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset    ;
; N/A                                     ; None                                                ; 10.300 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[1] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset    ;
; N/A                                     ; None                                                ; 10.200 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset    ;
; N/A                                     ; None                                                ; 10.100 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset    ;
; N/A                                     ; None                                                ; 10.100 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset    ;
; N/A                                     ; None                                                ; 10.100 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset    ;
; N/A                                     ; None                                                ; 10.100 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset    ;
; N/A                                     ; None                                                ; 10.100 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset    ;
; N/A                                     ; None                                                ; 10.100 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset    ;
; N/A                                     ; None                                                ; 10.100 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset    ;
; N/A                                     ; None                                                ; 10.100 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset    ;
; N/A                                     ; None                                                ; 10.100 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset    ;
; N/A                                     ; None                                                ; 10.100 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset    ;
; N/A                                     ; None                                                ; 10.100 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset    ;
; N/A                                     ; None                                                ; 10.100 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset    ;
; N/A                                     ; None                                                ; 10.100 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset    ;
; N/A                                     ; None                                                ; 10.100 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset    ;
; N/A                                     ; None                                                ; 10.100 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset    ;
; N/A                                     ; None                                                ; 10.100 ns  ; Step_Sum[2] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset    ;
; N/A                                     ; None                                                ; 10.000 ns  ; Step_Sum[3] ; sum_control:inst5|out_control                                                         ; Reset    ;
; N/A                                     ; None                                                ; 9.900 ns   ; Step_Sum[0] ; sum_control:inst5|out_control                                                         ; Reset    ;
; N/A                                     ; None                                                ; 9.900 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset    ;
; N/A                                     ; None                                                ; 9.900 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset    ;
; N/A                                     ; None                                                ; 9.900 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset    ;
; N/A                                     ; None                                                ; 9.900 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset    ;
; N/A                                     ; None                                                ; 9.900 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset    ;
; N/A                                     ; None                                                ; 9.900 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset    ;
; N/A                                     ; None                                                ; 9.900 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset    ;
; N/A                                     ; None                                                ; 9.900 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[1] ; sum_control:inst5|out_control                                                         ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset    ;
; N/A                                     ; None                                                ; 9.800 ns   ; Step_Sum[4] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[5] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[2] ; sum_control:inst5|out_control                                                         ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[7] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[7] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[7] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[7] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[7] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[7] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[7] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Reset    ;
; N/A                                     ; None                                                ; 9.700 ns   ; Step_Sum[7] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[9] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Reset    ;
; N/A                                     ; None                                                ; 9.600 ns   ; Step_Sum[6] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Reset    ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;            ;             ;                                                                                       ;          ;
+-----------------------------------------+-----------------------------------------------------+------------+-------------+---------------------------------------------------------------------------------------+----------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                                    ;
+-------+--------------+------------+------------------------------------------------------------------------------------------+------------+------------+
; Slack ; Required tco ; Actual tco ; From                                                                                     ; To         ; From Clock ;
+-------+--------------+------------+------------------------------------------------------------------------------------------+------------+------------+
; N/A   ; None         ; 24.700 ns  ; sum_control:inst5|out_control                                                            ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 20.800 ns  ; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[0]  ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 20.800 ns  ; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1]  ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 19.800 ns  ; fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1]                      ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 19.500 ns  ; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[2]  ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 19.500 ns  ; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[3]  ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 18.600 ns  ; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[4]  ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 18.600 ns  ; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[5]  ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 17.700 ns  ; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[6]  ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 17.700 ns  ; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[7]  ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 16.200 ns  ; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[9]  ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 16.200 ns  ; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[8]  ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 15.300 ns  ; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[10] ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 15.300 ns  ; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[11] ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 15.200 ns  ; second_pulse_latch:inst3|second_pulse_out[4]                                             ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 14.800 ns  ; second_pulse_latch:inst3|second_pulse_out[5]                                             ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 14.700 ns  ; sum_control:inst5|out_control                                                            ; Pulse_Wave ; Reset      ;
; N/A   ; None         ; 14.700 ns  ; second_pulse_latch:inst3|second_pulse_out[7]                                             ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 14.600 ns  ; second_pulse_latch:inst3|second_pulse_out[6]                                             ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 14.600 ns  ; second_pulse_latch:inst3|second_pulse_out[3]                                             ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 14.200 ns  ; second_pulse_latch:inst3|second_pulse_out[9]                                             ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 14.100 ns  ; second_pulse_latch:inst3|second_pulse_out[10]                                            ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 14.100 ns  ; second_pulse_latch:inst3|second_pulse_out[12]                                            ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 14.000 ns  ; second_pulse_latch:inst3|second_pulse_out[8]                                             ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 14.000 ns  ; second_pulse_latch:inst3|second_pulse_out[14]                                            ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 13.700 ns  ; second_pulse_latch:inst3|second_pulse_out[13]                                            ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 13.700 ns  ; second_pulse_latch:inst3|second_pulse_out[11]                                            ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 13.600 ns  ; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[12] ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 13.600 ns  ; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[13] ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 13.400 ns  ; second_pulse_latch:inst3|second_pulse_out[2]                                             ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 12.600 ns  ; second_pulse_latch:inst3|second_pulse_out[1]                                             ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 12.500 ns  ; second_pulse_latch:inst3|second_pulse_out[0]                                             ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 12.100 ns  ; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[14] ; Pulse_Wave ; Clock_8MHz ;
; N/A   ; None         ; 12.000 ns  ; counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[15] ; Pulse_Wave ; Clock_8MHz ;
+-------+--------------+------------+------------------------------------------------------------------------------------------+------------+------------+


+------------------------------------------------------------------+
; tpd                                                              ;
+-------+-------------------+-----------------+-------+------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From  ; To         ;
+-------+-------------------+-----------------+-------+------------+
; N/A   ; None              ; 10.800 ns       ; Reset ; Pulse_Wave ;
+-------+-------------------+-----------------+-------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                                                                                                                            ;
+-----------------------------------------+-----------------------------------------------------+-----------+--------------+---------------------------------------------------------------------------------------+------------+
; Minimum Slack                           ; Required th                                         ; Actual th ; From         ; To                                                                                    ; To Clock   ;
+-----------------------------------------+-----------------------------------------------------+-----------+--------------+---------------------------------------------------------------------------------------+------------+
; N/A                                     ; None                                                ; 16.600 ns ; Reset        ; sum_control:inst5|out_control                                                         ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.300 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.300 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.300 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.300 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.300 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.300 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.300 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.300 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.300 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.300 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.300 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.300 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.300 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.300 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.300 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.300 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.200 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.200 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.200 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.200 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.200 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.200 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.200 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 16.200 ns ; Reset        ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.900 ns ; Step_Sum[11] ; sum_control:inst5|out_control                                                         ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.700 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.700 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.700 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.700 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.700 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.700 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.700 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.700 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.700 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.700 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.700 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.700 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.700 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.700 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.700 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.700 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.600 ns ; Step_Sum[8]  ; sum_control:inst5|out_control                                                         ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.600 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.600 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.600 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.600 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.600 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.600 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.600 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.600 ns ; Step_Sum[8]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.600 ns ; Step_Sum[1]  ; sum_control:inst5|out_control                                                         ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.600 ns ; Step_Sum[10] ; sum_control:inst5|out_control                                                         ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.500 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.500 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.500 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.500 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.500 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.500 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.500 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.500 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.500 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.500 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.500 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.500 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.500 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.500 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.500 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.500 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.400 ns ; Step_Sum[14] ; sum_control:inst5|out_control                                                         ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.400 ns ; Step_Sum[16] ; sum_control:inst5|out_control                                                         ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.400 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.400 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.400 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.400 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.400 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.400 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.400 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.400 ns ; Step_Sum[16] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.300 ns ; Step_Sum[0]  ; sum_control:inst5|out_control                                                         ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.200 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.200 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.200 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.200 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.200 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.200 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.200 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.200 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.200 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.200 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.200 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.200 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.200 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.200 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.200 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.200 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[11] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[6]  ; sum_control:inst5|out_control                                                         ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.100 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[6]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[7]  ; sum_control:inst5|out_control                                                         ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 10.000 ns ; Step_Sum[7]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[5]  ; sum_control:inst5|out_control                                                         ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[5]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[1]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[14] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[14] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[14] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[14] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; Clock_8MHz ;
; N/A                                     ; None                                                ; 9.900 ns  ; Step_Sum[14] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; Clock_8MHz ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;           ;              ;                                                                                       ;            ;
+-----------------------------------------+-----------------------------------------------------+-----------+--------------+---------------------------------------------------------------------------------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Wed Aug 02 16:41:44 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off main -c main
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis found one or more latches implemented as combinational loops
    Warning: Node "pulse_sum:inst4|pulse_1[3]" is a latch
    Warning: Node "pulse_sum:inst4|pulse_1[4]" is a latch
    Warning: Node "pulse_sum:inst4|pulse_1[5]" is a latch
    Warning: Node "pulse_sum:inst4|pulse_1[6]" is a latch
    Warning: Node "pulse_sum:inst4|pulse_1[0]" is a latch
    Warning: Node "pulse_sum:inst4|pulse_1[1]" is a latch
    Warning: Node "pulse_sum:inst4|pulse_1[2]" is a latch
    Warning: Node "pulse_sum:inst4|pulse_1[11]" is a latch
    Warning: Node "pulse_sum:inst4|pulse_1[12]" is a latch
    Warning: Node "pulse_sum:inst4|pulse_1[13]" is a latch
    Warning: Node "pulse_sum:inst4|pulse_1[14]" is a latch
    Warning: Node "pulse_sum:inst4|pulse_1[7]" is a latch
    Warning: Node "pulse_sum:inst4|pulse_1[8]" is a latch
    Warning: Node "pulse_sum:inst4|pulse_1[9]" is a latch
    Warning: Node "pulse_sum:inst4|pulse_1[10]" is a latch
Info: Found combinational loop of 1 nodes
    Info: Node "pulse_sum:inst4|pulse_1[6]"
Info: Found combinational loop of 1 nodes
    Info: Node "pulse_sum:inst4|pulse_1[5]"
Info: Found combinational loop of 1 nodes
    Info: Node "pulse_sum:inst4|pulse_1[4]"
Info: Found combinational loop of 1 nodes
    Info: Node "pulse_sum:inst4|pulse_1[3]"
Info: Found combinational loop of 1 nodes
    Info: Node "pulse_sum:inst4|pulse_1[2]"
Info: Found combinational loop of 1 nodes
    Info: Node "pulse_sum:inst4|pulse_1[1]"
Info: Found combinational loop of 1 nodes
    Info: Node "pulse_sum:inst4|pulse_1[0]"
Info: Found combinational loop of 1 nodes
    Info: Node "pulse_sum:inst4|pulse_1[10]"
Info: Found combinational loop of 1 nodes
    Info: Node "pulse_sum:inst4|pulse_1[9]"
Info: Found combinational loop of 1 nodes
    Info: Node "pulse_sum:inst4|pulse_1[8]"
Info: Found combinational loop of 1 nodes
    Info: Node "pulse_sum:inst4|pulse_1[7]"
Info: Found combinational loop of 1 nodes
    Info: Node "pulse_sum:inst4|pulse_1[14]"
Info: Found combinational loop of 1 nodes
    Info: Node "pulse_sum:inst4|pulse_1[13]"
Info: Found combinational loop of 1 nodes
    Info: Node "pulse_sum:inst4|pulse_1[12]"
Info: Found combinational loop of 1 nodes
    Info: Node "pulse_sum:inst4|pulse_1[11]"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "Reset" is an undefined clock
    Info: Assuming node "Clock_8MHz" is an undefined clock
Warning: Found 71 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~23" as buffer
    Info: Detected ripple clock "second_pulse_latch:inst3|second_pulse_out[11]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~25" as buffer
    Info: Detected ripple clock "second_pulse_latch:inst3|second_pulse_out[12]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~27" as buffer
    Info: Detected ripple clock "second_pulse_latch:inst3|second_pulse_out[13]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~425" as buffer
    Info: Detected ripple clock "second_pulse_latch:inst3|second_pulse_out[14]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~15" as buffer
    Info: Detected ripple clock "second_pulse_latch:inst3|second_pulse_out[7]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~17" as buffer
    Info: Detected ripple clock "second_pulse_latch:inst3|second_pulse_out[8]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~19" as buffer
    Info: Detected ripple clock "second_pulse_latch:inst3|second_pulse_out[9]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~21" as buffer
    Info: Detected ripple clock "second_pulse_latch:inst3|second_pulse_out[10]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1[10]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1[9]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1[8]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1[7]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~1" as buffer
    Info: Detected ripple clock "counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[15]" as buffer
    Info: Detected ripple clock "second_pulse_latch:inst3|second_pulse_out[0]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~3" as buffer
    Info: Detected ripple clock "counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[14]" as buffer
    Info: Detected ripple clock "second_pulse_latch:inst3|second_pulse_out[1]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~424" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~5" as buffer
    Info: Detected ripple clock "counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[13]" as buffer
    Info: Detected ripple clock "second_pulse_latch:inst3|second_pulse_out[2]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~7" as buffer
    Info: Detected ripple clock "counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[12]" as buffer
    Info: Detected ripple clock "second_pulse_latch:inst3|second_pulse_out[3]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~423" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~9" as buffer
    Info: Detected ripple clock "counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[11]" as buffer
    Info: Detected ripple clock "second_pulse_latch:inst3|second_pulse_out[4]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~11" as buffer
    Info: Detected ripple clock "counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[10]" as buffer
    Info: Detected ripple clock "second_pulse_latch:inst3|second_pulse_out[5]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~422" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~13" as buffer
    Info: Detected ripple clock "counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[8]" as buffer
    Info: Detected ripple clock "counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[9]" as buffer
    Info: Detected ripple clock "fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[3]" as buffer
    Info: Detected ripple clock "second_pulse_latch:inst3|second_pulse_out[6]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~421" as buffer
    Info: Detected ripple clock "counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[7]" as buffer
    Info: Detected ripple clock "counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[6]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~420" as buffer
    Info: Detected ripple clock "counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[5]" as buffer
    Info: Detected ripple clock "counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[4]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~419" as buffer
    Info: Detected ripple clock "counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[3]" as buffer
    Info: Detected ripple clock "counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[2]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1~418" as buffer
    Info: Detected ripple clock "counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1]" as buffer
    Info: Detected ripple clock "counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[0]" as buffer
    Info: Detected ripple clock "fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1[14]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1[13]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1[12]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1[11]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1[2]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1[1]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1[0]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1[6]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1[5]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1[4]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_1[3]" as buffer
    Info: Detected gated clock "pulse_sum:inst4|pulse_out~16" as buffer
Info: Clock "Reset" has Internal fmax of 87.72 MHz between source register "sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]" and destination register "sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23]" (period= 11.4 ns)
    Info: + Longest register to register delay is 6.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B3; Fanout = 4; REG Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: 2: + IC(0.600 ns) + CELL(0.700 ns) = 1.300 ns; Loc. = LC5_B2; Fanout = 1; COMB Node = 'sum_control:inst5|reduce_nor~288'
        Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 2.300 ns; Loc. = LC6_B2; Fanout = 1; COMB Node = 'sum_control:inst5|reduce_nor~297'
        Info: 4: + IC(0.600 ns) + CELL(1.100 ns) = 4.000 ns; Loc. = LC4_B6; Fanout = 2; COMB Node = 'sum_control:inst5|reduce_nor~267'
        Info: 5: + IC(0.100 ns) + CELL(1.000 ns) = 5.100 ns; Loc. = LC1_B6; Fanout = 54; COMB Node = 'rtl~0'
        Info: 6: + IC(0.600 ns) + CELL(0.700 ns) = 6.400 ns; Loc. = LC8_B7; Fanout = 3; REG Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23]'
        Info: Total cell delay = 4.500 ns ( 70.31 % )
        Info: Total interconnect delay = 1.900 ns ( 29.69 % )
    Info: - Smallest clock skew is -4.300 ns
        Info: + Shortest clock path from clock "Reset" to destination register is 4.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 51; CLK Node = 'Reset'
            Info: 2: + IC(0.100 ns) + CELL(1.000 ns) = 2.400 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4|pulse_out~16'
            Info: 3: + IC(2.100 ns) + CELL(0.000 ns) = 4.500 ns; Loc. = LC8_B7; Fanout = 3; REG Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23]'
            Info: Total cell delay = 2.300 ns ( 51.11 % )
            Info: Total interconnect delay = 2.200 ns ( 48.89 % )
        Info: - Longest clock path from clock "Reset" to source register is 8.800 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 51; CLK Node = 'Reset'
            Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 2.300 ns; Loc. = LC8_A9; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4|pulse_1[5]'
                Info: Loc. = LC8_A9; Node "pulse_sum:inst4|pulse_1[5]"
            Info: 3: + IC(0.700 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC3_A1; Fanout = 1; COMB Node = 'pulse_sum:inst4|pulse_out~126'
            Info: 4: + IC(1.000 ns) + CELL(0.800 ns) = 5.800 ns; Loc. = LC2_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_out~127'
            Info: 5: + IC(0.100 ns) + CELL(0.800 ns) = 6.700 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4|pulse_out~16'
            Info: 6: + IC(2.100 ns) + CELL(0.000 ns) = 8.800 ns; Loc. = LC4_B3; Fanout = 4; REG Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
            Info: Total cell delay = 4.900 ns ( 55.68 % )
            Info: Total interconnect delay = 3.900 ns ( 44.32 % )
    Info: + Micro clock to output delay of source is 0.300 ns
    Info: + Micro setup delay of destination is 0.400 ns
Info: Clock "Clock_8MHz" has Internal fmax of 62.5 MHz between source register "sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]" and destination register "sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23]" (period= 16.0 ns)
    Info: + Longest register to register delay is 6.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B3; Fanout = 4; REG Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: 2: + IC(0.600 ns) + CELL(0.700 ns) = 1.300 ns; Loc. = LC5_B2; Fanout = 1; COMB Node = 'sum_control:inst5|reduce_nor~288'
        Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 2.300 ns; Loc. = LC6_B2; Fanout = 1; COMB Node = 'sum_control:inst5|reduce_nor~297'
        Info: 4: + IC(0.600 ns) + CELL(1.100 ns) = 4.000 ns; Loc. = LC4_B6; Fanout = 2; COMB Node = 'sum_control:inst5|reduce_nor~267'
        Info: 5: + IC(0.100 ns) + CELL(1.000 ns) = 5.100 ns; Loc. = LC1_B6; Fanout = 54; COMB Node = 'rtl~0'
        Info: 6: + IC(0.600 ns) + CELL(0.700 ns) = 6.400 ns; Loc. = LC8_B7; Fanout = 3; REG Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23]'
        Info: Total cell delay = 4.500 ns ( 70.31 % )
        Info: Total interconnect delay = 1.900 ns ( 29.69 % )
    Info: - Smallest clock skew is -8.900 ns
        Info: + Shortest clock path from clock "Clock_8MHz" to destination register is 9.900 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 26; CLK Node = 'Clock_8MHz'
            Info: 2: + IC(0.200 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC3_C7; Fanout = 36; REG Node = 'fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1]'
            Info: 3: + IC(0.900 ns) + CELL(0.800 ns) = 3.500 ns; Loc. = LC4_A2; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_1~425'
            Info: 4: + IC(0.000 ns) + CELL(1.800 ns) = 5.300 ns; Loc. = LC6_A12; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4|pulse_1[14]'
                Info: Loc. = LC6_A12; Node "pulse_sum:inst4|pulse_1[14]"
            Info: 5: + IC(0.100 ns) + CELL(0.800 ns) = 6.200 ns; Loc. = LC5_A12; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_out~133'
            Info: 6: + IC(0.600 ns) + CELL(1.000 ns) = 7.800 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4|pulse_out~16'
            Info: 7: + IC(2.100 ns) + CELL(0.000 ns) = 9.900 ns; Loc. = LC8_B7; Fanout = 3; REG Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23]'
            Info: Total cell delay = 6.000 ns ( 60.61 % )
            Info: Total interconnect delay = 3.900 ns ( 39.39 % )
        Info: - Longest clock path from clock "Clock_8MHz" to source register is 18.800 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 26; CLK Node = 'Clock_8MHz'
            Info: 2: + IC(0.200 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC3_C7; Fanout = 36; REG Node = 'fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1]'
            Info: 3: + IC(0.900 ns) + CELL(0.300 ns) = 3.000 ns; Loc. = LC2_A3; Fanout = 6; REG Node = 'counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1]'
            Info: 4: + IC(0.500 ns) + CELL(1.000 ns) = 4.500 ns; Loc. = LC8_A2; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~418'
            Info: 5: + IC(1.000 ns) + CELL(0.800 ns) = 6.300 ns; Loc. = LC3_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~419'
            Info: 6: + IC(0.100 ns) + CELL(0.800 ns) = 7.200 ns; Loc. = LC4_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~420'
            Info: 7: + IC(0.100 ns) + CELL(0.800 ns) = 8.100 ns; Loc. = LC8_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~421'
            Info: 8: + IC(0.600 ns) + CELL(0.800 ns) = 9.500 ns; Loc. = LC3_A9; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~422'
            Info: 9: + IC(0.100 ns) + CELL(0.800 ns) = 10.400 ns; Loc. = LC1_A9; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~423'
            Info: 10: + IC(0.700 ns) + CELL(0.800 ns) = 11.900 ns; Loc. = LC4_A1; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_1~424'
            Info: 11: + IC(1.000 ns) + CELL(0.800 ns) = 13.700 ns; Loc. = LC7_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_1~1'
            Info: 12: + IC(0.000 ns) + CELL(0.900 ns) = 14.600 ns; Loc. = LC8_A10; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4|pulse_1[0]'
                Info: Loc. = LC8_A10; Node "pulse_sum:inst4|pulse_1[0]"
            Info: 13: + IC(0.100 ns) + CELL(1.100 ns) = 15.800 ns; Loc. = LC2_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_out~127'
            Info: 14: + IC(0.100 ns) + CELL(0.800 ns) = 16.700 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4|pulse_out~16'
            Info: 15: + IC(2.100 ns) + CELL(0.000 ns) = 18.800 ns; Loc. = LC4_B3; Fanout = 4; REG Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
            Info: Total cell delay = 11.300 ns ( 60.11 % )
            Info: Total interconnect delay = 7.500 ns ( 39.89 % )
    Info: + Micro clock to output delay of source is 0.300 ns
    Info: + Micro setup delay of destination is 0.400 ns
Warning: Circuit may not operate. Detected 201 non-operational path(s) clocked by clock "Reset" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" and destination pin or register "sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]" for clock "Reset" (Hold time is 3.1 ns)
    Info: + Largest clock skew is 4.300 ns
        Info: + Longest clock path from clock "Reset" to destination register is 8.800 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 51; CLK Node = 'Reset'
            Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 2.300 ns; Loc. = LC8_A9; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4|pulse_1[5]'
                Info: Loc. = LC8_A9; Node "pulse_sum:inst4|pulse_1[5]"
            Info: 3: + IC(0.700 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC3_A1; Fanout = 1; COMB Node = 'pulse_sum:inst4|pulse_out~126'
            Info: 4: + IC(1.000 ns) + CELL(0.800 ns) = 5.800 ns; Loc. = LC2_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_out~127'
            Info: 5: + IC(0.100 ns) + CELL(0.800 ns) = 6.700 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4|pulse_out~16'
            Info: 6: + IC(2.100 ns) + CELL(0.000 ns) = 8.800 ns; Loc. = LC1_B5; Fanout = 5; REG Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]'
            Info: Total cell delay = 4.900 ns ( 55.68 % )
            Info: Total interconnect delay = 3.900 ns ( 44.32 % )
        Info: - Shortest clock path from clock "Reset" to source register is 4.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 51; CLK Node = 'Reset'
            Info: 2: + IC(0.100 ns) + CELL(1.000 ns) = 2.400 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4|pulse_out~16'
            Info: 3: + IC(2.100 ns) + CELL(0.000 ns) = 4.500 ns; Loc. = LC1_B3; Fanout = 4; REG Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
            Info: Total cell delay = 2.300 ns ( 51.11 % )
            Info: Total interconnect delay = 2.200 ns ( 48.89 % )
    Info: - Micro clock to output delay of source is 0.300 ns
    Info: - Shortest register to register delay is 1.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B3; Fanout = 4; REG Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 0.100 ns; Loc. = LC1_B3; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT'
        Info: 3: + IC(0.000 ns) + CELL(0.100 ns) = 0.200 ns; Loc. = LC2_B3; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT'
        Info: 4: + IC(0.000 ns) + CELL(0.100 ns) = 0.300 ns; Loc. = LC3_B3; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT'
        Info: 5: + IC(0.000 ns) + CELL(0.100 ns) = 0.400 ns; Loc. = LC4_B3; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT'
        Info: 6: + IC(0.000 ns) + CELL(0.100 ns) = 0.500 ns; Loc. = LC5_B3; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT'
        Info: 7: + IC(0.000 ns) + CELL(0.100 ns) = 0.600 ns; Loc. = LC6_B3; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT'
        Info: 8: + IC(0.000 ns) + CELL(0.100 ns) = 0.700 ns; Loc. = LC7_B3; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT'
        Info: 9: + IC(0.000 ns) + CELL(0.100 ns) = 0.800 ns; Loc. = LC8_B3; Fanout = 3; COMB Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT'
        Info: 10: + IC(0.300 ns) + CELL(0.500 ns) = 1.600 ns; Loc. = LC1_B5; Fanout = 5; REG Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]'
        Info: Total cell delay = 1.300 ns ( 81.25 % )
        Info: Total interconnect delay = 0.300 ns ( 18.75 % )
    Info: + Micro hold delay of destination is 0.700 ns
Warning: Circuit may not operate. Detected 201 non-operational path(s) clocked by clock "Clock_8MHz" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]" and destination pin or register "sum_control:inst5|out_control" for clock "Clock_8MHz" (Hold time is 4.2 ns)
    Info: + Largest clock skew is 8.900 ns
        Info: + Longest clock path from clock "Clock_8MHz" to destination register is 18.800 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 26; CLK Node = 'Clock_8MHz'
            Info: 2: + IC(0.200 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC3_C7; Fanout = 36; REG Node = 'fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1]'
            Info: 3: + IC(0.900 ns) + CELL(0.300 ns) = 3.000 ns; Loc. = LC2_A3; Fanout = 6; REG Node = 'counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1]'
            Info: 4: + IC(0.500 ns) + CELL(1.000 ns) = 4.500 ns; Loc. = LC8_A2; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~418'
            Info: 5: + IC(1.000 ns) + CELL(0.800 ns) = 6.300 ns; Loc. = LC3_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~419'
            Info: 6: + IC(0.100 ns) + CELL(0.800 ns) = 7.200 ns; Loc. = LC4_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~420'
            Info: 7: + IC(0.100 ns) + CELL(0.800 ns) = 8.100 ns; Loc. = LC8_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~421'
            Info: 8: + IC(0.600 ns) + CELL(0.800 ns) = 9.500 ns; Loc. = LC3_A9; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~422'
            Info: 9: + IC(0.100 ns) + CELL(0.800 ns) = 10.400 ns; Loc. = LC1_A9; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~423'
            Info: 10: + IC(0.700 ns) + CELL(0.800 ns) = 11.900 ns; Loc. = LC4_A1; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_1~424'
            Info: 11: + IC(1.000 ns) + CELL(0.800 ns) = 13.700 ns; Loc. = LC7_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_1~1'
            Info: 12: + IC(0.000 ns) + CELL(0.900 ns) = 14.600 ns; Loc. = LC8_A10; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4|pulse_1[0]'
                Info: Loc. = LC8_A10; Node "pulse_sum:inst4|pulse_1[0]"
            Info: 13: + IC(0.100 ns) + CELL(1.100 ns) = 15.800 ns; Loc. = LC2_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_out~127'
            Info: 14: + IC(0.100 ns) + CELL(0.800 ns) = 16.700 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4|pulse_out~16'
            Info: 15: + IC(2.100 ns) + CELL(0.000 ns) = 18.800 ns; Loc. = LC1_B8; Fanout = 2; REG Node = 'sum_control:inst5|out_control'
            Info: Total cell delay = 11.300 ns ( 60.11 % )
            Info: Total interconnect delay = 7.500 ns ( 39.89 % )
        Info: - Shortest clock path from clock "Clock_8MHz" to source register is 9.900 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 26; CLK Node = 'Clock_8MHz'
            Info: 2: + IC(0.200 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC3_C7; Fanout = 36; REG Node = 'fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1]'
            Info: 3: + IC(0.900 ns) + CELL(0.800 ns) = 3.500 ns; Loc. = LC4_A2; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_1~425'
            Info: 4: + IC(0.000 ns) + CELL(1.800 ns) = 5.300 ns; Loc. = LC6_A12; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4|pulse_1[14]'
                Info: Loc. = LC6_A12; Node "pulse_sum:inst4|pulse_1[14]"
            Info: 5: + IC(0.100 ns) + CELL(0.800 ns) = 6.200 ns; Loc. = LC5_A12; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_out~133'
            Info: 6: + IC(0.600 ns) + CELL(1.000 ns) = 7.800 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4|pulse_out~16'
            Info: 7: + IC(2.100 ns) + CELL(0.000 ns) = 9.900 ns; Loc. = LC3_B3; Fanout = 4; REG Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]'
            Info: Total cell delay = 6.000 ns ( 60.61 % )
            Info: Total interconnect delay = 3.900 ns ( 39.39 % )
    Info: - Micro clock to output delay of source is 0.300 ns
    Info: - Shortest register to register delay is 5.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B3; Fanout = 4; REG Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]'
        Info: 2: + IC(0.700 ns) + CELL(1.000 ns) = 1.700 ns; Loc. = LC3_B4; Fanout = 1; COMB Node = 'sum_control:inst5|reduce_nor~295'
        Info: 3: + IC(0.500 ns) + CELL(1.000 ns) = 3.200 ns; Loc. = LC4_B6; Fanout = 2; COMB Node = 'sum_control:inst5|reduce_nor~267'
        Info: 4: + IC(0.600 ns) + CELL(0.800 ns) = 4.600 ns; Loc. = LC5_B8; Fanout = 1; COMB Node = 'sum_control:inst5|out_control~246'
        Info: 5: + IC(0.100 ns) + CELL(0.400 ns) = 5.100 ns; Loc. = LC1_B8; Fanout = 2; REG Node = 'sum_control:inst5|out_control'
        Info: Total cell delay = 3.200 ns ( 62.75 % )
        Info: Total interconnect delay = 1.900 ns ( 37.25 % )
    Info: + Micro hold delay of destination is 0.700 ns
Info: tsu for register "sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16]" (data pin = "Step_Sum[3]", clock pin = "Reset") is 10.500 ns
    Info: + Longest pin to register delay is 14.600 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_61; Fanout = 2; PIN Node = 'Step_Sum[3]'
        Info: 2: + IC(1.300 ns) + CELL(0.400 ns) = 4.500 ns; Loc. = LC4_B15; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[3]'
        Info: 3: + IC(0.000 ns) + CELL(0.100 ns) = 4.600 ns; Loc. = LC5_B15; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[4]'
        Info: 4: + IC(0.000 ns) + CELL(0.100 ns) = 4.700 ns; Loc. = LC6_B15; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[5]'
        Info: 5: + IC(0.000 ns) + CELL(0.100 ns) = 4.800 ns; Loc. = LC7_B15; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[6]'
        Info: 6: + IC(0.000 ns) + CELL(0.100 ns) = 4.900 ns; Loc. = LC8_B15; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[7]'
        Info: 7: + IC(0.300 ns) + CELL(0.100 ns) = 5.300 ns; Loc. = LC1_B17; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[8]'
        Info: 8: + IC(0.000 ns) + CELL(0.100 ns) = 5.400 ns; Loc. = LC2_B17; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[9]'
        Info: 9: + IC(0.000 ns) + CELL(0.100 ns) = 5.500 ns; Loc. = LC3_B17; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[10]'
        Info: 10: + IC(0.000 ns) + CELL(0.100 ns) = 5.600 ns; Loc. = LC4_B17; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[11]'
        Info: 11: + IC(0.000 ns) + CELL(0.100 ns) = 5.700 ns; Loc. = LC5_B17; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[12]'
        Info: 12: + IC(0.000 ns) + CELL(0.100 ns) = 5.800 ns; Loc. = LC6_B17; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[13]'
        Info: 13: + IC(0.000 ns) + CELL(0.100 ns) = 5.900 ns; Loc. = LC7_B17; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[14]'
        Info: 14: + IC(0.000 ns) + CELL(0.100 ns) = 6.000 ns; Loc. = LC8_B17; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[15]'
        Info: 15: + IC(0.300 ns) + CELL(0.100 ns) = 6.400 ns; Loc. = LC1_B19; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[16]'
        Info: 16: + IC(0.000 ns) + CELL(0.100 ns) = 6.500 ns; Loc. = LC2_B19; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[17]'
        Info: 17: + IC(0.000 ns) + CELL(0.100 ns) = 6.600 ns; Loc. = LC3_B19; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[18]'
        Info: 18: + IC(0.000 ns) + CELL(0.100 ns) = 6.700 ns; Loc. = LC4_B19; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[19]'
        Info: 19: + IC(0.000 ns) + CELL(0.100 ns) = 6.800 ns; Loc. = LC5_B19; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[20]'
        Info: 20: + IC(0.000 ns) + CELL(0.100 ns) = 6.900 ns; Loc. = LC6_B19; Fanout = 2; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[21]'
        Info: 21: + IC(0.000 ns) + CELL(0.100 ns) = 7.000 ns; Loc. = LC7_B19; Fanout = 1; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[22]'
        Info: 22: + IC(0.000 ns) + CELL(0.900 ns) = 7.900 ns; Loc. = LC8_B19; Fanout = 1; COMB Node = 'sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|unreg_res_node[23]'
        Info: 23: + IC(1.200 ns) + CELL(0.400 ns) = 9.500 ns; Loc. = LC5_B2; Fanout = 1; COMB Node = 'sum_control:inst5|reduce_nor~288'
        Info: 24: + IC(0.000 ns) + CELL(1.000 ns) = 10.500 ns; Loc. = LC6_B2; Fanout = 1; COMB Node = 'sum_control:inst5|reduce_nor~297'
        Info: 25: + IC(0.600 ns) + CELL(1.100 ns) = 12.200 ns; Loc. = LC4_B6; Fanout = 2; COMB Node = 'sum_control:inst5|reduce_nor~267'
        Info: 26: + IC(0.100 ns) + CELL(1.000 ns) = 13.300 ns; Loc. = LC1_B6; Fanout = 54; COMB Node = 'rtl~0'
        Info: 27: + IC(0.600 ns) + CELL(0.700 ns) = 14.600 ns; Loc. = LC1_B7; Fanout = 5; REG Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16]'
        Info: Total cell delay = 10.200 ns ( 69.86 % )
        Info: Total interconnect delay = 4.400 ns ( 30.14 % )
    Info: + Micro setup delay of destination is 0.400 ns
    Info: - Shortest clock path from clock "Reset" to destination register is 4.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 51; CLK Node = 'Reset'
        Info: 2: + IC(0.100 ns) + CELL(1.000 ns) = 2.400 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4|pulse_out~16'
        Info: 3: + IC(2.100 ns) + CELL(0.000 ns) = 4.500 ns; Loc. = LC1_B7; Fanout = 5; REG Node = 'sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16]'
        Info: Total cell delay = 2.300 ns ( 51.11 % )
        Info: Total interconnect delay = 2.200 ns ( 48.89 % )
Info: tco from clock "Clock_8MHz" to destination pin "Pulse_Wave" through register "sum_control:inst5|out_control" is 24.700 ns
    Info: + Longest clock path from clock "Clock_8MHz" to source register is 18.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 26; CLK Node = 'Clock_8MHz'
        Info: 2: + IC(0.200 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC3_C7; Fanout = 36; REG Node = 'fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1]'
        Info: 3: + IC(0.900 ns) + CELL(0.300 ns) = 3.000 ns; Loc. = LC2_A3; Fanout = 6; REG Node = 'counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1]'
        Info: 4: + IC(0.500 ns) + CELL(1.000 ns) = 4.500 ns; Loc. = LC8_A2; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~418'
        Info: 5: + IC(1.000 ns) + CELL(0.800 ns) = 6.300 ns; Loc. = LC3_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~419'
        Info: 6: + IC(0.100 ns) + CELL(0.800 ns) = 7.200 ns; Loc. = LC4_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~420'
        Info: 7: + IC(0.100 ns) + CELL(0.800 ns) = 8.100 ns; Loc. = LC8_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~421'
        Info: 8: + IC(0.600 ns) + CELL(0.800 ns) = 9.500 ns; Loc. = LC3_A9; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~422'
        Info: 9: + IC(0.100 ns) + CELL(0.800 ns) = 10.400 ns; Loc. = LC1_A9; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~423'
        Info: 10: + IC(0.700 ns) + CELL(0.800 ns) = 11.900 ns; Loc. = LC4_A1; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_1~424'
        Info: 11: + IC(1.000 ns) + CELL(0.800 ns) = 13.700 ns; Loc. = LC7_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_1~1'
        Info: 12: + IC(0.000 ns) + CELL(0.900 ns) = 14.600 ns; Loc. = LC8_A10; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4|pulse_1[0]'
            Info: Loc. = LC8_A10; Node "pulse_sum:inst4|pulse_1[0]"
        Info: 13: + IC(0.100 ns) + CELL(1.100 ns) = 15.800 ns; Loc. = LC2_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_out~127'
        Info: 14: + IC(0.100 ns) + CELL(0.800 ns) = 16.700 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4|pulse_out~16'
        Info: 15: + IC(2.100 ns) + CELL(0.000 ns) = 18.800 ns; Loc. = LC1_B8; Fanout = 2; REG Node = 'sum_control:inst5|out_control'
        Info: Total cell delay = 11.300 ns ( 60.11 % )
        Info: Total interconnect delay = 7.500 ns ( 39.89 % )
    Info: + Micro clock to output delay of source is 0.300 ns
    Info: + Longest register to pin delay is 5.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B8; Fanout = 2; REG Node = 'sum_control:inst5|out_control'
        Info: 2: + IC(0.900 ns) + CELL(0.800 ns) = 1.700 ns; Loc. = LC6_A10; Fanout = 1; COMB Node = 'sum_control:inst5|wave_out'
        Info: 3: + IC(0.100 ns) + CELL(3.800 ns) = 5.600 ns; Loc. = PIN_46; Fanout = 0; PIN Node = 'Pulse_Wave'
        Info: Total cell delay = 4.600 ns ( 82.14 % )
        Info: Total interconnect delay = 1.000 ns ( 17.86 % )
Info: Longest tpd from source pin "Reset" to destination pin "Pulse_Wave" is 10.800 ns
    Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 51; CLK Node = 'Reset'
    Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 2.300 ns; Loc. = LC8_A9; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4|pulse_1[5]'
        Info: Loc. = LC8_A9; Node "pulse_sum:inst4|pulse_1[5]"
    Info: 3: + IC(0.700 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC3_A1; Fanout = 1; COMB Node = 'pulse_sum:inst4|pulse_out~126'
    Info: 4: + IC(1.000 ns) + CELL(0.800 ns) = 5.800 ns; Loc. = LC2_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_out~127'
    Info: 5: + IC(0.100 ns) + CELL(1.000 ns) = 6.900 ns; Loc. = LC6_A10; Fanout = 1; COMB Node = 'sum_control:inst5|wave_out'
    Info: 6: + IC(0.100 ns) + CELL(3.800 ns) = 10.800 ns; Loc. = PIN_46; Fanout = 0; PIN Node = 'Pulse_Wave'
    Info: Total cell delay = 8.900 ns ( 82.41 % )
    Info: Total interconnect delay = 1.900 ns ( 17.59 % )
Info: th for register "sum_control:inst5|out_control" (data pin = "Reset", clock pin = "Clock_8MHz") is 16.600 ns
    Info: + Longest clock path from clock "Clock_8MHz" to destination register is 18.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 26; CLK Node = 'Clock_8MHz'
        Info: 2: + IC(0.200 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC3_C7; Fanout = 36; REG Node = 'fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1]'
        Info: 3: + IC(0.900 ns) + CELL(0.300 ns) = 3.000 ns; Loc. = LC2_A3; Fanout = 6; REG Node = 'counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1]'
        Info: 4: + IC(0.500 ns) + CELL(1.000 ns) = 4.500 ns; Loc. = LC8_A2; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~418'
        Info: 5: + IC(1.000 ns) + CELL(0.800 ns) = 6.300 ns; Loc. = LC3_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~419'
        Info: 6: + IC(0.100 ns) + CELL(0.800 ns) = 7.200 ns; Loc. = LC4_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~420'
        Info: 7: + IC(0.100 ns) + CELL(0.800 ns) = 8.100 ns; Loc. = LC8_A11; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~421'
        Info: 8: + IC(0.600 ns) + CELL(0.800 ns) = 9.500 ns; Loc. = LC3_A9; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~422'
        Info: 9: + IC(0.100 ns) + CELL(0.800 ns) = 10.400 ns; Loc. = LC1_A9; Fanout = 3; COMB Node = 'pulse_sum:inst4|pulse_1~423'
        Info: 10: + IC(0.700 ns) + CELL(0.800 ns) = 11.900 ns; Loc. = LC4_A1; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_1~424'
        Info: 11: + IC(1.000 ns) + CELL(0.800 ns) = 13.700 ns; Loc. = LC7_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_1~1'
        Info: 12: + IC(0.000 ns) + CELL(0.900 ns) = 14.600 ns; Loc. = LC8_A10; Fanout = 2; COMB LOOP Node = 'pulse_sum:inst4|pulse_1[0]'
            Info: Loc. = LC8_A10; Node "pulse_sum:inst4|pulse_1[0]"
        Info: 13: + IC(0.100 ns) + CELL(1.100 ns) = 15.800 ns; Loc. = LC2_A10; Fanout = 2; COMB Node = 'pulse_sum:inst4|pulse_out~127'
        Info: 14: + IC(0.100 ns) + CELL(0.800 ns) = 16.700 ns; Loc. = LC1_A10; Fanout = 28; COMB Node = 'pulse_sum:inst4|pulse_out~16'
        Info: 15: + IC(2.100 ns) + CELL(0.000 ns) = 18.800 ns; Loc. = LC1_B8; Fanout = 2; REG Node = 'sum_control:inst5|out_control'
        Info: Total cell delay = 11.300 ns ( 60.11 % )
        Info: Total interconnect delay = 7.500 ns ( 39.89 % )
    Info: + Micro hold delay of destination is 0.700 ns
    Info: - Shortest pin to register delay is 2.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 51; CLK Node = 'Reset'
        Info: 2: + IC(0.000 ns) + CELL(1.100 ns) = 2.400 ns; Loc. = LC5_B8; Fanout = 1; COMB Node = 'sum_control:inst5|out_control~246'
        Info: 3: + IC(0.100 ns) + CELL(0.400 ns) = 2.900 ns; Loc. = LC1_B8; Fanout = 2; REG Node = 'sum_control:inst5|out_control'
        Info: Total cell delay = 2.800 ns ( 96.55 % )
        Info: Total interconnect delay = 0.100 ns ( 3.45 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 20 warnings
    Info: Processing ended: Wed Aug 02 16:41:50 2006
    Info: Elapsed time: 00:00:07


