{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 08 14:20:03 2006 " "Info: Processing started: Tue Aug 08 14:20:03 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off Full_Adder -c Full_Adder " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Full_Adder -c Full_Adder" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "CIN COUT 5.000 ns Longest " "Info: Longest tpd from source pin \"CIN\" to destination pin \"COUT\" is 5.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns CIN 1 PIN PIN_25 3 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_25; Fanout = 3; PIN Node = 'CIN'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Full_Adder/db/Full_Adder_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Full_Adder/db/Full_Adder_cmp.qrpt" Compiler "Full_Adder" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Full_Adder/db/Full_Adder.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Full_Adder/" "" "" { CIN } "NODE_NAME" } "" } } { "Full_Adder.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Full_Adder/Full_Adder.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns add~48 2 COMB LC2 1 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC2; Fanout = 1; COMB Node = 'add~48'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Full_Adder/db/Full_Adder_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Full_Adder/db/Full_Adder_cmp.qrpt" Compiler "Full_Adder" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Full_Adder/db/Full_Adder.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Full_Adder/" "" "4.600 ns" { CIN add~48 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.000 ns COUT 3 PIN PIN_5 0 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 5.000 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'COUT'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Full_Adder/db/Full_Adder_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Full_Adder/db/Full_Adder_cmp.qrpt" Compiler "Full_Adder" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Full_Adder/db/Full_Adder.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Full_Adder/" "" "0.200 ns" { add~48 COUT } "NODE_NAME" } "" } } { "Full_Adder.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Full_Adder/Full_Adder.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 80.00 % " "Info: Total cell delay = 4.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 20.00 % " "Info: Total interconnect delay = 1.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/戴仙金/verilog/源代码/第2章/Full_Adder/db/Full_Adder_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Full_Adder/db/Full_Adder_cmp.qrpt" Compiler "Full_Adder" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Full_Adder/db/Full_Adder.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Full_Adder/" "" "5.000 ns" { CIN add~48 COUT } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "5.000 ns" { CIN CIN~out add~48 COUT } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 0.200ns 3.600ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 08 14:20:03 2006 " "Info: Processing ended: Tue Aug 08 14:20:03 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}
