{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 19 21:11:47 2006 " "Info: Processing started: Wed Jul 19 21:11:47 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off pulse_16 -c pulse_16 " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off pulse_16 -c pulse_16" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "Reset pulse_16_out\[0\] 5.100 ns Longest " "Info: Longest tpd from source pin \"Reset\" to destination pin \"pulse_16_out\[0\]\" is 5.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Reset 1 PIN PIN_84 16 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_84; Fanout = 16; PIN Node = 'Reset'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/db/pulse_16_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/db/pulse_16_cmp.qrpt" Compiler "pulse_16" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/db/pulse_16.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/" "" "" { Reset } "NODE_NAME" } "" } } { "pulse_16.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/pulse_16.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(3.500 ns) 4.900 ns pulse_16_out~262 2 COMB LC1 1 " "Info: 2: + IC(1.200 ns) + CELL(3.500 ns) = 4.900 ns; Loc. = LC1; Fanout = 1; COMB Node = 'pulse_16_out~262'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/db/pulse_16_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/db/pulse_16_cmp.qrpt" Compiler "pulse_16" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/db/pulse_16.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/" "" "4.700 ns" { Reset pulse_16_out~262 } "NODE_NAME" } "" } } { "pulse_16.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/pulse_16.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.100 ns pulse_16_out\[0\] 3 PIN PIN_14 0 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 5.100 ns; Loc. = PIN_14; Fanout = 0; PIN Node = 'pulse_16_out\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/db/pulse_16_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/db/pulse_16_cmp.qrpt" Compiler "pulse_16" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/db/pulse_16.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/" "" "0.200 ns" { pulse_16_out~262 pulse_16_out[0] } "NODE_NAME" } "" } } { "pulse_16.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/pulse_16.v" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 76.47 % " "Info: Total cell delay = 3.900 ns ( 76.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns 23.53 % " "Info: Total interconnect delay = 1.200 ns ( 23.53 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/db/pulse_16_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/db/pulse_16_cmp.qrpt" Compiler "pulse_16" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/db/pulse_16.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16/" "" "5.100 ns" { Reset pulse_16_out~262 pulse_16_out[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.100 ns" { Reset Reset~out pulse_16_out~262 pulse_16_out[0] } { 0.000ns 0.000ns 1.200ns 0.000ns } { 0.000ns 0.200ns 3.500ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 19 21:11:48 2006 " "Info: Processing ended: Wed Jul 19 21:11:48 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}
