// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

module DC_Motor_Main(
	Reset,
	AD7895_Busy,
	AD7492_Busy,
	AD7895_Data,
	Position_SW,
	Rate_SW,
	Current_SW,
	Clk_SCL,
	Clock,
	Rate_Pulse,
	Rate_Measure_Ctrl,
	AD7492_Data,
	Current_Set,
	Position_Set,
	Rate_Set,
	AD7895_SCL,
	AD7492_RD,
	AD7492_Mode,
	AD7492_CS,
	Rate_Over,
	Current_Adjust_Drive,
	Rate_Adjust_Drive,
	Position_Adjust_Drive,
	AD7895_Conv,
	AD7492_Conv
);

input	Reset;
input	AD7895_Busy;
input	AD7492_Busy;
input	AD7895_Data;
input	Position_SW;
input	Rate_SW;
input	Current_SW;
input	Clk_SCL;
input	Clock;
input	Rate_Pulse;
input	Rate_Measure_Ctrl;
input	[11:0] AD7492_Data;
input	[11:0] Current_Set;
input	[11:0] Position_Set;
input	[15:0] Rate_Set;
output	AD7895_SCL;
output	AD7492_RD;
output	AD7492_Mode;
output	AD7492_CS;
output	Rate_Over;
output	Current_Adjust_Drive;
output	Rate_Adjust_Drive;
output	Position_Adjust_Drive;
output	AD7895_Conv;
output	AD7492_Conv;

wire	SYNTHESIZED_WIRE_12;
wire	SYNTHESIZED_WIRE_1;
wire	[15:0] SYNTHESIZED_WIRE_2;
wire	SYNTHESIZED_WIRE_13;
wire	SYNTHESIZED_WIRE_6;
wire	[11:0] SYNTHESIZED_WIRE_7;
wire	SYNTHESIZED_WIRE_14;
wire	SYNTHESIZED_WIRE_10;
wire	[11:0] SYNTHESIZED_WIRE_11;





Rate_Adjust	b2v_inst11(.En(SYNTHESIZED_WIRE_12),
.Reset(Reset),.Rate_Adjust_Select(SYNTHESIZED_WIRE_1),.Rate_Data(SYNTHESIZED_WIRE_2),.Rate_Set(Rate_Set),.Rate_Adjust_Out(Rate_Adjust_Drive));

Rate_Measure	b2v_inst2(.En(SYNTHESIZED_WIRE_12),
.Reset(Reset),.Rate_Pulse(Rate_Pulse),.Measure_Ctrl(Rate_Measure_Ctrl),.Rate_Pulse_Alarm(Rate_Over),.Rate_Pulse_Data(SYNTHESIZED_WIRE_2));

main	b2v_inst3(.En(SYNTHESIZED_WIRE_13),
.Reset(Reset),.Adc_Busy(AD7895_Busy),.Adc_Data(AD7895_Data),.Clk_SCL(Clk_SCL),.Adc_SCL(AD7895_SCL),.Adc_Conv(AD7895_Conv),.Current_Data(SYNTHESIZED_WIRE_7));

Current_Adjust	b2v_inst5(.En(SYNTHESIZED_WIRE_13),
.Reset(Reset),.Current_Adjust_Select(SYNTHESIZED_WIRE_6),.Current_Data(SYNTHESIZED_WIRE_7),.Current_Set(Current_Set),.Current_Adjust_Out(Current_Adjust_Drive));

Position_adc_ctrl	b2v_inst6(.Reset(Reset),
.En(SYNTHESIZED_WIRE_14),.Clk(Clock),.Adc_Over(AD7492_Busy),.Adc_Data(AD7492_Data),.Adc_Cs(AD7492_CS),.Adc_Conv(AD7492_Conv),.Adc_Mode(AD7492_Mode),.Adc_Rd(AD7492_RD),.Position_Data(SYNTHESIZED_WIRE_11));

Position_Adjust	b2v_inst8(.Reset(Reset),
.En(SYNTHESIZED_WIRE_14),.Position_Adjust_Select(SYNTHESIZED_WIRE_10),.Position_Data(SYNTHESIZED_WIRE_11),.Position_Set(Position_Set),.Position_Adjust_Out(Position_Adjust_Drive));

Main_Ctrl	b2v_inst9(.Reset(Reset),
.Position_SW(Position_SW),.Rate_SW(Rate_SW),.Current_SW(Current_SW),.Position_En(SYNTHESIZED_WIRE_14),.Position_Adjust_En(SYNTHESIZED_WIRE_10),.Rate_En(SYNTHESIZED_WIRE_12),.Rate_Adjust_En(SYNTHESIZED_WIRE_1),.Current_En(SYNTHESIZED_WIRE_13),.Current_Adjust_En(SYNTHESIZED_WIRE_6));


endmodule
