module  SRAM_8_8(CS,RD,WR,Address,DIN,DOUT);
input   CS;
input   RD,WR;
input   [2:0] Address;
input   [7:0] DIN;
output  [7:0] DOUT;

reg  [7:0] DOUT;

reg  [7:0] Sram [0:7]; //存储空间

always  @(CS or RD or WR or Address or DIN)
begin
  if(WR == 1'b1)  //写数据
    begin
      if((CS == 1'b1) && (RD == 1'b0))
        Sram[Address] <= DIN;
    end
  else if(RD == 1'b1)  //读数据
    begin
      if((CS == 1'b1) && (WR == 1'b0))
        DOUT <= Sram[Address];
    end
end

endmodule