--G1_out_control is sum_control:inst5|out_control
--operation mode is normal

G1_out_control_lut_out = G1L01;
G1_out_control = DFFEA(G1_out_control_lut_out, F1L93, , , , , );


--F1L04 is pulse_sum:inst4|pulse_out~126
--operation mode is normal

F1L04 = F1_pulse_1[6] # F1_pulse_1[5] # F1_pulse_1[4] # F1_pulse_1[3];


--F1L14 is pulse_sum:inst4|pulse_out~127
--operation mode is normal

F1L14 = F1L04 # F1_pulse_1[2] # F1_pulse_1[1] # F1_pulse_1[0];


--G1_wave_out is sum_control:inst5|wave_out
--operation mode is normal

G1_wave_out = G1_out_control & !Reset & F1L14 # !F1L34;


--F1L93 is pulse_sum:inst4|pulse_out~16
--operation mode is normal

F1L93 = !Reset & F1L14 # !F1L34;


--J1_q[1] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

J1_q[1]_lut_out = (J1_q[1] $ J1L3) & B1L1;
J1_q[1] = DFFEA(J1_q[1]_lut_out, Clock_8MHz, , , , , );

--J1L5 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

J1L5 = CARRY(J1_q[1] & J1L3);


--J2_q[0] is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

J2_q[0]_lut_out = (!J2_q[0]) & C1L5;
J2_q[0] = DFFEA(J2_q[0]_lut_out, J1_q[1], , , , , );

--J2L3 is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

J2L3 = CARRY(J2_q[0]);


--J2_q[1] is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

J2_q[1]_lut_out = (J2_q[1] $ J2L3) & C1L5;
J2_q[1] = DFFEA(J2_q[1]_lut_out, J1_q[1], , , , , );

--J2L5 is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

J2L5 = CARRY(J2_q[1] & J2L3);


--F1L13 is pulse_sum:inst4|pulse_1~418
--operation mode is normal

F1L13 = J1_q[1] & !J2_q[0] & !J2_q[1];


--J2_q[2] is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

J2_q[2]_lut_out = (J2_q[2] $ J2L5) & C1L5;
J2_q[2] = DFFEA(J2_q[2]_lut_out, J1_q[1], , , , , );

--J2L7 is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

J2L7 = CARRY(J2_q[2] & J2L5);


--J2_q[3] is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

J2_q[3]_lut_out = (J2_q[3] $ J2L7) & C1L5;
J2_q[3] = DFFEA(J2_q[3]_lut_out, J1_q[1], , , , , );

--J2L9 is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

J2L9 = CARRY(J2_q[3] & J2L7);


--F1L23 is pulse_sum:inst4|pulse_1~419
--operation mode is normal

F1L23 = F1L13 & !J2_q[2] & !J2_q[3];


--J2_q[4] is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

J2_q[4]_lut_out = (J2_q[4] $ J2L9) & C1L5;
J2_q[4] = DFFEA(J2_q[4]_lut_out, J1_q[1], , , , , );

--J2L11 is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

J2L11 = CARRY(J2_q[4] & J2L9);


--J2_q[5] is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

J2_q[5]_lut_out = (J2_q[5] $ J2L11) & C1L5;
J2_q[5] = DFFEA(J2_q[5]_lut_out, J1_q[1], , , , , );

--J2L31 is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is clrb_cntr

J2L31 = CARRY(J2_q[5] & J2L11);


--F1L33 is pulse_sum:inst4|pulse_1~420
--operation mode is normal

F1L33 = F1L23 & !J2_q[4] & !J2_q[5];


--J2_q[6] is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

J2_q[6]_lut_out = (J2_q[6] $ J2L31) & C1L5;
J2_q[6] = DFFEA(J2_q[6]_lut_out, J1_q[1], , , , , );

--J2L51 is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

J2L51 = CARRY(J2_q[6] & J2L31);


--J2_q[7] is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

J2_q[7]_lut_out = (J2_q[7] $ J2L51) & C1L5;
J2_q[7] = DFFEA(J2_q[7]_lut_out, J1_q[1], , , , , );

--J2L71 is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is clrb_cntr

J2L71 = CARRY(J2_q[7] & J2L51);


--F1L43 is pulse_sum:inst4|pulse_1~421
--operation mode is normal

F1L43 = F1L33 & !J2_q[6] & !J2_q[7];


--E1_second_pulse_out[6] is second_pulse_latch:inst3|second_pulse_out[6]
--operation mode is normal

E1_second_pulse_out[6]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[7] # !Acceleration[16] & N6_cs_buffer[6];
E1_second_pulse_out[6] = DFFEA(E1_second_pulse_out[6]_lut_out, J1_q[3], , , , , );


--J2_q[9] is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[9]
--operation mode is clrb_cntr

J2_q[9]_lut_out = (J2_q[9] $ J2L91) & C1L5;
J2_q[9] = DFFEA(J2_q[9]_lut_out, J1_q[1], , , , , );

--J2L12 is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT
--operation mode is clrb_cntr

J2L12 = CARRY(J2_q[9] & J2L91);


--J2_q[8] is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[8]
--operation mode is clrb_cntr

J2_q[8]_lut_out = (J2_q[8] $ J2L71) & C1L5;
J2_q[8] = DFFEA(J2_q[8]_lut_out, J1_q[1], , , , , );

--J2L91 is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is clrb_cntr

J2L91 = CARRY(J2_q[8] & J2L71);


--F1L32 is pulse_sum:inst4|pulse_1~13
--operation mode is normal

F1L32 = F1L43 & E1_second_pulse_out[6] & J2_q[9] & !J2_q[8];


--F1_pulse_1[6] is pulse_sum:inst4|pulse_1[6]
--operation mode is normal

F1_pulse_1[6] = Reset & F1_pulse_1[6] # !Reset & F1L32;


--F1L53 is pulse_sum:inst4|pulse_1~422
--operation mode is normal

F1L53 = F1L43 & !J2_q[8] & !J2_q[9];


--E1_second_pulse_out[5] is second_pulse_latch:inst3|second_pulse_out[5]
--operation mode is normal

E1_second_pulse_out[5]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[6] # !Acceleration[16] & N6_cs_buffer[5];
E1_second_pulse_out[5] = DFFEA(E1_second_pulse_out[5]_lut_out, J1_q[3], , , , , );


--J2_q[10] is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[10]
--operation mode is clrb_cntr

J2_q[10]_lut_out = (J2_q[10] $ J2L12) & C1L5;
J2_q[10] = DFFEA(J2_q[10]_lut_out, J1_q[1], , , , , );

--J2L32 is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[10]~COUT
--operation mode is clrb_cntr

J2L32 = CARRY(J2_q[10] & J2L12);


--F1L22 is pulse_sum:inst4|pulse_1~11
--operation mode is normal

F1L22 = F1L53 & E1_second_pulse_out[5] & J2_q[10];


--F1_pulse_1[5] is pulse_sum:inst4|pulse_1[5]
--operation mode is normal

F1_pulse_1[5] = Reset & F1_pulse_1[5] # !Reset & F1L22;


--E1_second_pulse_out[4] is second_pulse_latch:inst3|second_pulse_out[4]
--operation mode is normal

E1_second_pulse_out[4]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[5] # !Acceleration[16] & N6_cs_buffer[4];
E1_second_pulse_out[4] = DFFEA(E1_second_pulse_out[4]_lut_out, J1_q[3], , , , , );


--J2_q[11] is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[11]
--operation mode is clrb_cntr

J2_q[11]_lut_out = (J2_q[11] $ J2L32) & C1L5;
J2_q[11] = DFFEA(J2_q[11]_lut_out, J1_q[1], , , , , );

--J2L52 is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[11]~COUT
--operation mode is clrb_cntr

J2L52 = CARRY(J2_q[11] & J2L32);


--F1L12 is pulse_sum:inst4|pulse_1~9
--operation mode is normal

F1L12 = F1L53 & E1_second_pulse_out[4] & J2_q[11] & !J2_q[10];


--F1_pulse_1[4] is pulse_sum:inst4|pulse_1[4]
--operation mode is normal

F1_pulse_1[4] = Reset & F1_pulse_1[4] # !Reset & F1L12;


--F1L63 is pulse_sum:inst4|pulse_1~423
--operation mode is normal

F1L63 = F1L53 & !J2_q[10] & !J2_q[11];


--E1_second_pulse_out[3] is second_pulse_latch:inst3|second_pulse_out[3]
--operation mode is normal

E1_second_pulse_out[3]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[4] # !Acceleration[16] & N6_cs_buffer[3];
E1_second_pulse_out[3] = DFFEA(E1_second_pulse_out[3]_lut_out, J1_q[3], , , , , );


--J2_q[12] is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[12]
--operation mode is clrb_cntr

J2_q[12]_lut_out = (J2_q[12] $ J2L52) & C1L5;
J2_q[12] = DFFEA(J2_q[12]_lut_out, J1_q[1], , , , , );

--J2L72 is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[12]~COUT
--operation mode is clrb_cntr

J2L72 = CARRY(J2_q[12] & J2L52);


--F1L02 is pulse_sum:inst4|pulse_1~7
--operation mode is normal

F1L02 = F1L63 & E1_second_pulse_out[3] & J2_q[12];


--F1_pulse_1[3] is pulse_sum:inst4|pulse_1[3]
--operation mode is normal

F1_pulse_1[3] = Reset & F1_pulse_1[3] # !Reset & F1L02;


--E1_second_pulse_out[2] is second_pulse_latch:inst3|second_pulse_out[2]
--operation mode is normal

E1_second_pulse_out[2]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[3] # !Acceleration[16] & N6_cs_buffer[2];
E1_second_pulse_out[2] = DFFEA(E1_second_pulse_out[2]_lut_out, J1_q[3], , , , , );


--J2_q[13] is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[13]
--operation mode is clrb_cntr

J2_q[13]_lut_out = (J2_q[13] $ J2L72) & C1L5;
J2_q[13] = DFFEA(J2_q[13]_lut_out, J1_q[1], , , , , );

--J2L92 is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[13]~COUT
--operation mode is clrb_cntr

J2L92 = CARRY(J2_q[13] & J2L72);


--F1L91 is pulse_sum:inst4|pulse_1~5
--operation mode is normal

F1L91 = F1L63 & E1_second_pulse_out[2] & J2_q[13] & !J2_q[12];


--F1_pulse_1[2] is pulse_sum:inst4|pulse_1[2]
--operation mode is normal

F1_pulse_1[2] = Reset & F1_pulse_1[2] # !Reset & F1L91;


--F1L73 is pulse_sum:inst4|pulse_1~424
--operation mode is normal

F1L73 = F1L63 & !J2_q[12] & !J2_q[13];


--E1_second_pulse_out[1] is second_pulse_latch:inst3|second_pulse_out[1]
--operation mode is normal

E1_second_pulse_out[1]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[2] # !Acceleration[16] & N6_cs_buffer[1];
E1_second_pulse_out[1] = DFFEA(E1_second_pulse_out[1]_lut_out, J1_q[3], , , , , );


--J2_q[14] is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[14]
--operation mode is clrb_cntr

J2_q[14]_lut_out = (J2_q[14] $ J2L92) & C1L5;
J2_q[14] = DFFEA(J2_q[14]_lut_out, J1_q[1], , , , , );

--J2L13 is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT
--operation mode is clrb_cntr

J2L13 = CARRY(J2_q[14] & J2L92);


--F1L81 is pulse_sum:inst4|pulse_1~3
--operation mode is normal

F1L81 = F1L73 & E1_second_pulse_out[1] & J2_q[14];


--F1_pulse_1[1] is pulse_sum:inst4|pulse_1[1]
--operation mode is normal

F1_pulse_1[1] = Reset & F1_pulse_1[1] # !Reset & F1L81;


--E1_second_pulse_out[0] is second_pulse_latch:inst3|second_pulse_out[0]
--operation mode is normal

E1_second_pulse_out[0]_lut_out = !Reset & Acceleration[16] & N3_cs_buffer[1] # !Acceleration[16] & N6_cs_buffer[0];
E1_second_pulse_out[0] = DFFEA(E1_second_pulse_out[0]_lut_out, J1_q[3], , , , , );


--J2_q[15] is counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter|q[15]
--operation mode is clrb_cntr

J2_q[15]_lut_out = (J2_q[15] $ J2L13) & C1L5;
J2_q[15] = DFFEA(J2_q[15]_lut_out, J1_q[1], , , , , );


--F1L71 is pulse_sum:inst4|pulse_1~1
--operation mode is normal

F1L71 = F1L73 & E1_second_pulse_out[0] & J2_q[15] & !J2_q[14];


--F1_pulse_1[0] is pulse_sum:inst4|pulse_1[0]
--operation mode is normal

F1_pulse_1[0] = Reset & F1_pulse_1[0] # !Reset & F1L71;


--J1_q[3] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

J1_q[3]_lut_out = (J1_q[3] $ J1L7) & B1L1;
J1_q[3] = DFFEA(J1_q[3]_lut_out, Clock_8MHz, , , , , );

--J1L9 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

J1L9 = CARRY(J1_q[3] & J1L7);


--J1_q[2] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

J1_q[2]_lut_out = (J1_q[2] $ J1L5) & B1L1;
J1_q[2] = DFFEA(J1_q[2]_lut_out, Clock_8MHz, , , , , );

--J1L7 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

J1L7 = CARRY(J1_q[2] & J1L5);


--J1_q[0] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

J1_q[0]_lut_out = (!J1_q[0]) & B1L1;
J1_q[0] = DFFEA(J1_q[0]_lut_out, Clock_8MHz, , , , , );

--J1L3 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

J1L3 = CARRY(J1_q[0]);


--B1L7 is fdiv:inst|LessThan~111
--operation mode is normal

B1L7 = !J1_q[0] # !J1_q[2] # !J1_q[3] # !J1_q[1];


--J1_q[22] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[22]
--operation mode is clrb_cntr

J1_q[22]_lut_out = (J1_q[22] $ J1L54) & B1L1;
J1_q[22] = DFFEA(J1_q[22]_lut_out, Clock_8MHz, , , , , );


--J1_q[21] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[21]
--operation mode is clrb_cntr

J1_q[21]_lut_out = (J1_q[21] $ J1L34) & B1L1;
J1_q[21] = DFFEA(J1_q[21]_lut_out, Clock_8MHz, , , , , );

--J1L54 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[21]~COUT
--operation mode is clrb_cntr

J1L54 = CARRY(J1_q[21] & J1L34);


--J1_q[20] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[20]
--operation mode is clrb_cntr

J1_q[20]_lut_out = (J1_q[20] $ J1L14) & B1L1;
J1_q[20] = DFFEA(J1_q[20]_lut_out, Clock_8MHz, , , , , );

--J1L34 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[20]~COUT
--operation mode is clrb_cntr

J1L34 = CARRY(J1_q[20] & J1L14);


--B1L2 is fdiv:inst|CNT~252
--operation mode is normal

B1L2 = !Reset & !J1_q[22] & !J1_q[21] & !J1_q[20];


--B1L1 is fdiv:inst|CNT~46
--operation mode is normal

B1L1 = B1L7 & B1L2 & B1L5 & B1L6;


--C1L1 is counter_16_bits:inst1|LessThan~170
--operation mode is normal

C1L1 = !J2_q[3] # !J2_q[2] # !J2_q[1] # !J2_q[0];


--C1L2 is counter_16_bits:inst1|LessThan~171
--operation mode is normal

C1L2 = !J2_q[7] # !J2_q[6] # !J2_q[5] # !J2_q[4];


--C1L3 is counter_16_bits:inst1|LessThan~172
--operation mode is normal

C1L3 = !J2_q[11] # !J2_q[10] # !J2_q[9] # !J2_q[8];


--C1L4 is counter_16_bits:inst1|LessThan~173
--operation mode is normal

C1L4 = !J2_q[15] # !J2_q[14] # !J2_q[13] # !J2_q[12];


--C1L5 is counter_16_bits:inst1|LessThan~174
--operation mode is normal

C1L5 = C1L1 # C1L2 # C1L3 # C1L4;


--N6_cs_buffer[6] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]
--operation mode is arithmetic

N6_cs_buffer[6] = Acceleration[6] $ E1_second_pulse_out[6] $ N6_cout[5];

--N6_cout[6] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

N6_cout[6] = CARRY(Acceleration[6] & E1_second_pulse_out[6] # N6_cout[5] # !Acceleration[6] & E1_second_pulse_out[6] & N6_cout[5]);


--N3_cs_buffer[7] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]
--operation mode is arithmetic

N3_cs_buffer[7] = Acceleration[6] $ E1_second_pulse_out[6] $ N3_cout[6];

--N3_cout[7] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[7]
--operation mode is arithmetic

N3_cout[7] = CARRY(Acceleration[6] & E1_second_pulse_out[6] & N3_cout[6] # !Acceleration[6] & E1_second_pulse_out[6] # N3_cout[6]);


--N6_cs_buffer[5] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

N6_cs_buffer[5] = Acceleration[5] $ E1_second_pulse_out[5] $ N6_cout[4];

--N6_cout[5] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

N6_cout[5] = CARRY(Acceleration[5] & E1_second_pulse_out[5] # N6_cout[4] # !Acceleration[5] & E1_second_pulse_out[5] & N6_cout[4]);


--N3_cs_buffer[6] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]
--operation mode is arithmetic

N3_cs_buffer[6] = Acceleration[5] $ E1_second_pulse_out[5] $ N3_cout[5];

--N3_cout[6] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

N3_cout[6] = CARRY(Acceleration[5] & E1_second_pulse_out[5] & N3_cout[5] # !Acceleration[5] & E1_second_pulse_out[5] # N3_cout[5]);


--N6_cs_buffer[4] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

N6_cs_buffer[4] = Acceleration[4] $ E1_second_pulse_out[4] $ N6_cout[3];

--N6_cout[4] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

N6_cout[4] = CARRY(Acceleration[4] & E1_second_pulse_out[4] # N6_cout[3] # !Acceleration[4] & E1_second_pulse_out[4] & N6_cout[3]);


--N3_cs_buffer[5] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

N3_cs_buffer[5] = Acceleration[4] $ E1_second_pulse_out[4] $ N3_cout[4];

--N3_cout[5] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

N3_cout[5] = CARRY(Acceleration[4] & E1_second_pulse_out[4] & N3_cout[4] # !Acceleration[4] & E1_second_pulse_out[4] # N3_cout[4]);


--N6_cs_buffer[3] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

N6_cs_buffer[3] = Acceleration[3] $ E1_second_pulse_out[3] $ N6_cout[2];

--N6_cout[3] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

N6_cout[3] = CARRY(Acceleration[3] & E1_second_pulse_out[3] # N6_cout[2] # !Acceleration[3] & E1_second_pulse_out[3] & N6_cout[2]);


--N3_cs_buffer[4] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

N3_cs_buffer[4] = Acceleration[3] $ E1_second_pulse_out[3] $ N3_cout[3];

--N3_cout[4] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

N3_cout[4] = CARRY(Acceleration[3] & E1_second_pulse_out[3] & N3_cout[3] # !Acceleration[3] & E1_second_pulse_out[3] # N3_cout[3]);


--N6_cs_buffer[2] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

N6_cs_buffer[2] = Acceleration[2] $ E1_second_pulse_out[2] $ N6_cout[1];

--N6_cout[2] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

N6_cout[2] = CARRY(Acceleration[2] & E1_second_pulse_out[2] # N6_cout[1] # !Acceleration[2] & E1_second_pulse_out[2] & N6_cout[1]);


--N3_cs_buffer[3] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

N3_cs_buffer[3] = Acceleration[2] $ E1_second_pulse_out[2] $ N3_cout[2];

--N3_cout[3] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

N3_cout[3] = CARRY(Acceleration[2] & E1_second_pulse_out[2] & N3_cout[2] # !Acceleration[2] & E1_second_pulse_out[2] # N3_cout[2]);


--N6_cs_buffer[1] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

N6_cs_buffer[1] = Acceleration[1] $ E1_second_pulse_out[1] $ N6_cout[0];

--N6_cout[1] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

N6_cout[1] = CARRY(Acceleration[1] & E1_second_pulse_out[1] # N6_cout[0] # !Acceleration[1] & E1_second_pulse_out[1] & N6_cout[0]);


--N3_cs_buffer[2] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

N3_cs_buffer[2] = Acceleration[1] $ E1_second_pulse_out[1] $ N3_cout[1];

--N3_cout[2] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

N3_cout[2] = CARRY(Acceleration[1] & E1_second_pulse_out[1] & N3_cout[1] # !Acceleration[1] & E1_second_pulse_out[1] # N3_cout[1]);


--N3_cs_buffer[1] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

N3_cs_buffer[1] = E1_second_pulse_out[0] $ Acceleration[0];

--N3_cout[1] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

N3_cout[1] = CARRY(E1_second_pulse_out[0] # !Acceleration[0]);


--N6_cs_buffer[0] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]
--operation mode is arithmetic

N6_cs_buffer[0] = E1_second_pulse_out[0] $ Acceleration[0];

--N6_cout[0] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

N6_cout[0] = CARRY(E1_second_pulse_out[0] & Acceleration[0]);


--F1L24 is pulse_sum:inst4|pulse_out~131
--operation mode is normal

F1L24 = !F1_pulse_1[10] & !F1_pulse_1[9] & !F1_pulse_1[8] & !F1_pulse_1[7];


--F1L34 is pulse_sum:inst4|pulse_out~133
--operation mode is normal

F1L34 = (!F1_pulse_1[14] & !F1_pulse_1[13] & !F1_pulse_1[12] & !F1_pulse_1[11]) & CASCADE(F1L24);


--J3_q[8] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[8]
--operation mode is clrb_cntr

J3_q[8]_lut_out = (J3_q[8] $ (A1L04 & J3L71)) & A1L93;
J3_q[8] = DFFEA(J3_q[8]_lut_out, F1L93, , , A1L04, , );

--J3L91 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is clrb_cntr

J3L91 = CARRY(J3_q[8] & J3L71);


--J3_q[16] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16]
--operation mode is clrb_cntr

J3_q[16]_lut_out = (J3_q[16] $ (A1L04 & J3L33)) & A1L93;
J3_q[16] = DFFEA(J3_q[16]_lut_out, F1L93, , , A1L04, , );

--J3L53 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[16]~COUT
--operation mode is clrb_cntr

J3L53 = CARRY(J3_q[16] & J3L33);


--J3_q[9] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[9]
--operation mode is clrb_cntr

J3_q[9]_lut_out = (J3_q[9] $ (A1L04 & J3L91)) & A1L93;
J3_q[9] = DFFEA(J3_q[9]_lut_out, F1L93, , , A1L04, , );

--J3L12 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT
--operation mode is clrb_cntr

J3L12 = CARRY(J3_q[9] & J3L91);


--G1L3 is sum_control:inst5|out_control~237
--operation mode is normal

G1L3 = G1_out_control # !J3_q[9] # !J3_q[16] # !J3_q[8];


--J3_q[12] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[12]
--operation mode is clrb_cntr

J3_q[12]_lut_out = (J3_q[12] $ (A1L04 & J3L52)) & A1L93;
J3_q[12] = DFFEA(J3_q[12]_lut_out, F1L93, , , A1L04, , );

--J3L72 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~COUT
--operation mode is clrb_cntr

J3L72 = CARRY(J3_q[12] & J3L52);


--J3_q[11] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[11]
--operation mode is clrb_cntr

J3_q[11]_lut_out = (J3_q[11] $ (A1L04 & J3L32)) & A1L93;
J3_q[11] = DFFEA(J3_q[11]_lut_out, F1L93, , , A1L04, , );

--J3L52 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[11]~COUT
--operation mode is clrb_cntr

J3L52 = CARRY(J3_q[11] & J3L32);


--J3_q[1] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

J3_q[1]_lut_out = (J3_q[1] $ (A1L04 & J3L3)) & A1L93;
J3_q[1] = DFFEA(J3_q[1]_lut_out, F1L93, , , A1L04, , );

--J3L5 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

J3L5 = CARRY(J3_q[1] & J3L3);


--J3_q[14] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[14]
--operation mode is clrb_cntr

J3_q[14]_lut_out = (J3_q[14] $ (A1L04 & J3L92)) & A1L93;
J3_q[14] = DFFEA(J3_q[14]_lut_out, F1L93, , , A1L04, , );

--J3L13 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT
--operation mode is clrb_cntr

J3L13 = CARRY(J3_q[14] & J3L92);


--G1L4 is sum_control:inst5|out_control~238
--operation mode is normal

G1L4 = !J3_q[14] # !J3_q[1] # !J3_q[11] # !J3_q[12];


--J3_q[6] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

J3_q[6]_lut_out = (J3_q[6] $ (A1L04 & J3L31)) & A1L93;
J3_q[6] = DFFEA(J3_q[6]_lut_out, F1L93, , , A1L04, , );

--J3L51 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

J3L51 = CARRY(J3_q[6] & J3L31);


--J3_q[22] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22]
--operation mode is clrb_cntr

J3_q[22]_lut_out = (J3_q[22] $ (A1L04 & J3L54)) & A1L93;
J3_q[22] = DFFEA(J3_q[22]_lut_out, F1L93, , , A1L04, , );

--J3L74 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[22]~COUT
--operation mode is clrb_cntr

J3L74 = CARRY(J3_q[22] & J3L54);


--J3_q[10] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[10]
--operation mode is clrb_cntr

J3_q[10]_lut_out = (J3_q[10] $ (A1L04 & J3L12)) & A1L93;
J3_q[10] = DFFEA(J3_q[10]_lut_out, F1L93, , , A1L04, , );

--J3L32 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[10]~COUT
--operation mode is clrb_cntr

J3L32 = CARRY(J3_q[10] & J3L12);


--J3_q[17] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[17]
--operation mode is clrb_cntr

J3_q[17]_lut_out = (J3_q[17] $ (A1L04 & J3L53)) & A1L93;
J3_q[17] = DFFEA(J3_q[17]_lut_out, F1L93, , , A1L04, , );

--J3L73 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[17]~COUT
--operation mode is clrb_cntr

J3L73 = CARRY(J3_q[17] & J3L53);


--G1L5 is sum_control:inst5|out_control~239
--operation mode is normal

G1L5 = !J3_q[17] # !J3_q[10] # !J3_q[22] # !J3_q[6];


--J3_q[7] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

J3_q[7]_lut_out = (J3_q[7] $ (A1L04 & J3L51)) & A1L93;
J3_q[7] = DFFEA(J3_q[7]_lut_out, F1L93, , , A1L04, , );

--J3L71 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is clrb_cntr

J3L71 = CARRY(J3_q[7] & J3L51);


--J3_q[2] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

J3_q[2]_lut_out = (J3_q[2] $ (A1L04 & J3L5)) & A1L93;
J3_q[2] = DFFEA(J3_q[2]_lut_out, F1L93, , , A1L04, , );

--J3L7 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

J3L7 = CARRY(J3_q[2] & J3L5);


--J3_q[0] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

J3_q[0]_lut_out = (A1L04 $ J3_q[0]) & A1L93;
J3_q[0] = DFFEA(J3_q[0]_lut_out, F1L93, , , A1L04, , );

--J3L3 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

J3L3 = CARRY(J3_q[0]);


--J3_q[4] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

J3_q[4]_lut_out = (J3_q[4] $ (A1L04 & J3L9)) & A1L93;
J3_q[4] = DFFEA(J3_q[4]_lut_out, F1L93, , , A1L04, , );

--J3L11 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

J3L11 = CARRY(J3_q[4] & J3L9);


--G1L6 is sum_control:inst5|out_control~240
--operation mode is normal

G1L6 = !J3_q[4] # !J3_q[0] # !J3_q[2] # !J3_q[7];


--G1L7 is sum_control:inst5|out_control~241
--operation mode is normal

G1L7 = G1L3 # G1L4 # G1L5 # G1L6;


--J3_q[15] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[15]
--operation mode is clrb_cntr

J3_q[15]_lut_out = (J3_q[15] $ (A1L04 & J3L13)) & A1L93;
J3_q[15] = DFFEA(J3_q[15]_lut_out, F1L93, , , A1L04, , );

--J3L33 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[15]~COUT
--operation mode is clrb_cntr

J3L33 = CARRY(J3_q[15] & J3L13);


--J3_q[13] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[13]
--operation mode is clrb_cntr

J3_q[13]_lut_out = (J3_q[13] $ (A1L04 & J3L72)) & A1L93;
J3_q[13] = DFFEA(J3_q[13]_lut_out, F1L93, , , A1L04, , );

--J3L92 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[13]~COUT
--operation mode is clrb_cntr

J3L92 = CARRY(J3_q[13] & J3L72);


--J3_q[21] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[21]
--operation mode is clrb_cntr

J3_q[21]_lut_out = (J3_q[21] $ (A1L04 & J3L34)) & A1L93;
J3_q[21] = DFFEA(J3_q[21]_lut_out, F1L93, , , A1L04, , );

--J3L54 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[21]~COUT
--operation mode is clrb_cntr

J3L54 = CARRY(J3_q[21] & J3L34);


--J3_q[20] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[20]
--operation mode is clrb_cntr

J3_q[20]_lut_out = (J3_q[20] $ (A1L04 & J3L14)) & A1L93;
J3_q[20] = DFFEA(J3_q[20]_lut_out, F1L93, , , A1L04, , );

--J3L34 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[20]~COUT
--operation mode is clrb_cntr

J3L34 = CARRY(J3_q[20] & J3L14);


--G1L8 is sum_control:inst5|out_control~242
--operation mode is normal

G1L8 = !J3_q[20] # !J3_q[21] # !J3_q[13] # !J3_q[15];


--J3_q[18] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[18]
--operation mode is clrb_cntr

J3_q[18]_lut_out = (J3_q[18] $ (A1L04 & J3L73)) & A1L93;
J3_q[18] = DFFEA(J3_q[18]_lut_out, F1L93, , , A1L04, , );

--J3L93 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[18]~COUT
--operation mode is clrb_cntr

J3L93 = CARRY(J3_q[18] & J3L73);


--J3_q[5] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

J3_q[5]_lut_out = (J3_q[5] $ (A1L04 & J3L11)) & A1L93;
J3_q[5] = DFFEA(J3_q[5]_lut_out, F1L93, , , A1L04, , );

--J3L31 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is clrb_cntr

J3L31 = CARRY(J3_q[5] & J3L11);


--J3_q[19] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[19]
--operation mode is clrb_cntr

J3_q[19]_lut_out = (J3_q[19] $ (A1L04 & J3L93)) & A1L93;
J3_q[19] = DFFEA(J3_q[19]_lut_out, F1L93, , , A1L04, , );

--J3L14 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[19]~COUT
--operation mode is clrb_cntr

J3L14 = CARRY(J3_q[19] & J3L93);


--J3_q[23] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23]
--operation mode is clrb_cntr

J3_q[23]_lut_out = (J3_q[23] $ (A1L04 & J3L74)) & A1L93;
J3_q[23] = DFFEA(J3_q[23]_lut_out, F1L93, , , A1L04, , );


--G1L9 is sum_control:inst5|out_control~243
--operation mode is normal

G1L9 = !J3_q[23] # !J3_q[19] # !J3_q[5] # !J3_q[18];


--J3_q[3] is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

J3_q[3]_lut_out = (J3_q[3] $ (A1L04 & J3L7)) & A1L93;
J3_q[3] = DFFEA(J3_q[3]_lut_out, F1L93, , , A1L04, , );

--J3L9 is sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is clrb_cntr

J3L9 = CARRY(J3_q[3] & J3L7);


--G1L2 is sum_control:inst5|out_control~4
--operation mode is normal

G1L2 = G1L7 # G1L8 # G1L9 # !J3_q[3];


--G1L11 is sum_control:inst5|reduce_nor~267
--operation mode is normal

G1L11 = !G1L12 # !G1L02 # !G1L91 # !G1L81;


--G1L01 is sum_control:inst5|out_control~246
--operation mode is normal

G1L01 = (!Reset & G1L11 # !G1L32 # !G1L22) & CASCADE(G1L2);


--J1_q[19] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[19]
--operation mode is clrb_cntr

J1_q[19]_lut_out = (J1_q[19] $ J1L93) & B1L1;
J1_q[19] = DFFEA(J1_q[19]_lut_out, Clock_8MHz, , , , , );

--J1L14 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[19]~COUT
--operation mode is clrb_cntr

J1L14 = CARRY(J1_q[19] & J1L93);


--E1_second_pulse_out[10] is second_pulse_latch:inst3|second_pulse_out[10]
--operation mode is normal

E1_second_pulse_out[10]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[11] # !Acceleration[16] & N6_cs_buffer[10];
E1_second_pulse_out[10] = DFFEA(E1_second_pulse_out[10]_lut_out, J1_q[3], , , , , );


--F1L72 is pulse_sum:inst4|pulse_1~21
--operation mode is normal

F1L72 = F1L23 & E1_second_pulse_out[10] & J2_q[5] & !J2_q[4];


--F1_pulse_1[10] is pulse_sum:inst4|pulse_1[10]
--operation mode is normal

F1_pulse_1[10] = Reset & F1_pulse_1[10] # !Reset & F1L72;


--E1_second_pulse_out[9] is second_pulse_latch:inst3|second_pulse_out[9]
--operation mode is normal

E1_second_pulse_out[9]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[10] # !Acceleration[16] & N6_cs_buffer[9];
E1_second_pulse_out[9] = DFFEA(E1_second_pulse_out[9]_lut_out, J1_q[3], , , , , );


--F1L62 is pulse_sum:inst4|pulse_1~19
--operation mode is normal

F1L62 = F1L33 & E1_second_pulse_out[9] & J2_q[6];


--F1_pulse_1[9] is pulse_sum:inst4|pulse_1[9]
--operation mode is normal

F1_pulse_1[9] = Reset & F1_pulse_1[9] # !Reset & F1L62;


--E1_second_pulse_out[8] is second_pulse_latch:inst3|second_pulse_out[8]
--operation mode is normal

E1_second_pulse_out[8]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[9] # !Acceleration[16] & N6_cs_buffer[8];
E1_second_pulse_out[8] = DFFEA(E1_second_pulse_out[8]_lut_out, J1_q[3], , , , , );


--F1L52 is pulse_sum:inst4|pulse_1~17
--operation mode is normal

F1L52 = F1L33 & E1_second_pulse_out[8] & J2_q[7] & !J2_q[6];


--F1_pulse_1[8] is pulse_sum:inst4|pulse_1[8]
--operation mode is normal

F1_pulse_1[8] = Reset & F1_pulse_1[8] # !Reset & F1L52;


--E1_second_pulse_out[7] is second_pulse_latch:inst3|second_pulse_out[7]
--operation mode is normal

E1_second_pulse_out[7]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[8] # !Acceleration[16] & N6_cs_buffer[7];
E1_second_pulse_out[7] = DFFEA(E1_second_pulse_out[7]_lut_out, J1_q[3], , , , , );


--F1L42 is pulse_sum:inst4|pulse_1~15
--operation mode is normal

F1L42 = F1L43 & E1_second_pulse_out[7] & J2_q[8];


--F1_pulse_1[7] is pulse_sum:inst4|pulse_1[7]
--operation mode is normal

F1_pulse_1[7] = Reset & F1_pulse_1[7] # !Reset & F1L42;


--E1_second_pulse_out[14] is second_pulse_latch:inst3|second_pulse_out[14]
--operation mode is normal

E1_second_pulse_out[14]_lut_out = !Reset & Acceleration[16] & !L1_unreg_res_node[15] # !Acceleration[16] & L2_unreg_res_node[14];
E1_second_pulse_out[14] = DFFEA(E1_second_pulse_out[14]_lut_out, J1_q[3], , , , , );


--F1L83 is pulse_sum:inst4|pulse_1~425
--operation mode is normal

F1L83 = J1_q[1] & E1_second_pulse_out[14] & J2_q[1] & !J2_q[0];


--F1_pulse_1[14] is pulse_sum:inst4|pulse_1[14]
--operation mode is normal

F1_pulse_1[14] = Reset & F1_pulse_1[14] # !Reset & F1L83;


--E1_second_pulse_out[13] is second_pulse_latch:inst3|second_pulse_out[13]
--operation mode is normal

E1_second_pulse_out[13]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[14] # !Acceleration[16] & N6_cs_buffer[13];
E1_second_pulse_out[13] = DFFEA(E1_second_pulse_out[13]_lut_out, J1_q[3], , , , , );


--F1L03 is pulse_sum:inst4|pulse_1~27
--operation mode is normal

F1L03 = J2_q[2] & E1_second_pulse_out[13] & F1L13;


--F1_pulse_1[13] is pulse_sum:inst4|pulse_1[13]
--operation mode is normal

F1_pulse_1[13] = Reset & F1_pulse_1[13] # !Reset & F1L03;


--E1_second_pulse_out[12] is second_pulse_latch:inst3|second_pulse_out[12]
--operation mode is normal

E1_second_pulse_out[12]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[13] # !Acceleration[16] & N6_cs_buffer[12];
E1_second_pulse_out[12] = DFFEA(E1_second_pulse_out[12]_lut_out, J1_q[3], , , , , );


--F1L92 is pulse_sum:inst4|pulse_1~25
--operation mode is normal

F1L92 = F1L13 & E1_second_pulse_out[12] & J2_q[3] & !J2_q[2];


--F1_pulse_1[12] is pulse_sum:inst4|pulse_1[12]
--operation mode is normal

F1_pulse_1[12] = Reset & F1_pulse_1[12] # !Reset & F1L92;


--E1_second_pulse_out[11] is second_pulse_latch:inst3|second_pulse_out[11]
--operation mode is normal

E1_second_pulse_out[11]_lut_out = !Reset & Acceleration[16] & !N3_cs_buffer[12] # !Acceleration[16] & N6_cs_buffer[11];
E1_second_pulse_out[11] = DFFEA(E1_second_pulse_out[11]_lut_out, J1_q[3], , , , , );


--F1L82 is pulse_sum:inst4|pulse_1~23
--operation mode is normal

F1L82 = F1L23 & E1_second_pulse_out[11] & J2_q[4];


--F1_pulse_1[11] is pulse_sum:inst4|pulse_1[11]
--operation mode is normal

F1_pulse_1[11] = Reset & F1_pulse_1[11] # !Reset & F1L82;


--A1L04 is rtl~0
--operation mode is normal

A1L04 = Reset # G1L11 # !G1L32 # !G1L22;


--J1_q[18] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[18]
--operation mode is clrb_cntr

J1_q[18]_lut_out = (J1_q[18] $ J1L73) & B1L1;
J1_q[18] = DFFEA(J1_q[18]_lut_out, Clock_8MHz, , , , , );

--J1L93 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[18]~COUT
--operation mode is clrb_cntr

J1L93 = CARRY(J1_q[18] & J1L73);


--J1_q[15] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[15]
--operation mode is clrb_cntr

J1_q[15]_lut_out = (J1_q[15] $ J1L13) & B1L1;
J1_q[15] = DFFEA(J1_q[15]_lut_out, Clock_8MHz, , , , , );

--J1L33 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[15]~COUT
--operation mode is clrb_cntr

J1L33 = CARRY(J1_q[15] & J1L13);


--J1_q[14] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[14]
--operation mode is clrb_cntr

J1_q[14]_lut_out = (J1_q[14] $ J1L92) & B1L1;
J1_q[14] = DFFEA(J1_q[14]_lut_out, Clock_8MHz, , , , , );

--J1L13 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[14]~COUT
--operation mode is clrb_cntr

J1L13 = CARRY(J1_q[14] & J1L92);


--J1_q[13] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[13]
--operation mode is clrb_cntr

J1_q[13]_lut_out = (J1_q[13] $ J1L72) & B1L1;
J1_q[13] = DFFEA(J1_q[13]_lut_out, Clock_8MHz, , , , , );

--J1L92 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[13]~COUT
--operation mode is clrb_cntr

J1L92 = CARRY(J1_q[13] & J1L72);


--J1_q[12] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[12]
--operation mode is clrb_cntr

J1_q[12]_lut_out = (J1_q[12] $ J1L52) & B1L1;
J1_q[12] = DFFEA(J1_q[12]_lut_out, Clock_8MHz, , , , , );

--J1L72 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[12]~COUT
--operation mode is clrb_cntr

J1L72 = CARRY(J1_q[12] & J1L52);


--B1L3 is fdiv:inst|CNT~259
--operation mode is normal

B1L3 = !J1_q[15] & !J1_q[14] & !J1_q[13] & !J1_q[12];


--J1_q[17] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[17]
--operation mode is clrb_cntr

J1_q[17]_lut_out = (J1_q[17] $ J1L53) & B1L1;
J1_q[17] = DFFEA(J1_q[17]_lut_out, Clock_8MHz, , , , , );

--J1L73 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[17]~COUT
--operation mode is clrb_cntr

J1L73 = CARRY(J1_q[17] & J1L53);


--J1_q[16] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[16]
--operation mode is clrb_cntr

J1_q[16]_lut_out = (J1_q[16] $ J1L33) & B1L1;
J1_q[16] = DFFEA(J1_q[16]_lut_out, Clock_8MHz, , , , , );

--J1L53 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[16]~COUT
--operation mode is clrb_cntr

J1L53 = CARRY(J1_q[16] & J1L33);


--B1L5 is fdiv:inst|CNT~263
--operation mode is normal

B1L5 = (!J1_q[19] & !J1_q[18] & !J1_q[17] & !J1_q[16]) & CASCADE(B1L3);


--J1_q[7] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[7]
--operation mode is clrb_cntr

J1_q[7]_lut_out = (J1_q[7] $ J1L51) & B1L1;
J1_q[7] = DFFEA(J1_q[7]_lut_out, Clock_8MHz, , , , , );

--J1L71 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[7]~COUT
--operation mode is clrb_cntr

J1L71 = CARRY(J1_q[7] & J1L51);


--J1_q[6] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[6]
--operation mode is clrb_cntr

J1_q[6]_lut_out = (J1_q[6] $ J1L31) & B1L1;
J1_q[6] = DFFEA(J1_q[6]_lut_out, Clock_8MHz, , , , , );

--J1L51 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT
--operation mode is clrb_cntr

J1L51 = CARRY(J1_q[6] & J1L31);


--J1_q[5] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is clrb_cntr

J1_q[5]_lut_out = (J1_q[5] $ J1L11) & B1L1;
J1_q[5] = DFFEA(J1_q[5]_lut_out, Clock_8MHz, , , , , );

--J1L31 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT
--operation mode is clrb_cntr

J1L31 = CARRY(J1_q[5] & J1L11);


--J1_q[4] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is clrb_cntr

J1_q[4]_lut_out = (J1_q[4] $ J1L9) & B1L1;
J1_q[4] = DFFEA(J1_q[4]_lut_out, Clock_8MHz, , , , , );

--J1L11 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is clrb_cntr

J1L11 = CARRY(J1_q[4] & J1L9);


--B1L4 is fdiv:inst|CNT~261
--operation mode is normal

B1L4 = !J1_q[7] & !J1_q[6] & !J1_q[5] & !J1_q[4];


--J1_q[11] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[11]
--operation mode is clrb_cntr

J1_q[11]_lut_out = (J1_q[11] $ J1L32) & B1L1;
J1_q[11] = DFFEA(J1_q[11]_lut_out, Clock_8MHz, , , , , );

--J1L52 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[11]~COUT
--operation mode is clrb_cntr

J1L52 = CARRY(J1_q[11] & J1L32);


--J1_q[10] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[10]
--operation mode is clrb_cntr

J1_q[10]_lut_out = (J1_q[10] $ J1L12) & B1L1;
J1_q[10] = DFFEA(J1_q[10]_lut_out, Clock_8MHz, , , , , );

--J1L32 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[10]~COUT
--operation mode is clrb_cntr

J1L32 = CARRY(J1_q[10] & J1L12);


--J1_q[9] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[9]
--operation mode is clrb_cntr

J1_q[9]_lut_out = (J1_q[9] $ J1L91) & B1L1;
J1_q[9] = DFFEA(J1_q[9]_lut_out, Clock_8MHz, , , , , );

--J1L12 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[9]~COUT
--operation mode is clrb_cntr

J1L12 = CARRY(J1_q[9] & J1L91);


--J1_q[8] is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|q[8]
--operation mode is clrb_cntr

J1_q[8]_lut_out = (J1_q[8] $ J1L71) & B1L1;
J1_q[8] = DFFEA(J1_q[8]_lut_out, Clock_8MHz, , , , , );

--J1L91 is fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[8]~COUT
--operation mode is clrb_cntr

J1L91 = CARRY(J1_q[8] & J1L71);


--B1L6 is fdiv:inst|CNT~264
--operation mode is normal

B1L6 = (!J1_q[11] & !J1_q[10] & !J1_q[9] & !J1_q[8]) & CASCADE(B1L4);


--N6_cs_buffer[10] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]
--operation mode is arithmetic

N6_cs_buffer[10] = Acceleration[10] $ E1_second_pulse_out[10] $ N6_cout[9];

--N6_cout[10] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[10]
--operation mode is arithmetic

N6_cout[10] = CARRY(Acceleration[10] & E1_second_pulse_out[10] # N6_cout[9] # !Acceleration[10] & E1_second_pulse_out[10] & N6_cout[9]);


--N3_cs_buffer[11] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]
--operation mode is arithmetic

N3_cs_buffer[11] = Acceleration[10] $ E1_second_pulse_out[10] $ N3_cout[10];

--N3_cout[11] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[11]
--operation mode is arithmetic

N3_cout[11] = CARRY(Acceleration[10] & E1_second_pulse_out[10] & N3_cout[10] # !Acceleration[10] & E1_second_pulse_out[10] # N3_cout[10]);


--N6_cs_buffer[9] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]
--operation mode is arithmetic

N6_cs_buffer[9] = Acceleration[9] $ E1_second_pulse_out[9] $ N6_cout[8];

--N6_cout[9] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[9]
--operation mode is arithmetic

N6_cout[9] = CARRY(Acceleration[9] & E1_second_pulse_out[9] # N6_cout[8] # !Acceleration[9] & E1_second_pulse_out[9] & N6_cout[8]);


--N3_cs_buffer[10] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]
--operation mode is arithmetic

N3_cs_buffer[10] = Acceleration[9] $ E1_second_pulse_out[9] $ N3_cout[9];

--N3_cout[10] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[10]
--operation mode is arithmetic

N3_cout[10] = CARRY(Acceleration[9] & E1_second_pulse_out[9] & N3_cout[9] # !Acceleration[9] & E1_second_pulse_out[9] # N3_cout[9]);


--N6_cs_buffer[8] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]
--operation mode is arithmetic

N6_cs_buffer[8] = Acceleration[8] $ E1_second_pulse_out[8] $ N6_cout[7];

--N6_cout[8] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[8]
--operation mode is arithmetic

N6_cout[8] = CARRY(Acceleration[8] & E1_second_pulse_out[8] # N6_cout[7] # !Acceleration[8] & E1_second_pulse_out[8] & N6_cout[7]);


--N3_cs_buffer[9] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]
--operation mode is arithmetic

N3_cs_buffer[9] = Acceleration[8] $ E1_second_pulse_out[8] $ N3_cout[8];

--N3_cout[9] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[9]
--operation mode is arithmetic

N3_cout[9] = CARRY(Acceleration[8] & E1_second_pulse_out[8] & N3_cout[8] # !Acceleration[8] & E1_second_pulse_out[8] # N3_cout[8]);


--N6_cs_buffer[7] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]
--operation mode is arithmetic

N6_cs_buffer[7] = Acceleration[7] $ E1_second_pulse_out[7] $ N6_cout[6];

--N6_cout[7] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[7]
--operation mode is arithmetic

N6_cout[7] = CARRY(Acceleration[7] & E1_second_pulse_out[7] # N6_cout[6] # !Acceleration[7] & E1_second_pulse_out[7] & N6_cout[6]);


--N3_cs_buffer[8] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]
--operation mode is arithmetic

N3_cs_buffer[8] = Acceleration[7] $ E1_second_pulse_out[7] $ N3_cout[7];

--N3_cout[8] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[8]
--operation mode is arithmetic

N3_cout[8] = CARRY(Acceleration[7] & E1_second_pulse_out[7] & N3_cout[7] # !Acceleration[7] & E1_second_pulse_out[7] # N3_cout[7]);


--N6_cs_buffer[13] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]
--operation mode is arithmetic

N6_cs_buffer[13] = Acceleration[13] $ E1_second_pulse_out[13] $ N6_cout[12];

--N6_cout[13] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[13]
--operation mode is arithmetic

N6_cout[13] = CARRY(Acceleration[13] & E1_second_pulse_out[13] # N6_cout[12] # !Acceleration[13] & E1_second_pulse_out[13] & N6_cout[12]);


--N3_cs_buffer[14] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]
--operation mode is arithmetic

N3_cs_buffer[14] = Acceleration[13] $ E1_second_pulse_out[13] $ N3_cout[13];

--N3_cout[14] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[14]
--operation mode is arithmetic

N3_cout[14] = CARRY(Acceleration[13] & E1_second_pulse_out[13] & N3_cout[13] # !Acceleration[13] & E1_second_pulse_out[13] # N3_cout[13]);


--N6_cs_buffer[12] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]
--operation mode is arithmetic

N6_cs_buffer[12] = Acceleration[12] $ E1_second_pulse_out[12] $ N6_cout[11];

--N6_cout[12] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[12]
--operation mode is arithmetic

N6_cout[12] = CARRY(Acceleration[12] & E1_second_pulse_out[12] # N6_cout[11] # !Acceleration[12] & E1_second_pulse_out[12] & N6_cout[11]);


--N3_cs_buffer[13] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]
--operation mode is arithmetic

N3_cs_buffer[13] = Acceleration[12] $ E1_second_pulse_out[12] $ N3_cout[12];

--N3_cout[13] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[13]
--operation mode is arithmetic

N3_cout[13] = CARRY(Acceleration[12] & E1_second_pulse_out[12] & N3_cout[12] # !Acceleration[12] & E1_second_pulse_out[12] # N3_cout[12]);


--N6_cs_buffer[11] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]
--operation mode is arithmetic

N6_cs_buffer[11] = Acceleration[11] $ E1_second_pulse_out[11] $ N6_cout[10];

--N6_cout[11] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[11]
--operation mode is arithmetic

N6_cout[11] = CARRY(Acceleration[11] & E1_second_pulse_out[11] # N6_cout[10] # !Acceleration[11] & E1_second_pulse_out[11] & N6_cout[10]);


--N3_cs_buffer[12] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]
--operation mode is arithmetic

N3_cs_buffer[12] = Acceleration[11] $ E1_second_pulse_out[11] $ N3_cout[11];

--N3_cout[12] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[12]
--operation mode is arithmetic

N3_cout[12] = CARRY(Acceleration[11] & E1_second_pulse_out[11] & N3_cout[11] # !Acceleration[11] & E1_second_pulse_out[11] # N3_cout[11]);


--N9_cs_buffer[17] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[17]
--operation mode is arithmetic

N9_cs_buffer[17] = Step_Sum[17] $ (N9_cout[16]);

--N9_cout[17] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[17]
--operation mode is arithmetic

N9_cout[17] = CARRY(Step_Sum[17] # N9_cout[16]);


--N9_cs_buffer[7] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]
--operation mode is arithmetic

N9_cs_buffer[7] = Step_Sum[7] $ (N9_cout[6]);

--N9_cout[7] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[7]
--operation mode is arithmetic

N9_cout[7] = CARRY(Step_Sum[7] # N9_cout[6]);


--G1L21 is sum_control:inst5|reduce_nor~282
--operation mode is normal

G1L21 = N9_cs_buffer[17] & !J3_q[17] & N9_cs_buffer[7] $ J3_q[7] # !N9_cs_buffer[17] & J3_q[17] & N9_cs_buffer[7] $ J3_q[7];


--N9_cs_buffer[22] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[22]
--operation mode is arithmetic

N9_cs_buffer[22] = Step_Sum[22] $ (N9_cout[21]);

--N9_cout[22] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[22]
--operation mode is arithmetic

N9_cout[22] = CARRY(Step_Sum[22] # N9_cout[21]);


--N9_cs_buffer[10] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]
--operation mode is arithmetic

N9_cs_buffer[10] = Step_Sum[10] $ (N9_cout[9]);

--N9_cout[10] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[10]
--operation mode is arithmetic

N9_cout[10] = CARRY(Step_Sum[10] # N9_cout[9]);


--G1L81 is sum_control:inst5|reduce_nor~294
--operation mode is normal

G1L81 = (N9_cs_buffer[22] & !J3_q[22] & N9_cs_buffer[10] $ J3_q[10] # !N9_cs_buffer[22] & J3_q[22] & N9_cs_buffer[10] $ J3_q[10]) & CASCADE(G1L21);


--N9_cs_buffer[4] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

N9_cs_buffer[4] = Step_Sum[4] $ (N9_cout[3]);

--N9_cout[4] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

N9_cout[4] = CARRY(Step_Sum[4] # N9_cout[3]);


--N9_cs_buffer[15] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[15]
--operation mode is arithmetic

N9_cs_buffer[15] = Step_Sum[15] $ (N9_cout[14]);

--N9_cout[15] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[15]
--operation mode is arithmetic

N9_cout[15] = CARRY(Step_Sum[15] # N9_cout[14]);


--G1L31 is sum_control:inst5|reduce_nor~284
--operation mode is normal

G1L31 = N9_cs_buffer[4] & !J3_q[4] & N9_cs_buffer[15] $ J3_q[15] # !N9_cs_buffer[4] & J3_q[4] & N9_cs_buffer[15] $ J3_q[15];


--N9_cs_buffer[2] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

N9_cs_buffer[2] = Step_Sum[2] $ (N9_cout[1]);

--N9_cout[2] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

N9_cout[2] = CARRY(Step_Sum[2] # N9_cout[1]);


--N9_cs_buffer[0] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]
--operation mode is arithmetic

N9_cs_buffer[0] = Step_Sum[0];

--N9_cout[0] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

N9_cout[0] = CARRY(Step_Sum[0]);


--G1L91 is sum_control:inst5|reduce_nor~295
--operation mode is normal

G1L91 = (N9_cs_buffer[2] & !J3_q[2] & N9_cs_buffer[0] $ J3_q[0] # !N9_cs_buffer[2] & J3_q[2] & N9_cs_buffer[0] $ J3_q[0]) & CASCADE(G1L31);


--N9_cs_buffer[20] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[20]
--operation mode is arithmetic

N9_cs_buffer[20] = Step_Sum[20] $ (N9_cout[19]);

--N9_cout[20] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[20]
--operation mode is arithmetic

N9_cout[20] = CARRY(Step_Sum[20] # N9_cout[19]);


--N9_cs_buffer[18] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[18]
--operation mode is arithmetic

N9_cs_buffer[18] = Step_Sum[18] $ (N9_cout[17]);

--N9_cout[18] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[18]
--operation mode is arithmetic

N9_cout[18] = CARRY(Step_Sum[18] # N9_cout[17]);


--G1L41 is sum_control:inst5|reduce_nor~286
--operation mode is normal

G1L41 = N9_cs_buffer[20] & !J3_q[20] & N9_cs_buffer[18] $ J3_q[18] # !N9_cs_buffer[20] & J3_q[20] & N9_cs_buffer[18] $ J3_q[18];


--N9_cs_buffer[13] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]
--operation mode is arithmetic

N9_cs_buffer[13] = Step_Sum[13] $ (N9_cout[12]);

--N9_cout[13] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[13]
--operation mode is arithmetic

N9_cout[13] = CARRY(Step_Sum[13] # N9_cout[12]);


--N9_cs_buffer[21] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[21]
--operation mode is arithmetic

N9_cs_buffer[21] = Step_Sum[21] $ (N9_cout[20]);

--N9_cout[21] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[21]
--operation mode is arithmetic

N9_cout[21] = CARRY(Step_Sum[21] # N9_cout[20]);


--G1L02 is sum_control:inst5|reduce_nor~296
--operation mode is normal

G1L02 = (N9_cs_buffer[13] & !J3_q[13] & N9_cs_buffer[21] $ J3_q[21] # !N9_cs_buffer[13] & J3_q[13] & N9_cs_buffer[21] $ J3_q[21]) & CASCADE(G1L41);


--N9_cs_buffer[3] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

N9_cs_buffer[3] = Step_Sum[3] $ (N9_cout[2]);

--N9_cout[3] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

N9_cout[3] = CARRY(Step_Sum[3] # N9_cout[2]);


--G1L51 is sum_control:inst5|reduce_nor~288
--operation mode is normal

G1L51 = L3_unreg_res_node[23] & !J3_q[23] & N9_cs_buffer[3] $ J3_q[3] # !L3_unreg_res_node[23] & J3_q[23] & N9_cs_buffer[3] $ J3_q[3];


--N9_cs_buffer[5] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

N9_cs_buffer[5] = Step_Sum[5] $ (N9_cout[4]);

--N9_cout[5] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

N9_cout[5] = CARRY(Step_Sum[5] # N9_cout[4]);


--N9_cs_buffer[19] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[19]
--operation mode is arithmetic

N9_cs_buffer[19] = Step_Sum[19] $ (N9_cout[18]);

--N9_cout[19] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[19]
--operation mode is arithmetic

N9_cout[19] = CARRY(Step_Sum[19] # N9_cout[18]);


--G1L12 is sum_control:inst5|reduce_nor~297
--operation mode is normal

G1L12 = (N9_cs_buffer[5] & !J3_q[5] & N9_cs_buffer[19] $ J3_q[19] # !N9_cs_buffer[5] & J3_q[5] & N9_cs_buffer[19] $ J3_q[19]) & CASCADE(G1L51);


--N9_cs_buffer[9] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]
--operation mode is arithmetic

N9_cs_buffer[9] = Step_Sum[9] $ (N9_cout[8]);

--N9_cout[9] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[9]
--operation mode is arithmetic

N9_cout[9] = CARRY(Step_Sum[9] # N9_cout[8]);


--N9_cs_buffer[12] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]
--operation mode is arithmetic

N9_cs_buffer[12] = Step_Sum[12] $ (N9_cout[11]);

--N9_cout[12] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[12]
--operation mode is arithmetic

N9_cout[12] = CARRY(Step_Sum[12] # N9_cout[11]);


--G1L61 is sum_control:inst5|reduce_nor~290
--operation mode is normal

G1L61 = N9_cs_buffer[9] & !J3_q[9] & N9_cs_buffer[12] $ J3_q[12] # !N9_cs_buffer[9] & J3_q[9] & N9_cs_buffer[12] $ J3_q[12];


--N9_cs_buffer[8] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]
--operation mode is arithmetic

N9_cs_buffer[8] = Step_Sum[8] $ (N9_cout[7]);

--N9_cout[8] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[8]
--operation mode is arithmetic

N9_cout[8] = CARRY(Step_Sum[8] # N9_cout[7]);


--N9_cs_buffer[16] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[16]
--operation mode is arithmetic

N9_cs_buffer[16] = Step_Sum[16] $ (N9_cout[15]);

--N9_cout[16] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[16]
--operation mode is arithmetic

N9_cout[16] = CARRY(Step_Sum[16] # N9_cout[15]);


--G1L22 is sum_control:inst5|reduce_nor~298
--operation mode is normal

G1L22 = (N9_cs_buffer[8] & !J3_q[8] & N9_cs_buffer[16] $ J3_q[16] # !N9_cs_buffer[8] & J3_q[8] & N9_cs_buffer[16] $ J3_q[16]) & CASCADE(G1L61);


--N9_cs_buffer[14] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]
--operation mode is arithmetic

N9_cs_buffer[14] = Step_Sum[14] $ (N9_cout[13]);

--N9_cout[14] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[14]
--operation mode is arithmetic

N9_cout[14] = CARRY(Step_Sum[14] # N9_cout[13]);


--N9_cs_buffer[6] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]
--operation mode is arithmetic

N9_cs_buffer[6] = Step_Sum[6] $ (N9_cout[5]);

--N9_cout[6] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

N9_cout[6] = CARRY(Step_Sum[6] # N9_cout[5]);


--G1L71 is sum_control:inst5|reduce_nor~292
--operation mode is normal

G1L71 = N9_cs_buffer[14] & !J3_q[14] & N9_cs_buffer[6] $ J3_q[6] # !N9_cs_buffer[14] & J3_q[14] & N9_cs_buffer[6] $ J3_q[6];


--N9_cs_buffer[11] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]
--operation mode is arithmetic

N9_cs_buffer[11] = Step_Sum[11] $ (N9_cout[10]);

--N9_cout[11] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[11]
--operation mode is arithmetic

N9_cout[11] = CARRY(Step_Sum[11] # N9_cout[10]);


--N9_cs_buffer[1] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

N9_cs_buffer[1] = Step_Sum[1] $ (N9_cout[0]);

--N9_cout[1] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

N9_cout[1] = CARRY(Step_Sum[1] # N9_cout[0]);


--G1L32 is sum_control:inst5|reduce_nor~299
--operation mode is normal

G1L32 = (N9_cs_buffer[11] & !J3_q[11] & N9_cs_buffer[1] $ J3_q[1] # !N9_cs_buffer[11] & J3_q[11] & N9_cs_buffer[1] $ J3_q[1]) & CASCADE(G1L71);


--L2_unreg_res_node[14] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|unreg_res_node[14]
--operation mode is normal

L2_unreg_res_node[14] = E1_second_pulse_out[14] $ Acceleration[14] $ N6_cout[13];


--L1_unreg_res_node[15] is second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|unreg_res_node[15]
--operation mode is normal

L1_unreg_res_node[15] = Acceleration[14] $ E1_second_pulse_out[14] $ N3_cout[14];


--L3_unreg_res_node[23] is sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|unreg_res_node[23]
--operation mode is normal

L3_unreg_res_node[23] = N9_cout[22] $ Step_Sum[23];


--Initial_Speed[15] is Initial_Speed[15]
--operation mode is input

Initial_Speed[15] = INPUT();


--Initial_Speed[14] is Initial_Speed[14]
--operation mode is input

Initial_Speed[14] = INPUT();


--Initial_Speed[13] is Initial_Speed[13]
--operation mode is input

Initial_Speed[13] = INPUT();


--Initial_Speed[12] is Initial_Speed[12]
--operation mode is input

Initial_Speed[12] = INPUT();


--Initial_Speed[11] is Initial_Speed[11]
--operation mode is input

Initial_Speed[11] = INPUT();


--Initial_Speed[10] is Initial_Speed[10]
--operation mode is input

Initial_Speed[10] = INPUT();


--Initial_Speed[9] is Initial_Speed[9]
--operation mode is input

Initial_Speed[9] = INPUT();


--Initial_Speed[8] is Initial_Speed[8]
--operation mode is input

Initial_Speed[8] = INPUT();


--Initial_Speed[7] is Initial_Speed[7]
--operation mode is input

Initial_Speed[7] = INPUT();


--Initial_Speed[6] is Initial_Speed[6]
--operation mode is input

Initial_Speed[6] = INPUT();


--Initial_Speed[5] is Initial_Speed[5]
--operation mode is input

Initial_Speed[5] = INPUT();


--Initial_Speed[4] is Initial_Speed[4]
--operation mode is input

Initial_Speed[4] = INPUT();


--Initial_Speed[3] is Initial_Speed[3]
--operation mode is input

Initial_Speed[3] = INPUT();


--Initial_Speed[2] is Initial_Speed[2]
--operation mode is input

Initial_Speed[2] = INPUT();


--Initial_Speed[1] is Initial_Speed[1]
--operation mode is input

Initial_Speed[1] = INPUT();


--Initial_Speed[0] is Initial_Speed[0]
--operation mode is input

Initial_Speed[0] = INPUT();


--Acceleration[15] is Acceleration[15]
--operation mode is input

Acceleration[15] = INPUT();


--Reset is Reset
--operation mode is input

Reset = INPUT();


--Clock_8MHz is Clock_8MHz
--operation mode is input

Clock_8MHz = INPUT();


--Acceleration[16] is Acceleration[16]
--operation mode is input

Acceleration[16] = INPUT();


--Acceleration[6] is Acceleration[6]
--operation mode is input

Acceleration[6] = INPUT();


--Acceleration[5] is Acceleration[5]
--operation mode is input

Acceleration[5] = INPUT();


--Acceleration[4] is Acceleration[4]
--operation mode is input

Acceleration[4] = INPUT();


--Acceleration[3] is Acceleration[3]
--operation mode is input

Acceleration[3] = INPUT();


--Acceleration[2] is Acceleration[2]
--operation mode is input

Acceleration[2] = INPUT();


--Acceleration[1] is Acceleration[1]
--operation mode is input

Acceleration[1] = INPUT();


--Acceleration[0] is Acceleration[0]
--operation mode is input

Acceleration[0] = INPUT();


--Acceleration[14] is Acceleration[14]
--operation mode is input

Acceleration[14] = INPUT();


--Step_Sum[23] is Step_Sum[23]
--operation mode is input

Step_Sum[23] = INPUT();


--Acceleration[10] is Acceleration[10]
--operation mode is input

Acceleration[10] = INPUT();


--Acceleration[9] is Acceleration[9]
--operation mode is input

Acceleration[9] = INPUT();


--Acceleration[8] is Acceleration[8]
--operation mode is input

Acceleration[8] = INPUT();


--Acceleration[7] is Acceleration[7]
--operation mode is input

Acceleration[7] = INPUT();


--Acceleration[13] is Acceleration[13]
--operation mode is input

Acceleration[13] = INPUT();


--Acceleration[12] is Acceleration[12]
--operation mode is input

Acceleration[12] = INPUT();


--Acceleration[11] is Acceleration[11]
--operation mode is input

Acceleration[11] = INPUT();


--Step_Sum[17] is Step_Sum[17]
--operation mode is input

Step_Sum[17] = INPUT();


--Step_Sum[7] is Step_Sum[7]
--operation mode is input

Step_Sum[7] = INPUT();


--Step_Sum[22] is Step_Sum[22]
--operation mode is input

Step_Sum[22] = INPUT();


--Step_Sum[10] is Step_Sum[10]
--operation mode is input

Step_Sum[10] = INPUT();


--Step_Sum[4] is Step_Sum[4]
--operation mode is input

Step_Sum[4] = INPUT();


--Step_Sum[15] is Step_Sum[15]
--operation mode is input

Step_Sum[15] = INPUT();


--Step_Sum[2] is Step_Sum[2]
--operation mode is input

Step_Sum[2] = INPUT();


--Step_Sum[0] is Step_Sum[0]
--operation mode is input

Step_Sum[0] = INPUT();


--Step_Sum[20] is Step_Sum[20]
--operation mode is input

Step_Sum[20] = INPUT();


--Step_Sum[18] is Step_Sum[18]
--operation mode is input

Step_Sum[18] = INPUT();


--Step_Sum[13] is Step_Sum[13]
--operation mode is input

Step_Sum[13] = INPUT();


--Step_Sum[21] is Step_Sum[21]
--operation mode is input

Step_Sum[21] = INPUT();


--Step_Sum[3] is Step_Sum[3]
--operation mode is input

Step_Sum[3] = INPUT();


--Step_Sum[5] is Step_Sum[5]
--operation mode is input

Step_Sum[5] = INPUT();


--Step_Sum[19] is Step_Sum[19]
--operation mode is input

Step_Sum[19] = INPUT();


--Step_Sum[9] is Step_Sum[9]
--operation mode is input

Step_Sum[9] = INPUT();


--Step_Sum[12] is Step_Sum[12]
--operation mode is input

Step_Sum[12] = INPUT();


--Step_Sum[8] is Step_Sum[8]
--operation mode is input

Step_Sum[8] = INPUT();


--Step_Sum[16] is Step_Sum[16]
--operation mode is input

Step_Sum[16] = INPUT();


--Step_Sum[14] is Step_Sum[14]
--operation mode is input

Step_Sum[14] = INPUT();


--Step_Sum[6] is Step_Sum[6]
--operation mode is input

Step_Sum[6] = INPUT();


--Step_Sum[11] is Step_Sum[11]
--operation mode is input

Step_Sum[11] = INPUT();


--Step_Sum[1] is Step_Sum[1]
--operation mode is input

Step_Sum[1] = INPUT();


--Pulse_Wave is Pulse_Wave
--operation mode is output

Pulse_Wave = OUTPUT(G1_wave_out);


--A1L93 is Reset~7
--operation mode is normal

A1L93 = !Reset;


