module Data_Read(
				  En,  
				  Reset,
				  Adc_Sdata,
				  Adc_SCL,				  
				  Current_Data			
    			  );
input  En;
input  Reset;
input  Adc_Sdata;
input  Adc_SCL;
output [11:0] Current_Data;

//reg [11:0] Current_Data;
reg [3:0] cnt;
reg [15:0] Data;

always @(negedge Adc_SCL)
begin
  if(cnt <= 4'b1111)
  begin
    Data[cnt] <= Adc_Sdata;
    cnt <= cnt + 4'b1;
  end
  else
    cnt <= 4'b0;  
end

assign Current_Data = Data[15:4];

endmodule


