{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 09 02:16:41 2006 " "Info: Processing started: Wed Aug 09 02:16:41 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off SRAM_8_8 -c SRAM_8_8 " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off SRAM_8_8 -c SRAM_8_8" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SRAM_8_8.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SRAM_8_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 SRAM_8_8 " "Info: Found entity 1: SRAM_8_8" {  } { { "SRAM_8_8.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/第2章/SRAM_8_8/SRAM_8_8.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "Sram SRAM_8_8.v(22) " "Warning: Verilog HDL Always Construct warning at SRAM_8_8.v(22): variable \"Sram\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "SRAM_8_8.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/第2章/SRAM_8_8/SRAM_8_8.v" 22 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "DOUT SRAM_8_8.v(12) " "Warning: Verilog HDL Always Construct warning at SRAM_8_8.v(12): variable DOUT may not be assigned a new value in every possible path through the Always Construct.  Variable DOUT holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "SRAM_8_8.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/第2章/SRAM_8_8/SRAM_8_8.v" 12 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "156 " "Info: Implemented 156 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "14 " "Info: Implemented 14 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "128 " "Info: Implemented 128 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "6 " "Info: Implemented 6 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 09 02:16:47 2006 " "Info: Processing ended: Wed Aug 09 02:16:47 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}
