{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 08 11:29:06 2006 " "Info: Processing started: Tue Aug 08 11:29:06 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off Data_Mux -c Data_Mux " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Data_Mux -c Data_Mux" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Y_2\$latch~10 " "Info: Node \"Y_2\$latch~10\"" {  } { { "Data_Mux.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Data_Mux/Data_Mux.v" 19 -1 0 } }  } 0}  } { { "Data_Mux.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Data_Mux/Data_Mux.v" 19 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "B Y_2 9.600 ns Longest " "Info: Longest tpd from source pin \"B\" to destination pin \"Y_2\" is 9.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns B 1 PIN PIN_12 8 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_12; Fanout = 8; PIN Node = 'B'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux_cmp.qrpt" Compiler "Data_Mux" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Data_Mux/" "" "" { B } "NODE_NAME" } "" } } { "Data_Mux.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Data_Mux/Data_Mux.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns Y_2\$latch\$d_and~200 2 COMB LC3 3 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC3; Fanout = 3; COMB Node = 'Y_2\$latch\$d_and~200'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux_cmp.qrpt" Compiler "Data_Mux" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Data_Mux/" "" "4.600 ns" { B Y_2$latch$d_and~200 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.400 ns Y_2\$latch~10 3 COMB LOOP LC2 3 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC2; Fanout = 3; COMB LOOP Node = 'Y_2\$latch~10'" { { "Info" "ITDB_PART_OF_SCC" "Y_2\$latch~10 LC2 " "Info: Loc. = LC2; Node \"Y_2\$latch~10\"" {  } { { "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux_cmp.qrpt" Compiler "Data_Mux" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Data_Mux/" "" "" { Y_2$latch~10 } "NODE_NAME" } "" } }  } 0}  } { { "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux_cmp.qrpt" Compiler "Data_Mux" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Data_Mux/" "" "" { Y_2$latch~10 } "NODE_NAME" } "" } } { "Data_Mux.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Data_Mux/Data_Mux.v" 19 -1 0 } } { "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux_cmp.qrpt" Compiler "Data_Mux" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Data_Mux/" "" "4.600 ns" { Y_2$latch$d_and~200 Y_2$latch~10 } "NODE_NAME" } "" } } { "Data_Mux.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Data_Mux/Data_Mux.v" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 9.600 ns Y_2 4 PIN PIN_5 0 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 9.600 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'Y_2'" {  } { { "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux_cmp.qrpt" Compiler "Data_Mux" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Data_Mux/" "" "0.200 ns" { Y_2$latch~10 Y_2 } "NODE_NAME" } "" } } { "Data_Mux.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Data_Mux/Data_Mux.v" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.600 ns 89.58 % " "Info: Total cell delay = 8.600 ns ( 89.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.42 % " "Info: Total interconnect delay = 1.000 ns ( 10.42 % )" {  } {  } 0}  } { { "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux_cmp.qrpt" Compiler "Data_Mux" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代码/第2章/Data_Mux/db/Data_Mux.quartus_db" { Floorplan "D:/戴仙金/verilog/源代码/第2章/Data_Mux/" "" "9.600 ns" { B Y_2$latch$d_and~200 Y_2$latch~10 Y_2 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "9.600 ns" { B B~out Y_2$latch$d_and~200 Y_2$latch~10 Y_2 } { 0.000ns 0.000ns 1.000ns 0.000ns 0.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 08 11:29:06 2006 " "Info: Processing ended: Tue Aug 08 11:29:06 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}
