|Now_Direction_Disp
Reset => Direction_Disp_Row1[6]$latch$s_buf.IN0
En => Direction_Disp_Row1[6]$latch$s_buf.IN1
Clock_1KHz => Direction_Disp_Row2[3]~reg0.CLK
Clock_1KHz => Direction_Disp_Row2[2]~reg0.CLK
Clock_1KHz => Direction_Disp_Row2[1]~reg0.CLK
Clock_1KHz => Direction_Disp_Row2[0]~reg0.CLK
Clock_1KHz => Direction_Disp_Row2[4]~reg0.CLK
Now_Direction[0] => reduce_nor~0.IN0
Now_Direction[0] => always1~1.IN0
Now_Direction[1] => always1~0.IN0
Now_Direction[1] => reduce_nor~1.IN0
Direction_Disp_Row1[0] <= Direction_Disp_Row1[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
Direction_Disp_Row1[1] <= Direction_Disp_Row1[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
Direction_Disp_Row1[2] <= Direction_Disp_Row1[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
Direction_Disp_Row1[3] <= Direction_Disp_Row1[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
Direction_Disp_Row1[4] <= Direction_Disp_Row1[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
Direction_Disp_Row1[5] <= Direction_Disp_Row1[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
Direction_Disp_Row1[6] <= Direction_Disp_Row1[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
Direction_Disp_Row2[0] <= Direction_Disp_Row2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Direction_Disp_Row2[1] <= Direction_Disp_Row2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Direction_Disp_Row2[2] <= Direction_Disp_Row2[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Direction_Disp_Row2[3] <= Direction_Disp_Row2[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Direction_Disp_Row2[4] <= Direction_Disp_Row2[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE


