{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 09 01:32:48 2006 " "Info: Processing started: Wed Aug 09 01:32:48 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off ROM_3_4 -c ROM_3_4 " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off ROM_3_4 -c ROM_3_4" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "A0 D0 5.000 ns Longest " "Info: Longest tpd from source pin \"A0\" to destination pin \"D0\" is 5.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns A0 1 PIN PIN_25 4 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_25; Fanout = 4; PIN Node = 'A0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/第2章/ROM_3_4/db/ROM_3_4_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/第2章/ROM_3_4/db/ROM_3_4_cmp.qrpt" Compiler "ROM_3_4" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/第2章/ROM_3_4/db/ROM_3_4.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/第2章/ROM_3_4/" "" "" { A0 } "NODE_NAME" } "" } } { "ROM_3_4.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/第2章/ROM_3_4/ROM_3_4.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns reduce_or~73 2 COMB LC5 1 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC5; Fanout = 1; COMB Node = 'reduce_or~73'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/第2章/ROM_3_4/db/ROM_3_4_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/第2章/ROM_3_4/db/ROM_3_4_cmp.qrpt" Compiler "ROM_3_4" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/第2章/ROM_3_4/db/ROM_3_4.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/第2章/ROM_3_4/" "" "4.600 ns" { A0 reduce_or~73 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.000 ns D0 3 PIN PIN_8 0 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 5.000 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'D0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/第2章/ROM_3_4/db/ROM_3_4_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/第2章/ROM_3_4/db/ROM_3_4_cmp.qrpt" Compiler "ROM_3_4" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/第2章/ROM_3_4/db/ROM_3_4.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/第2章/ROM_3_4/" "" "0.200 ns" { reduce_or~73 D0 } "NODE_NAME" } "" } } { "ROM_3_4.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/第2章/ROM_3_4/ROM_3_4.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 80.00 % " "Info: Total cell delay = 4.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 20.00 % " "Info: Total interconnect delay = 1.000 ns ( 20.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/第2章/ROM_3_4/db/ROM_3_4_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/第2章/ROM_3_4/db/ROM_3_4_cmp.qrpt" Compiler "ROM_3_4" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/第2章/ROM_3_4/db/ROM_3_4.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/第2章/ROM_3_4/" "" "5.000 ns" { A0 reduce_or~73 D0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.000 ns" { A0 A0~out reduce_or~73 D0 } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 0.200ns 3.600ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 09 01:32:49 2006 " "Info: Processing ended: Wed Aug 09 01:32:49 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}
