{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 17 23:30:15 2006 " "Info: Processing started: Mon Jul 17 23:30:15 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off main -c main " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off main -c main" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dispdecoder:inst5\|data_out\[2\]~166 " "Info: Node \"dispdecoder:inst5\|data_out\[2\]~166\"" {  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0}  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dispdecoder:inst5\|data_out\[3\]~162 " "Info: Node \"dispdecoder:inst5\|data_out\[3\]~162\"" {  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0}  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dispdecoder:inst5\|data_out\[1\]~158 " "Info: Node \"dispdecoder:inst5\|data_out\[1\]~158\"" {  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0}  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dispdecoder:inst5\|data_out\[6\]~154 " "Info: Node \"dispdecoder:inst5\|data_out\[6\]~154\"" {  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0}  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dispdecoder:inst5\|data_out\[0\]~150 " "Info: Node \"dispdecoder:inst5\|data_out\[0\]~150\"" {  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0}  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dispdecoder:inst5\|data_out\[4\]~146 " "Info: Node \"dispdecoder:inst5\|data_out\[4\]~146\"" {  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0}  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dispdecoder:inst5\|data_out\[5\]~142 " "Info: Node \"dispdecoder:inst5\|data_out\[5\]~142\"" {  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0}  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "gate_control:inst3\|fref~126 " "Info: Node \"gate_control:inst3\|fref~126\"" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0}  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "gate_control:inst3\|dp_s100hz~25 " "Info: Node \"gate_control:inst3\|dp_s100hz~25\"" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 12 -1 0 } }  } 0}  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 12 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "gate_control:inst3\|dp_s1hz~24 " "Info: Node \"gate_control:inst3\|dp_s1hz~24\"" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 12 -1 0 } }  } 0}  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 12 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "gate_control:inst3\|dp_s10hz~40 " "Info: Node \"gate_control:inst3\|dp_s10hz~40\"" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 12 -1 0 } }  } 0}  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 12 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clock " "Info: Assuming node \"Clock\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 352 -224 -56 368 "Clock" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Clock" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW2 " "Info: Assuming node \"SW2\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 264 -224 -56 280 "SW2" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW2" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW1 " "Info: Assuming node \"SW1\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 248 -224 -56 264 "SW1" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW1" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW0 " "Info: Assuming node \"SW0\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 232 -224 -56 248 "SW0" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW0" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "F_in " "Info: Assuming node \"F_in\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 56 -224 -56 72 "F_in" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "F_in" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "10 " "Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "gate_control:inst3\|wire_2 " "Info: Detected ripple clock \"gate_control:inst3\|wire_2\" as buffer" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "gate_control:inst3\|wire_2" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "gate_control:inst3\|wire_1 " "Info: Detected ripple clock \"gate_control:inst3\|wire_1\" as buffer" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "gate_control:inst3\|wire_1" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "gate_control:inst3\|always0~44 " "Info: Detected gated clock \"gate_control:inst3\|always0~44\" as buffer" {  } { { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "gate_control:inst3\|always0~44" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "gate_control:inst3\|fref~126 " "Info: Detected gated clock \"gate_control:inst3\|fref~126\" as buffer" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "gate_control:inst3\|fref~126" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "gate_control:inst3\|fref~114 " "Info: Detected gated clock \"gate_control:inst3\|fref~114\" as buffer" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "gate_control:inst3\|fref~114" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "gate_control:inst3\|fref~120 " "Info: Detected gated clock \"gate_control:inst3\|fref~120\" as buffer" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "gate_control:inst3\|fref~120" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst1\|f1hz " "Info: Detected ripple clock \"fdiv:inst1\|f1hz\" as buffer" {  } { { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fdiv:inst1\|f1hz" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst1\|f10hz " "Info: Detected ripple clock \"fdiv:inst1\|f10hz\" as buffer" {  } { { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fdiv:inst1\|f10hz" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst1\|f100hz " "Info: Detected ripple clock \"fdiv:inst1\|f100hz\" as buffer" {  } { { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fdiv:inst1\|f100hz" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst1\|f1khz " "Info: Detected ripple clock \"fdiv:inst1\|f1khz\" as buffer" {  } { { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fdiv:inst1\|f1khz" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clock register gate_control:inst3\|wire_1 register gate_control:inst3\|wire_2 17.12 MHz 58.4 ns Internal " "Info: Clock \"Clock\" has Internal fmax of 17.12 MHz between source register \"gate_control:inst3\|wire_1\" and destination register \"gate_control:inst3\|wire_2\" (period= 58.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns gate_control:inst3\|wire_1 1 REG LC193 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.600 ns) 6.000 ns gate_control:inst3\|wire_2 2 REG LC201 24 " "Info: 2: + IC(3.400 ns) + CELL(2.600 ns) = 6.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 43.33 % " "Info: Total cell delay = 2.600 ns ( 43.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.400 ns 56.67 % " "Info: Total interconnect delay = 3.400 ns ( 56.67 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } { 0.000ns 3.400ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-21.000 ns - Smallest " "Info: - Smallest clock skew is -21.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 31.000 ns + Shortest register " "Info: + Shortest clock path from clock \"Clock\" to destination register is 31.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns Clock 1 CLK PIN_181 33 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_181; Fanout = 33; CLK Node = 'Clock'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { Clock } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 352 -224 -56 368 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 4.200 ns fdiv:inst1\|f1khz 2 REG LC225 42 " "Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 4.200 ns; Loc. = LC225; Fanout = 42; REG Node = 'fdiv:inst1\|f1khz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "1.400 ns" { Clock fdiv:inst1|f1khz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(4.000 ns) 11.500 ns fdiv:inst1\|f100hz 3 REG LC115 34 " "Info: 3: + IC(3.300 ns) + CELL(4.000 ns) = 11.500 ns; Loc. = LC115; Fanout = 34; REG Node = 'fdiv:inst1\|f100hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "7.300 ns" { fdiv:inst1|f1khz fdiv:inst1|f100hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(3.700 ns) 18.400 ns gate_control:inst3\|fref~114 4 COMB LC203 3 " "Info: 4: + IC(3.200 ns) + CELL(3.700 ns) = 18.400 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3\|fref~114'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.900 ns" { fdiv:inst1|f100hz gate_control:inst3|fref~114 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 25.100 ns gate_control:inst3\|fref~126 5 COMB LOOP LC205 4 " "Info: 5: + IC(0.000 ns) + CELL(6.700 ns) = 25.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~114 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 31.000 ns gate_control:inst3\|wire_2 6 REG LC201 24 " "Info: 6: + IC(3.000 ns) + CELL(2.900 ns) = 31.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.500 ns 69.35 % " "Info: Total cell delay = 21.500 ns ( 69.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.500 ns 30.65 % " "Info: Total interconnect delay = 9.500 ns ( 30.65 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "31.000 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "31.000 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.300ns 3.200ns 0.000ns 3.000ns } { 0.000ns 2.800ns 1.400ns 4.000ns 3.700ns 6.700ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 52.000 ns - Longest register " "Info: - Longest clock path from clock \"Clock\" to source register is 52.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns Clock 1 CLK PIN_181 33 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_181; Fanout = 33; CLK Node = 'Clock'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { Clock } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 352 -224 -56 368 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 4.200 ns fdiv:inst1\|f1khz 2 REG LC225 42 " "Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 4.200 ns; Loc. = LC225; Fanout = 42; REG Node = 'fdiv:inst1\|f1khz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "1.400 ns" { Clock fdiv:inst1|f1khz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(4.000 ns) 11.500 ns fdiv:inst1\|f100hz 3 REG LC115 34 " "Info: 3: + IC(3.300 ns) + CELL(4.000 ns) = 11.500 ns; Loc. = LC115; Fanout = 34; REG Node = 'fdiv:inst1\|f100hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "7.300 ns" { fdiv:inst1|f1khz fdiv:inst1|f100hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(4.000 ns) 18.700 ns fdiv:inst1\|f10hz 4 REG LC129 34 " "Info: 4: + IC(3.200 ns) + CELL(4.000 ns) = 18.700 ns; Loc. = LC129; Fanout = 34; REG Node = 'fdiv:inst1\|f10hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "7.200 ns" { fdiv:inst1|f100hz fdiv:inst1|f10hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(4.000 ns) 26.000 ns fdiv:inst1\|f1hz 5 REG LC145 1 " "Info: 5: + IC(3.300 ns) + CELL(4.000 ns) = 26.000 ns; Loc. = LC145; Fanout = 1; REG Node = 'fdiv:inst1\|f1hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "7.300 ns" { fdiv:inst1|f10hz fdiv:inst1|f1hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(3.700 ns) 32.700 ns gate_control:inst3\|fref~120 6 COMB LC195 1 " "Info: 6: + IC(3.000 ns) + CELL(3.700 ns) = 32.700 ns; Loc. = LC195; Fanout = 1; COMB Node = 'gate_control:inst3\|fref~120'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { fdiv:inst1|f1hz gate_control:inst3|fref~120 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(3.700 ns) 39.400 ns gate_control:inst3\|fref~114 7 COMB LC203 3 " "Info: 7: + IC(3.000 ns) + CELL(3.700 ns) = 39.400 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3\|fref~114'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~120 gate_control:inst3|fref~114 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 46.100 ns gate_control:inst3\|fref~126 8 COMB LOOP LC205 4 " "Info: 8: + IC(0.000 ns) + CELL(6.700 ns) = 46.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~114 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 52.000 ns gate_control:inst3\|wire_1 9 REG LC193 114 " "Info: 9: + IC(3.000 ns) + CELL(2.900 ns) = 52.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "33.200 ns 63.85 % " "Info: Total cell delay = 33.200 ns ( 63.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "18.800 ns 36.15 % " "Info: Total interconnect delay = 18.800 ns ( 36.15 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "52.000 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "52.000 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 0.000ns 3.300ns 3.200ns 3.300ns 3.000ns 3.000ns 0.000ns 3.000ns } { 0.000ns 2.800ns 1.400ns 4.000ns 4.000ns 4.000ns 3.700ns 3.700ns 6.700ns 2.900ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "31.000 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "31.000 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.300ns 3.200ns 0.000ns 3.000ns } { 0.000ns 2.800ns 1.400ns 4.000ns 3.700ns 6.700ns 2.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "52.000 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "52.000 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 0.000ns 3.300ns 3.200ns 3.300ns 3.000ns 3.000ns 0.000ns 3.000ns } { 0.000ns 2.800ns 1.400ns 4.000ns 4.000ns 4.000ns 3.700ns 3.700ns 6.700ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.100 ns + " "Info: + Micro setup delay of destination is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } { 0.000ns 3.400ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "31.000 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "31.000 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.300ns 3.200ns 0.000ns 3.000ns } { 0.000ns 2.800ns 1.400ns 4.000ns 3.700ns 6.700ns 2.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "52.000 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "52.000 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 0.000ns 3.300ns 3.200ns 3.300ns 3.000ns 3.000ns 0.000ns 3.000ns } { 0.000ns 2.800ns 1.400ns 4.000ns 4.000ns 4.000ns 3.700ns 3.700ns 6.700ns 2.900ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW2 register gate_control:inst3\|wire_1 register gate_control:inst3\|wire_2 33.56 MHz 29.8 ns Internal " "Info: Clock \"SW2\" has Internal fmax of 33.56 MHz between source register \"gate_control:inst3\|wire_1\" and destination register \"gate_control:inst3\|wire_2\" (period= 29.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns gate_control:inst3\|wire_1 1 REG LC193 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.600 ns) 6.000 ns gate_control:inst3\|wire_2 2 REG LC201 24 " "Info: 2: + IC(3.400 ns) + CELL(2.600 ns) = 6.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 43.33 % " "Info: Total cell delay = 2.600 ns ( 43.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.400 ns 56.67 % " "Info: Total interconnect delay = 3.400 ns ( 56.67 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } { 0.000ns 3.400ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.700 ns - Smallest " "Info: - Smallest clock skew is -6.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 destination 13.000 ns + Shortest register " "Info: + Shortest clock path from clock \"SW2\" to destination register is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW2 1 CLK PIN_129 21 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_129; Fanout = 21; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { SW2 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 264 -224 -56 280 "SW2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.800 ns) 7.100 ns gate_control:inst3\|fref~126 2 COMB LOOP LC205 4 " "Info: 2: + IC(0.000 ns) + CELL(6.800 ns) = 7.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.800 ns" { SW2 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 13.000 ns gate_control:inst3\|wire_2 3 REG LC201 24 " "Info: 3: + IC(3.000 ns) + CELL(2.900 ns) = 13.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 76.92 % " "Info: Total cell delay = 10.000 ns ( 76.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 23.08 % " "Info: Total interconnect delay = 3.000 ns ( 23.08 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW2 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW2 SW2~out gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.800ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 source 19.700 ns - Longest register " "Info: - Longest clock path from clock \"SW2\" to source register is 19.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW2 1 CLK PIN_129 21 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_129; Fanout = 21; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { SW2 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 264 -224 -56 280 "SW2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(3.700 ns) 7.100 ns gate_control:inst3\|fref~114 2 COMB LC203 3 " "Info: 2: + IC(3.100 ns) + CELL(3.700 ns) = 7.100 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3\|fref~114'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.800 ns" { SW2 gate_control:inst3|fref~114 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 13.800 ns gate_control:inst3\|fref~126 3 COMB LOOP LC205 4 " "Info: 3: + IC(0.000 ns) + CELL(6.700 ns) = 13.800 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~114 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 19.700 ns gate_control:inst3\|wire_1 4 REG LC193 114 " "Info: 4: + IC(3.000 ns) + CELL(2.900 ns) = 19.700 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.600 ns 69.04 % " "Info: Total cell delay = 13.600 ns ( 69.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.100 ns 30.96 % " "Info: Total interconnect delay = 6.100 ns ( 30.96 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "19.700 ns" { SW2 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "19.700 ns" { SW2 SW2~out gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 3.100ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.700ns 6.700ns 2.900ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW2 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW2 SW2~out gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.800ns 2.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "19.700 ns" { SW2 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "19.700 ns" { SW2 SW2~out gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 3.100ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.700ns 6.700ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.100 ns + " "Info: + Micro setup delay of destination is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } { 0.000ns 3.400ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW2 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW2 SW2~out gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.800ns 2.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "19.700 ns" { SW2 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "19.700 ns" { SW2 SW2~out gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 3.100ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.700ns 6.700ns 2.900ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW1 register gate_control:inst3\|wire_1 register gate_control:inst3\|wire_2 23.15 MHz 43.2 ns Internal " "Info: Clock \"SW1\" has Internal fmax of 23.15 MHz between source register \"gate_control:inst3\|wire_1\" and destination register \"gate_control:inst3\|wire_2\" (period= 43.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns gate_control:inst3\|wire_1 1 REG LC193 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.600 ns) 6.000 ns gate_control:inst3\|wire_2 2 REG LC201 24 " "Info: 2: + IC(3.400 ns) + CELL(2.600 ns) = 6.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 43.33 % " "Info: Total cell delay = 2.600 ns ( 43.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.400 ns 56.67 % " "Info: Total interconnect delay = 3.400 ns ( 56.67 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } { 0.000ns 3.400ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-13.400 ns - Smallest " "Info: - Smallest clock skew is -13.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 13.000 ns + Shortest register " "Info: + Shortest clock path from clock \"SW1\" to destination register is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW1 1 CLK PIN_145 18 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_145; Fanout = 18; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { SW1 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 248 -224 -56 264 "SW1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.800 ns) 7.100 ns gate_control:inst3\|fref~126 2 COMB LOOP LC205 4 " "Info: 2: + IC(0.000 ns) + CELL(6.800 ns) = 7.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.800 ns" { SW1 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 13.000 ns gate_control:inst3\|wire_2 3 REG LC201 24 " "Info: 3: + IC(3.000 ns) + CELL(2.900 ns) = 13.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 76.92 % " "Info: Total cell delay = 10.000 ns ( 76.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 23.08 % " "Info: Total interconnect delay = 3.000 ns ( 23.08 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW1 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW1 SW1~out gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.800ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 source 26.400 ns - Longest register " "Info: - Longest clock path from clock \"SW1\" to source register is 26.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW1 1 CLK PIN_145 18 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_145; Fanout = 18; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { SW1 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 248 -224 -56 264 "SW1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(3.700 ns) 7.100 ns gate_control:inst3\|fref~120 2 COMB LC195 1 " "Info: 2: + IC(3.100 ns) + CELL(3.700 ns) = 7.100 ns; Loc. = LC195; Fanout = 1; COMB Node = 'gate_control:inst3\|fref~120'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.800 ns" { SW1 gate_control:inst3|fref~120 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(3.700 ns) 13.800 ns gate_control:inst3\|fref~114 3 COMB LC203 3 " "Info: 3: + IC(3.000 ns) + CELL(3.700 ns) = 13.800 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3\|fref~114'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~120 gate_control:inst3|fref~114 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 20.500 ns gate_control:inst3\|fref~126 4 COMB LOOP LC205 4 " "Info: 4: + IC(0.000 ns) + CELL(6.700 ns) = 20.500 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~114 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 26.400 ns gate_control:inst3\|wire_1 5 REG LC193 114 " "Info: 5: + IC(3.000 ns) + CELL(2.900 ns) = 26.400 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.300 ns 65.53 % " "Info: Total cell delay = 17.300 ns ( 65.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.100 ns 34.47 % " "Info: Total interconnect delay = 9.100 ns ( 34.47 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "26.400 ns" { SW1 gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "26.400 ns" { SW1 SW1~out gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 3.100ns 3.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.700ns 3.700ns 6.700ns 2.900ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW1 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW1 SW1~out gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.800ns 2.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "26.400 ns" { SW1 gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "26.400 ns" { SW1 SW1~out gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 3.100ns 3.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.700ns 3.700ns 6.700ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.100 ns + " "Info: + Micro setup delay of destination is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } { 0.000ns 3.400ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW1 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW1 SW1~out gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.800ns 2.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "26.400 ns" { SW1 gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "26.400 ns" { SW1 SW1~out gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 3.100ns 3.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.700ns 3.700ns 6.700ns 2.900ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW0 register gate_control:inst3\|wire_1 register gate_control:inst3\|wire_2 41.32 MHz 24.2 ns Internal " "Info: Clock \"SW0\" has Internal fmax of 41.32 MHz between source register \"gate_control:inst3\|wire_1\" and destination register \"gate_control:inst3\|wire_2\" (period= 24.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns gate_control:inst3\|wire_1 1 REG LC193 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.600 ns) 6.000 ns gate_control:inst3\|wire_2 2 REG LC201 24 " "Info: 2: + IC(3.400 ns) + CELL(2.600 ns) = 6.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 43.33 % " "Info: Total cell delay = 2.600 ns ( 43.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.400 ns 56.67 % " "Info: Total interconnect delay = 3.400 ns ( 56.67 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } { 0.000ns 3.400ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.900 ns - Smallest " "Info: - Smallest clock skew is -3.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW0 destination 13.000 ns + Shortest register " "Info: + Shortest clock path from clock \"SW0\" to destination register is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW0 1 CLK PIN_135 12 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_135; Fanout = 12; CLK Node = 'SW0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { SW0 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 232 -224 -56 248 "SW0" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.800 ns) 7.100 ns gate_control:inst3\|fref~126 2 COMB LOOP LC205 4 " "Info: 2: + IC(0.000 ns) + CELL(6.800 ns) = 7.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.800 ns" { SW0 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 13.000 ns gate_control:inst3\|wire_2 3 REG LC201 24 " "Info: 3: + IC(3.000 ns) + CELL(2.900 ns) = 13.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 76.92 % " "Info: Total cell delay = 10.000 ns ( 76.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 23.08 % " "Info: Total interconnect delay = 3.000 ns ( 23.08 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW0 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW0 SW0~out gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.800ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW0 source 16.900 ns - Longest register " "Info: - Longest clock path from clock \"SW0\" to source register is 16.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW0 1 CLK PIN_135 12 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_135; Fanout = 12; CLK Node = 'SW0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { SW0 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 232 -224 -56 248 "SW0" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(3.900 ns) 7.300 ns gate_control:inst3\|always0~44 2 COMB SEXP193 2 " "Info: 2: + IC(3.100 ns) + CELL(3.900 ns) = 7.300 ns; Loc. = SEXP193; Fanout = 2; COMB Node = 'gate_control:inst3\|always0~44'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "7.000 ns" { SW0 gate_control:inst3|always0~44 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.700 ns) 11.000 ns gate_control:inst3\|fref~126 3 COMB LOOP LC205 4 " "Info: 3: + IC(0.000 ns) + CELL(3.700 ns) = 11.000 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "3.700 ns" { gate_control:inst3|always0~44 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 16.900 ns gate_control:inst3\|wire_1 4 REG LC193 114 " "Info: 4: + IC(3.000 ns) + CELL(2.900 ns) = 16.900 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.800 ns 63.91 % " "Info: Total cell delay = 10.800 ns ( 63.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.100 ns 36.09 % " "Info: Total interconnect delay = 6.100 ns ( 36.09 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "16.900 ns" { SW0 gate_control:inst3|always0~44 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "16.900 ns" { SW0 SW0~out gate_control:inst3|always0~44 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 3.100ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.900ns 3.700ns 2.900ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW0 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW0 SW0~out gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.800ns 2.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "16.900 ns" { SW0 gate_control:inst3|always0~44 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "16.900 ns" { SW0 SW0~out gate_control:inst3|always0~44 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 3.100ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.900ns 3.700ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.100 ns + " "Info: + Micro setup delay of destination is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } { 0.000ns 3.400ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW0 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW0 SW0~out gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.800ns 2.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "16.900 ns" { SW0 gate_control:inst3|always0~44 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "16.900 ns" { SW0 SW0~out gate_control:inst3|always0~44 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 3.100ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.900ns 3.700ns 2.900ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "F_in register counter:inst\|lpm_counter:Q0_rtl_1\|dffs\[0\] register counter:inst\|F_OUT 53.48 MHz 18.7 ns Internal " "Info: Clock \"F_in\" has Internal fmax of 53.48 MHz between source register \"counter:inst\|lpm_counter:Q0_rtl_1\|dffs\[0\]\" and destination register \"counter:inst\|F_OUT\" (period= 18.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.500 ns + Longest register register " "Info: + Longest register to register delay is 16.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst\|lpm_counter:Q0_rtl_1\|dffs\[0\] 1 REG LC211 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC211; Fanout = 16; REG Node = 'counter:inst\|lpm_counter:Q0_rtl_1\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { counter:inst|lpm_counter:Q0_rtl_1|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(3.700 ns) 6.900 ns counter:inst\|F_OUT~201 2 COMB LC103 19 " "Info: 2: + IC(3.200 ns) + CELL(3.700 ns) = 6.900 ns; Loc. = LC103; Fanout = 19; COMB Node = 'counter:inst\|F_OUT~201'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.900 ns" { counter:inst|lpm_counter:Q0_rtl_1|dffs[0] counter:inst|F_OUT~201 } "NODE_NAME" } "" } } { "counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(3.900 ns) 13.900 ns counter:inst\|F_OUT~204 3 COMB SEXP95 1 " "Info: 3: + IC(3.100 ns) + CELL(3.900 ns) = 13.900 ns; Loc. = SEXP95; Fanout = 1; COMB Node = 'counter:inst\|F_OUT~204'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "7.000 ns" { counter:inst|F_OUT~201 counter:inst|F_OUT~204 } "NODE_NAME" } "" } } { "counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.600 ns) 16.500 ns counter:inst\|F_OUT 4 REG LC81 5 " "Info: 4: + IC(0.000 ns) + CELL(2.600 ns) = 16.500 ns; Loc. = LC81; Fanout = 5; REG Node = 'counter:inst\|F_OUT'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "2.600 ns" { counter:inst|F_OUT~204 counter:inst|F_OUT } "NODE_NAME" } "" } } { "counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.200 ns 61.82 % " "Info: Total cell delay = 10.200 ns ( 61.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.300 ns 38.18 % " "Info: Total interconnect delay = 6.300 ns ( 38.18 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "16.500 ns" { counter:inst|lpm_counter:Q0_rtl_1|dffs[0] counter:inst|F_OUT~201 counter:inst|F_OUT~204 counter:inst|F_OUT } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "16.500 ns" { counter:inst|lpm_counter:Q0_rtl_1|dffs[0] counter:inst|F_OUT~201 counter:inst|F_OUT~204 counter:inst|F_OUT } { 0.000ns 3.200ns 3.100ns 0.000ns } { 0.000ns 3.700ns 3.900ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F_in destination 3.100 ns + Shortest register " "Info: + Shortest clock path from clock \"F_in\" to destination register is 3.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns F_in 1 CLK PIN_184 25 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_184; Fanout = 25; CLK Node = 'F_in'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { F_in } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 56 -224 -56 72 "F_in" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 3.100 ns counter:inst\|F_OUT 2 REG LC81 5 " "Info: 2: + IC(0.000 ns) + CELL(0.300 ns) = 3.100 ns; Loc. = LC81; Fanout = 5; REG Node = 'counter:inst\|F_OUT'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "0.300 ns" { F_in counter:inst|F_OUT } "NODE_NAME" } "" } } { "counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/counter.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns 100.00 % " "Info: Total cell delay = 3.100 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "3.100 ns" { F_in counter:inst|F_OUT } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.100 ns" { F_in F_in~out counter:inst|F_OUT } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.800ns 0.300ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F_in source 3.100 ns - Longest register " "Info: - Longest clock path from clock \"F_in\" to source register is 3.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns F_in 1 CLK PIN_184 25 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_184; Fanout = 25; CLK Node = 'F_in'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { F_in } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 56 -224 -56 72 "F_in" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 3.100 ns counter:inst\|lpm_counter:Q0_rtl_1\|dffs\[0\] 2 REG LC211 16 " "Info: 2: + IC(0.000 ns) + CELL(0.300 ns) = 3.100 ns; Loc. = LC211; Fanout = 16; REG Node = 'counter:inst\|lpm_counter:Q0_rtl_1\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "0.300 ns" { F_in counter:inst|lpm_counter:Q0_rtl_1|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns 100.00 % " "Info: Total cell delay = 3.100 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "3.100 ns" { F_in counter:inst|lpm_counter:Q0_rtl_1|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.100 ns" { F_in F_in~out counter:inst|lpm_counter:Q0_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.800ns 0.300ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "3.100 ns" { F_in counter:inst|F_OUT } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.100 ns" { F_in F_in~out counter:inst|F_OUT } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.800ns 0.300ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "3.100 ns" { F_in counter:inst|lpm_counter:Q0_rtl_1|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.100 ns" { F_in F_in~out counter:inst|lpm_counter:Q0_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.800ns 0.300ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.100 ns + " "Info: + Micro setup delay of destination is 1.100 ns" {  } { { "counter.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/counter.v" 4 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "16.500 ns" { counter:inst|lpm_counter:Q0_rtl_1|dffs[0] counter:inst|F_OUT~201 counter:inst|F_OUT~204 counter:inst|F_OUT } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "16.500 ns" { counter:inst|lpm_counter:Q0_rtl_1|dffs[0] counter:inst|F_OUT~201 counter:inst|F_OUT~204 counter:inst|F_OUT } { 0.000ns 3.200ns 3.100ns 0.000ns } { 0.000ns 3.700ns 3.900ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "3.100 ns" { F_in counter:inst|F_OUT } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.100 ns" { F_in F_in~out counter:inst|F_OUT } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.800ns 0.300ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "3.100 ns" { F_in counter:inst|lpm_counter:Q0_rtl_1|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.100 ns" { F_in F_in~out counter:inst|lpm_counter:Q0_rtl_1|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.800ns 0.300ns } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "Clock 2 " "Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock \"Clock\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "gate_control:inst3\|wire_1 gate_control:inst3\|wire_1 Clock 15.9 ns " "Info: Found hold time violation between source  pin or register \"gate_control:inst3\|wire_1\" and destination pin or register \"gate_control:inst3\|wire_1\" for clock \"Clock\" (Hold time is 15.9 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "21.000 ns + Largest " "Info: + Largest clock skew is 21.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 52.000 ns + Longest register " "Info: + Longest clock path from clock \"Clock\" to destination register is 52.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns Clock 1 CLK PIN_181 33 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_181; Fanout = 33; CLK Node = 'Clock'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { Clock } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 352 -224 -56 368 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 4.200 ns fdiv:inst1\|f1khz 2 REG LC225 42 " "Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 4.200 ns; Loc. = LC225; Fanout = 42; REG Node = 'fdiv:inst1\|f1khz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "1.400 ns" { Clock fdiv:inst1|f1khz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(4.000 ns) 11.500 ns fdiv:inst1\|f100hz 3 REG LC115 34 " "Info: 3: + IC(3.300 ns) + CELL(4.000 ns) = 11.500 ns; Loc. = LC115; Fanout = 34; REG Node = 'fdiv:inst1\|f100hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "7.300 ns" { fdiv:inst1|f1khz fdiv:inst1|f100hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(4.000 ns) 18.700 ns fdiv:inst1\|f10hz 4 REG LC129 34 " "Info: 4: + IC(3.200 ns) + CELL(4.000 ns) = 18.700 ns; Loc. = LC129; Fanout = 34; REG Node = 'fdiv:inst1\|f10hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "7.200 ns" { fdiv:inst1|f100hz fdiv:inst1|f10hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(4.000 ns) 26.000 ns fdiv:inst1\|f1hz 5 REG LC145 1 " "Info: 5: + IC(3.300 ns) + CELL(4.000 ns) = 26.000 ns; Loc. = LC145; Fanout = 1; REG Node = 'fdiv:inst1\|f1hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "7.300 ns" { fdiv:inst1|f10hz fdiv:inst1|f1hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(3.700 ns) 32.700 ns gate_control:inst3\|fref~120 6 COMB LC195 1 " "Info: 6: + IC(3.000 ns) + CELL(3.700 ns) = 32.700 ns; Loc. = LC195; Fanout = 1; COMB Node = 'gate_control:inst3\|fref~120'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { fdiv:inst1|f1hz gate_control:inst3|fref~120 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(3.700 ns) 39.400 ns gate_control:inst3\|fref~114 7 COMB LC203 3 " "Info: 7: + IC(3.000 ns) + CELL(3.700 ns) = 39.400 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3\|fref~114'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~120 gate_control:inst3|fref~114 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 46.100 ns gate_control:inst3\|fref~126 8 COMB LOOP LC205 4 " "Info: 8: + IC(0.000 ns) + CELL(6.700 ns) = 46.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~114 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 52.000 ns gate_control:inst3\|wire_1 9 REG LC193 114 " "Info: 9: + IC(3.000 ns) + CELL(2.900 ns) = 52.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "33.200 ns 63.85 % " "Info: Total cell delay = 33.200 ns ( 63.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "18.800 ns 36.15 % " "Info: Total interconnect delay = 18.800 ns ( 36.15 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "52.000 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "52.000 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.0ns 0.0ns 0.0ns 3.3ns 3.2ns 3.3ns 3.0ns 3.0ns 0.0ns 3.0ns } { 0.0ns 2.8ns 1.4ns 4.0ns 4.0ns 4.0ns 3.7ns 3.7ns 6.7ns 2.9ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 31.000 ns - Shortest register " "Info: - Shortest clock path from clock \"Clock\" to source register is 31.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns Clock 1 CLK PIN_181 33 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_181; Fanout = 33; CLK Node = 'Clock'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { Clock } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 352 -224 -56 368 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 4.200 ns fdiv:inst1\|f1khz 2 REG LC225 42 " "Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 4.200 ns; Loc. = LC225; Fanout = 42; REG Node = 'fdiv:inst1\|f1khz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "1.400 ns" { Clock fdiv:inst1|f1khz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(4.000 ns) 11.500 ns fdiv:inst1\|f100hz 3 REG LC115 34 " "Info: 3: + IC(3.300 ns) + CELL(4.000 ns) = 11.500 ns; Loc. = LC115; Fanout = 34; REG Node = 'fdiv:inst1\|f100hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "7.300 ns" { fdiv:inst1|f1khz fdiv:inst1|f100hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(3.700 ns) 18.400 ns gate_control:inst3\|fref~114 4 COMB LC203 3 " "Info: 4: + IC(3.200 ns) + CELL(3.700 ns) = 18.400 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3\|fref~114'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.900 ns" { fdiv:inst1|f100hz gate_control:inst3|fref~114 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 25.100 ns gate_control:inst3\|fref~126 5 COMB LOOP LC205 4 " "Info: 5: + IC(0.000 ns) + CELL(6.700 ns) = 25.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~114 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 31.000 ns gate_control:inst3\|wire_1 6 REG LC193 114 " "Info: 6: + IC(3.000 ns) + CELL(2.900 ns) = 31.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.500 ns 69.35 % " "Info: Total cell delay = 21.500 ns ( 69.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.500 ns 30.65 % " "Info: Total interconnect delay = 9.500 ns ( 30.65 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "31.000 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "31.000 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.0ns 0.0ns 0.0ns 3.3ns 3.2ns 0.0ns 3.0ns } { 0.0ns 2.8ns 1.4ns 4.0ns 3.7ns 6.7ns 2.9ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "52.000 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "52.000 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.0ns 0.0ns 0.0ns 3.3ns 3.2ns 3.3ns 3.0ns 3.0ns 0.0ns 3.0ns } { 0.0ns 2.8ns 1.4ns 4.0ns 4.0ns 4.0ns 3.7ns 3.7ns 6.7ns 2.9ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "31.000 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "31.000 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.0ns 0.0ns 0.0ns 3.3ns 3.2ns 0.0ns 3.0ns } { 0.0ns 2.8ns 1.4ns 4.0ns 3.7ns 6.7ns 2.9ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.600 ns - Shortest register register " "Info: - Shortest register to register delay is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns gate_control:inst3\|wire_1 1 REG LC193 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.600 ns) 5.600 ns gate_control:inst3\|wire_1 2 REG LC193 114 " "Info: 2: + IC(0.000 ns) + CELL(5.600 ns) = 5.600 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.600 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.600 ns 100.00 % " "Info: Total cell delay = 5.600 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.600 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_1 } { 0.0ns 0.0ns } { 0.0ns 5.6ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "52.000 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "52.000 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.0ns 0.0ns 0.0ns 3.3ns 3.2ns 3.3ns 3.0ns 3.0ns 0.0ns 3.0ns } { 0.0ns 2.8ns 1.4ns 4.0ns 4.0ns 4.0ns 3.7ns 3.7ns 6.7ns 2.9ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "31.000 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "31.000 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.0ns 0.0ns 0.0ns 3.3ns 3.2ns 0.0ns 3.0ns } { 0.0ns 2.8ns 1.4ns 4.0ns 3.7ns 6.7ns 2.9ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.600 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_1 } { 0.0ns 0.0ns } { 0.0ns 5.6ns } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "SW2 2 " "Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock \"SW2\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "gate_control:inst3\|wire_1 gate_control:inst3\|wire_1 SW2 1.6 ns " "Info: Found hold time violation between source  pin or register \"gate_control:inst3\|wire_1\" and destination pin or register \"gate_control:inst3\|wire_1\" for clock \"SW2\" (Hold time is 1.6 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.700 ns + Largest " "Info: + Largest clock skew is 6.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 destination 19.700 ns + Longest register " "Info: + Longest clock path from clock \"SW2\" to destination register is 19.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW2 1 CLK PIN_129 21 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_129; Fanout = 21; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { SW2 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 264 -224 -56 280 "SW2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(3.700 ns) 7.100 ns gate_control:inst3\|fref~114 2 COMB LC203 3 " "Info: 2: + IC(3.100 ns) + CELL(3.700 ns) = 7.100 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3\|fref~114'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.800 ns" { SW2 gate_control:inst3|fref~114 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 13.800 ns gate_control:inst3\|fref~126 3 COMB LOOP LC205 4 " "Info: 3: + IC(0.000 ns) + CELL(6.700 ns) = 13.800 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~114 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 19.700 ns gate_control:inst3\|wire_1 4 REG LC193 114 " "Info: 4: + IC(3.000 ns) + CELL(2.900 ns) = 19.700 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.600 ns 69.04 % " "Info: Total cell delay = 13.600 ns ( 69.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.100 ns 30.96 % " "Info: Total interconnect delay = 6.100 ns ( 30.96 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "19.700 ns" { SW2 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "19.700 ns" { SW2 SW2~out gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.0ns 0.0ns 3.1ns 0.0ns 3.0ns } { 0.0ns 0.3ns 3.7ns 6.7ns 2.9ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 source 13.000 ns - Shortest register " "Info: - Shortest clock path from clock \"SW2\" to source register is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW2 1 CLK PIN_129 21 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_129; Fanout = 21; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { SW2 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 264 -224 -56 280 "SW2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.800 ns) 7.100 ns gate_control:inst3\|fref~126 2 COMB LOOP LC205 4 " "Info: 2: + IC(0.000 ns) + CELL(6.800 ns) = 7.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.800 ns" { SW2 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 13.000 ns gate_control:inst3\|wire_1 3 REG LC193 114 " "Info: 3: + IC(3.000 ns) + CELL(2.900 ns) = 13.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 76.92 % " "Info: Total cell delay = 10.000 ns ( 76.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 23.08 % " "Info: Total interconnect delay = 3.000 ns ( 23.08 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW2 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW2 SW2~out gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.0ns 0.0ns 0.0ns 3.0ns } { 0.0ns 0.3ns 6.8ns 2.9ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "19.700 ns" { SW2 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "19.700 ns" { SW2 SW2~out gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.0ns 0.0ns 3.1ns 0.0ns 3.0ns } { 0.0ns 0.3ns 3.7ns 6.7ns 2.9ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW2 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW2 SW2~out gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.0ns 0.0ns 0.0ns 3.0ns } { 0.0ns 0.3ns 6.8ns 2.9ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.600 ns - Shortest register register " "Info: - Shortest register to register delay is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns gate_control:inst3\|wire_1 1 REG LC193 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.600 ns) 5.600 ns gate_control:inst3\|wire_1 2 REG LC193 114 " "Info: 2: + IC(0.000 ns) + CELL(5.600 ns) = 5.600 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.600 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.600 ns 100.00 % " "Info: Total cell delay = 5.600 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.600 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_1 } { 0.0ns 0.0ns } { 0.0ns 5.6ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "19.700 ns" { SW2 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "19.700 ns" { SW2 SW2~out gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.0ns 0.0ns 3.1ns 0.0ns 3.0ns } { 0.0ns 0.3ns 3.7ns 6.7ns 2.9ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW2 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW2 SW2~out gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.0ns 0.0ns 0.0ns 3.0ns } { 0.0ns 0.3ns 6.8ns 2.9ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.600 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_1 } { 0.0ns 0.0ns } { 0.0ns 5.6ns } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "SW1 2 " "Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock \"SW1\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "gate_control:inst3\|wire_1 gate_control:inst3\|wire_1 SW1 8.3 ns " "Info: Found hold time violation between source  pin or register \"gate_control:inst3\|wire_1\" and destination pin or register \"gate_control:inst3\|wire_1\" for clock \"SW1\" (Hold time is 8.3 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "13.400 ns + Largest " "Info: + Largest clock skew is 13.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 26.400 ns + Longest register " "Info: + Longest clock path from clock \"SW1\" to destination register is 26.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW1 1 CLK PIN_145 18 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_145; Fanout = 18; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { SW1 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 248 -224 -56 264 "SW1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(3.700 ns) 7.100 ns gate_control:inst3\|fref~120 2 COMB LC195 1 " "Info: 2: + IC(3.100 ns) + CELL(3.700 ns) = 7.100 ns; Loc. = LC195; Fanout = 1; COMB Node = 'gate_control:inst3\|fref~120'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.800 ns" { SW1 gate_control:inst3|fref~120 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(3.700 ns) 13.800 ns gate_control:inst3\|fref~114 3 COMB LC203 3 " "Info: 3: + IC(3.000 ns) + CELL(3.700 ns) = 13.800 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3\|fref~114'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~120 gate_control:inst3|fref~114 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 20.500 ns gate_control:inst3\|fref~126 4 COMB LOOP LC205 4 " "Info: 4: + IC(0.000 ns) + CELL(6.700 ns) = 20.500 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~114 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 26.400 ns gate_control:inst3\|wire_1 5 REG LC193 114 " "Info: 5: + IC(3.000 ns) + CELL(2.900 ns) = 26.400 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.300 ns 65.53 % " "Info: Total cell delay = 17.300 ns ( 65.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.100 ns 34.47 % " "Info: Total interconnect delay = 9.100 ns ( 34.47 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "26.400 ns" { SW1 gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "26.400 ns" { SW1 SW1~out gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.0ns 0.0ns 3.1ns 3.0ns 0.0ns 3.0ns } { 0.0ns 0.3ns 3.7ns 3.7ns 6.7ns 2.9ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 source 13.000 ns - Shortest register " "Info: - Shortest clock path from clock \"SW1\" to source register is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW1 1 CLK PIN_145 18 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_145; Fanout = 18; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { SW1 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 248 -224 -56 264 "SW1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.800 ns) 7.100 ns gate_control:inst3\|fref~126 2 COMB LOOP LC205 4 " "Info: 2: + IC(0.000 ns) + CELL(6.800 ns) = 7.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.800 ns" { SW1 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 13.000 ns gate_control:inst3\|wire_1 3 REG LC193 114 " "Info: 3: + IC(3.000 ns) + CELL(2.900 ns) = 13.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 76.92 % " "Info: Total cell delay = 10.000 ns ( 76.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 23.08 % " "Info: Total interconnect delay = 3.000 ns ( 23.08 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW1 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW1 SW1~out gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.0ns 0.0ns 0.0ns 3.0ns } { 0.0ns 0.3ns 6.8ns 2.9ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "26.400 ns" { SW1 gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "26.400 ns" { SW1 SW1~out gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.0ns 0.0ns 3.1ns 3.0ns 0.0ns 3.0ns } { 0.0ns 0.3ns 3.7ns 3.7ns 6.7ns 2.9ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW1 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW1 SW1~out gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.0ns 0.0ns 0.0ns 3.0ns } { 0.0ns 0.3ns 6.8ns 2.9ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.600 ns - Shortest register register " "Info: - Shortest register to register delay is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns gate_control:inst3\|wire_1 1 REG LC193 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.600 ns) 5.600 ns gate_control:inst3\|wire_1 2 REG LC193 114 " "Info: 2: + IC(0.000 ns) + CELL(5.600 ns) = 5.600 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.600 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.600 ns 100.00 % " "Info: Total cell delay = 5.600 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.600 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_1 } { 0.0ns 0.0ns } { 0.0ns 5.6ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "26.400 ns" { SW1 gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "26.400 ns" { SW1 SW1~out gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.0ns 0.0ns 3.1ns 3.0ns 0.0ns 3.0ns } { 0.0ns 0.3ns 3.7ns 3.7ns 6.7ns 2.9ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW1 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW1 SW1~out gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.0ns 0.0ns 0.0ns 3.0ns } { 0.0ns 0.3ns 6.8ns 2.9ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.600 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_1 } { 0.0ns 0.0ns } { 0.0ns 5.6ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clock disp_data\[2\] flip_latch:inst2\|Q1\[2\] 82.300 ns register " "Info: tco from clock \"Clock\" to destination pin \"disp_data\[2\]\" through register \"flip_latch:inst2\|Q1\[2\]\" is 82.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 59.400 ns + Longest register " "Info: + Longest clock path from clock \"Clock\" to source register is 59.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns Clock 1 CLK PIN_181 33 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_181; Fanout = 33; CLK Node = 'Clock'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { Clock } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 352 -224 -56 368 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 4.200 ns fdiv:inst1\|f1khz 2 REG LC225 42 " "Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 4.200 ns; Loc. = LC225; Fanout = 42; REG Node = 'fdiv:inst1\|f1khz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "1.400 ns" { Clock fdiv:inst1|f1khz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(4.000 ns) 11.500 ns fdiv:inst1\|f100hz 3 REG LC115 34 " "Info: 3: + IC(3.300 ns) + CELL(4.000 ns) = 11.500 ns; Loc. = LC115; Fanout = 34; REG Node = 'fdiv:inst1\|f100hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "7.300 ns" { fdiv:inst1|f1khz fdiv:inst1|f100hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(4.000 ns) 18.700 ns fdiv:inst1\|f10hz 4 REG LC129 34 " "Info: 4: + IC(3.200 ns) + CELL(4.000 ns) = 18.700 ns; Loc. = LC129; Fanout = 34; REG Node = 'fdiv:inst1\|f10hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "7.200 ns" { fdiv:inst1|f100hz fdiv:inst1|f10hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(4.000 ns) 26.000 ns fdiv:inst1\|f1hz 5 REG LC145 1 " "Info: 5: + IC(3.300 ns) + CELL(4.000 ns) = 26.000 ns; Loc. = LC145; Fanout = 1; REG Node = 'fdiv:inst1\|f1hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "7.300 ns" { fdiv:inst1|f10hz fdiv:inst1|f1hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(3.700 ns) 32.700 ns gate_control:inst3\|fref~120 6 COMB LC195 1 " "Info: 6: + IC(3.000 ns) + CELL(3.700 ns) = 32.700 ns; Loc. = LC195; Fanout = 1; COMB Node = 'gate_control:inst3\|fref~120'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { fdiv:inst1|f1hz gate_control:inst3|fref~120 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(3.700 ns) 39.400 ns gate_control:inst3\|fref~114 7 COMB LC203 3 " "Info: 7: + IC(3.000 ns) + CELL(3.700 ns) = 39.400 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3\|fref~114'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~120 gate_control:inst3|fref~114 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 46.100 ns gate_control:inst3\|fref~126 8 COMB LOOP LC205 4 " "Info: 8: + IC(0.000 ns) + CELL(6.700 ns) = 46.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~114 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(4.000 ns) 53.100 ns gate_control:inst3\|wire_1 9 REG LC193 114 " "Info: 9: + IC(3.000 ns) + CELL(4.000 ns) = 53.100 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "7.000 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.900 ns) 59.400 ns flip_latch:inst2\|Q1\[2\] 10 REG LC227 6 " "Info: 10: + IC(3.400 ns) + CELL(2.900 ns) = 59.400 ns; Loc. = LC227; Fanout = 6; REG Node = 'flip_latch:inst2\|Q1\[2\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.300 ns" { gate_control:inst3|wire_1 flip_latch:inst2|Q1[2] } "NODE_NAME" } "" } } { "flip_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/flip_latch.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "37.200 ns 62.63 % " "Info: Total cell delay = 37.200 ns ( 62.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "22.200 ns 37.37 % " "Info: Total interconnect delay = 22.200 ns ( 37.37 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "59.400 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 flip_latch:inst2|Q1[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "59.400 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 flip_latch:inst2|Q1[2] } { 0.000ns 0.000ns 0.000ns 3.300ns 3.200ns 3.300ns 3.000ns 3.000ns 0.000ns 3.000ns 3.400ns } { 0.000ns 2.800ns 1.400ns 4.000ns 4.000ns 4.000ns 3.700ns 3.700ns 6.700ns 4.000ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "flip_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/flip_latch.v" 3 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "21.800 ns + Longest register pin " "Info: + Longest register to pin delay is 21.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns flip_latch:inst2\|Q1\[2\] 1 REG LC227 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC227; Fanout = 6; REG Node = 'flip_latch:inst2\|Q1\[2\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { flip_latch:inst2|Q1[2] } "NODE_NAME" } "" } } { "flip_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/flip_latch.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(2.600 ns) 5.700 ns dispdecoder:inst5\|reduce_or~1916 2 COMB LC79 1 " "Info: 2: + IC(3.100 ns) + CELL(2.600 ns) = 5.700 ns; Loc. = LC79; Fanout = 1; COMB Node = 'dispdecoder:inst5\|reduce_or~1916'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.700 ns" { flip_latch:inst2|Q1[2] dispdecoder:inst5|reduce_or~1916 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 7.900 ns dispdecoder:inst5\|reduce_or~1859 3 COMB LC80 6 " "Info: 3: + IC(0.000 ns) + CELL(2.200 ns) = 7.900 ns; Loc. = LC80; Fanout = 6; COMB Node = 'dispdecoder:inst5\|reduce_or~1859'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "2.200 ns" { dispdecoder:inst5|reduce_or~1916 dispdecoder:inst5|reduce_or~1859 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(3.700 ns) 14.600 ns dispdecoder:inst5\|reduce_or~1835 4 COMB LC250 9 " "Info: 4: + IC(3.000 ns) + CELL(3.700 ns) = 14.600 ns; Loc. = LC250; Fanout = 9; COMB Node = 'dispdecoder:inst5\|reduce_or~1835'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { dispdecoder:inst5|reduce_or~1859 dispdecoder:inst5|reduce_or~1835 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 21.300 ns dispdecoder:inst5\|data_out\[2\]~166 5 COMB LOOP LC246 3 " "Info: 5: + IC(0.000 ns) + CELL(6.700 ns) = 21.300 ns; Loc. = LC246; Fanout = 3; COMB LOOP Node = 'dispdecoder:inst5\|data_out\[2\]~166'" { { "Info" "ITDB_PART_OF_SCC" "dispdecoder:inst5\|data_out\[2\]~166 LC246 " "Info: Loc. = LC246; Node \"dispdecoder:inst5\|data_out\[2\]~166\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { dispdecoder:inst5|data_out[2]~166 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { dispdecoder:inst5|data_out[2]~166 } "NODE_NAME" } "" } } { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { dispdecoder:inst5|reduce_or~1835 dispdecoder:inst5|data_out[2]~166 } "NODE_NAME" } "" } } { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 21.800 ns disp_data\[2\] 6 PIN PIN_61 0 " "Info: 6: + IC(0.000 ns) + CELL(0.500 ns) = 21.800 ns; Loc. = PIN_61; Fanout = 0; PIN Node = 'disp_data\[2\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "0.500 ns" { dispdecoder:inst5|data_out[2]~166 disp_data[2] } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 248 720 896 264 "disp_data\[6..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "15.700 ns 72.02 % " "Info: Total cell delay = 15.700 ns ( 72.02 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.100 ns 27.98 % " "Info: Total interconnect delay = 6.100 ns ( 27.98 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "21.800 ns" { flip_latch:inst2|Q1[2] dispdecoder:inst5|reduce_or~1916 dispdecoder:inst5|reduce_or~1859 dispdecoder:inst5|reduce_or~1835 dispdecoder:inst5|data_out[2]~166 disp_data[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "21.800 ns" { flip_latch:inst2|Q1[2] dispdecoder:inst5|reduce_or~1916 dispdecoder:inst5|reduce_or~1859 dispdecoder:inst5|reduce_or~1835 dispdecoder:inst5|data_out[2]~166 disp_data[2] } { 0.000ns 3.100ns 0.000ns 3.000ns 0.000ns 0.000ns } { 0.000ns 2.600ns 2.200ns 3.700ns 6.700ns 0.500ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "59.400 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 flip_latch:inst2|Q1[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "59.400 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 flip_latch:inst2|Q1[2] } { 0.000ns 0.000ns 0.000ns 3.300ns 3.200ns 3.300ns 3.000ns 3.000ns 0.000ns 3.000ns 3.400ns } { 0.000ns 2.800ns 1.400ns 4.000ns 4.000ns 4.000ns 3.700ns 3.700ns 6.700ns 4.000ns 2.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "21.800 ns" { flip_latch:inst2|Q1[2] dispdecoder:inst5|reduce_or~1916 dispdecoder:inst5|reduce_or~1859 dispdecoder:inst5|reduce_or~1835 dispdecoder:inst5|data_out[2]~166 disp_data[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "21.800 ns" { flip_latch:inst2|Q1[2] dispdecoder:inst5|reduce_or~1916 dispdecoder:inst5|reduce_or~1859 dispdecoder:inst5|reduce_or~1835 dispdecoder:inst5|data_out[2]~166 disp_data[2] } { 0.000ns 3.100ns 0.000ns 3.000ns 0.000ns 0.000ns } { 0.000ns 2.600ns 2.200ns 3.700ns 6.700ns 0.500ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SW2 disp_data\[2\] 21.000 ns Longest " "Info: Longest tpd from source pin \"SW2\" to destination pin \"disp_data\[2\]\" is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW2 1 CLK PIN_129 21 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_129; Fanout = 21; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { SW2 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 264 -224 -56 280 "SW2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.800 ns) 7.100 ns gate_control:inst3\|dp_s100hz~25 2 COMB LOOP LC92 6 " "Info: 2: + IC(0.000 ns) + CELL(6.800 ns) = 7.100 ns; Loc. = LC92; Fanout = 6; COMB LOOP Node = 'gate_control:inst3\|dp_s100hz~25'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|dp_s100hz~25 LC92 " "Info: Loc. = LC92; Node \"gate_control:inst3\|dp_s100hz~25\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|dp_s100hz~25 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|dp_s100hz~25 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 12 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.800 ns" { SW2 gate_control:inst3|dp_s100hz~25 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(3.700 ns) 13.800 ns dispdecoder:inst5\|hide~386 3 COMB LC85 21 " "Info: 3: + IC(3.000 ns) + CELL(3.700 ns) = 13.800 ns; Loc. = LC85; Fanout = 21; COMB Node = 'dispdecoder:inst5\|hide~386'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|dp_s100hz~25 dispdecoder:inst5|hide~386 } "NODE_NAME" } "" } } { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 20.500 ns dispdecoder:inst5\|data_out\[2\]~166 4 COMB LOOP LC246 3 " "Info: 4: + IC(0.000 ns) + CELL(6.700 ns) = 20.500 ns; Loc. = LC246; Fanout = 3; COMB LOOP Node = 'dispdecoder:inst5\|data_out\[2\]~166'" { { "Info" "ITDB_PART_OF_SCC" "dispdecoder:inst5\|data_out\[2\]~166 LC246 " "Info: Loc. = LC246; Node \"dispdecoder:inst5\|data_out\[2\]~166\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { dispdecoder:inst5|data_out[2]~166 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { dispdecoder:inst5|data_out[2]~166 } "NODE_NAME" } "" } } { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { dispdecoder:inst5|hide~386 dispdecoder:inst5|data_out[2]~166 } "NODE_NAME" } "" } } { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 21.000 ns disp_data\[2\] 5 PIN PIN_61 0 " "Info: 5: + IC(0.000 ns) + CELL(0.500 ns) = 21.000 ns; Loc. = PIN_61; Fanout = 0; PIN Node = 'disp_data\[2\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "0.500 ns" { dispdecoder:inst5|data_out[2]~166 disp_data[2] } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 248 720 896 264 "disp_data\[6..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "18.000 ns 85.71 % " "Info: Total cell delay = 18.000 ns ( 85.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 14.29 % " "Info: Total interconnect delay = 3.000 ns ( 14.29 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "21.000 ns" { SW2 gate_control:inst3|dp_s100hz~25 dispdecoder:inst5|hide~386 dispdecoder:inst5|data_out[2]~166 disp_data[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "21.000 ns" { SW2 SW2~out gate_control:inst3|dp_s100hz~25 dispdecoder:inst5|hide~386 dispdecoder:inst5|data_out[2]~166 disp_data[2] } { 0.000ns 0.000ns 0.000ns 3.000ns 0.000ns 0.000ns } { 0.000ns 0.300ns 6.800ns 3.700ns 6.700ns 0.500ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 17 23:30:19 2006 " "Info: Processing ended: Mon Jul 17 23:30:19 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}
