|fdiv
Reset => CNT~23.OUTPUTSELECT
Reset => CNT~24.OUTPUTSELECT
Reset => CNT~25.OUTPUTSELECT
Reset => CNT~26.OUTPUTSELECT
Reset => CNT~27.OUTPUTSELECT
Reset => CNT~28.OUTPUTSELECT
Reset => CNT~29.OUTPUTSELECT
Reset => CNT~30.OUTPUTSELECT
Reset => CNT~31.OUTPUTSELECT
Reset => CNT~32.OUTPUTSELECT
Reset => CNT~33.OUTPUTSELECT
Reset => CNT~34.OUTPUTSELECT
Reset => CNT~35.OUTPUTSELECT
Reset => CNT~36.OUTPUTSELECT
Reset => CNT~37.OUTPUTSELECT
Reset => CNT~38.OUTPUTSELECT
Reset => CNT~39.OUTPUTSELECT
Reset => CNT~40.OUTPUTSELECT
Reset => CNT~41.OUTPUTSELECT
Reset => CNT~42.OUTPUTSELECT
Reset => CNT~43.OUTPUTSELECT
Reset => CNT~44.OUTPUTSELECT
Reset => CNT~45.OUTPUTSELECT
Clock_8MHz => CNT[21].CLK
Clock_8MHz => CNT[20].CLK
Clock_8MHz => CNT[19].CLK
Clock_8MHz => CNT[18].CLK
Clock_8MHz => CNT[17].CLK
Clock_8MHz => CNT[16].CLK
Clock_8MHz => CNT[15].CLK
Clock_8MHz => CNT[14].CLK
Clock_8MHz => CNT[13].CLK
Clock_8MHz => CNT[12].CLK
Clock_8MHz => CNT[11].CLK
Clock_8MHz => CNT[10].CLK
Clock_8MHz => CNT[9].CLK
Clock_8MHz => CNT[8].CLK
Clock_8MHz => CNT[7].CLK
Clock_8MHz => CNT[6].CLK
Clock_8MHz => CNT[5].CLK
Clock_8MHz => CNT[4].CLK
Clock_8MHz => CNT[3].CLK
Clock_8MHz => CNT[2].CLK
Clock_8MHz => CNT[1].CLK
Clock_8MHz => CNT[0].CLK
Clock_8MHz => CNT[22].CLK
F_65536Hz <= CNT[1].DB_MAX_OUTPUT_PORT_TYPE
F_1Hz <= CNT[3].DB_MAX_OUTPUT_PORT_TYPE


