{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 17 20:29:28 2006 " "Info: Processing started: Mon Jul 17 20:29:28 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off gate_control -c gate_control " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off gate_control -c gate_control" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "fref~106 " "Info: Node \"fref~106\"" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0}  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dp_s100hz\$latch~10 " "Info: Node \"dp_s100hz\$latch~10\"" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0}  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dp_s10hz\$latch~10 " "Info: Node \"dp_s10hz\$latch~10\"" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0}  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dp_s1hz\$latch~10 " "Info: Node \"dp_s1hz\$latch~10\"" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0}  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "SW2 " "Info: Assuming node \"SW2\" is an undefined clock" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 14 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW2" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "f100hz " "Info: Assuming node \"f100hz\" is an undefined clock" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 15 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "f100hz" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW1 " "Info: Assuming node \"SW1\" is an undefined clock" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 14 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW1" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "f10hz " "Info: Assuming node \"f10hz\" is an undefined clock" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 15 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "f10hz" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "f1hz " "Info: Assuming node \"f1hz\" is an undefined clock" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 15 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "f1hz" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW0 " "Info: Assuming node \"SW0\" is an undefined clock" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 14 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW0" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "fref~106 " "Info: Detected gated clock \"fref~106\" as buffer" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fref~106" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "always0~10sexp " "Info: Detected gated clock \"always0~10sexp\" as buffer" {  } { { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "always0~10sexp" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "fref~94 " "Info: Detected gated clock \"fref~94\" as buffer" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fref~94" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "fref~100 " "Info: Detected gated clock \"fref~100\" as buffer" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fref~100" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW2 register wire_1 register wire_2 48.54 MHz 20.6 ns Internal " "Info: Clock \"SW2\" has Internal fmax of 48.54 MHz between source register \"wire_1\" and destination register \"wire_2\" (period= 20.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wire_1 1 REG LC5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns wire_2 2 REG LC6 2 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 72.22 % " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 27.78 % " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_2 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.600 ns - Smallest " "Info: - Smallest clock skew is -4.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 destination 8.500 ns + Shortest register " "Info: + Shortest clock path from clock \"SW2\" to destination register is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW2 1 CLK PIN_28 17 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_28; Fanout = 17; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { SW2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 4.800 ns fref~106 2 COMB LOOP LC4 4 " "Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { SW2 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 8.500 ns wire_2 3 REG LC6 2 " "Info: 3: + IC(1.000 ns) + CELL(2.700 ns) = 8.500 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns 88.24 % " "Info: Total cell delay = 7.500 ns ( 88.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 11.76 % " "Info: Total interconnect delay = 1.000 ns ( 11.76 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.500 ns" { SW2 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { SW2 SW2~out fref~106 wire_2 } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 source 13.100 ns - Longest register " "Info: - Longest clock path from clock \"SW2\" to source register is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW2 1 CLK PIN_28 17 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_28; Fanout = 17; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { SW2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~94 2 COMB LC8 3 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { SW2 fref~94 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.400 ns fref~106 3 COMB LOOP LC4 4 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~94 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 13.100 ns wire_1 4 REG LC5 4 " "Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.100 ns 84.73 % " "Info: Total cell delay = 11.100 ns ( 84.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.27 % " "Info: Total interconnect delay = 2.000 ns ( 15.27 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "13.100 ns" { SW2 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { SW2 SW2~out fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.500 ns" { SW2 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { SW2 SW2~out fref~106 wire_2 } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "13.100 ns" { SW2 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { SW2 SW2~out fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_2 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.500 ns" { SW2 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { SW2 SW2~out fref~106 wire_2 } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "13.100 ns" { SW2 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { SW2 SW2~out fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "f100hz register wire_1 register wire_2 87.72 MHz 11.4 ns Internal " "Info: Clock \"f100hz\" has Internal fmax of 87.72 MHz between source register \"wire_1\" and destination register \"wire_2\" (period= 11.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wire_1 1 REG LC5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns wire_2 2 REG LC6 2 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 72.22 % " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 27.78 % " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_2 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f100hz destination 13.100 ns + Shortest register " "Info: + Shortest clock path from clock \"f100hz\" to destination register is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns f100hz 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'f100hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { f100hz } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~94 2 COMB LC8 3 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { f100hz fref~94 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.400 ns fref~106 3 COMB LOOP LC4 4 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~94 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 13.100 ns wire_2 4 REG LC6 2 " "Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.100 ns 84.73 % " "Info: Total cell delay = 11.100 ns ( 84.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.27 % " "Info: Total interconnect delay = 2.000 ns ( 15.27 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "13.100 ns" { f100hz fref~94 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { f100hz f100hz~out fref~94 fref~106 wire_2 } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f100hz source 13.100 ns - Longest register " "Info: - Longest clock path from clock \"f100hz\" to source register is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns f100hz 1 CLK PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 1; CLK Node = 'f100hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { f100hz } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~94 2 COMB LC8 3 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { f100hz fref~94 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.400 ns fref~106 3 COMB LOOP LC4 4 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~94 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 13.100 ns wire_1 4 REG LC5 4 " "Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.100 ns 84.73 % " "Info: Total cell delay = 11.100 ns ( 84.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.27 % " "Info: Total interconnect delay = 2.000 ns ( 15.27 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "13.100 ns" { f100hz fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { f100hz f100hz~out fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "13.100 ns" { f100hz fref~94 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { f100hz f100hz~out fref~94 fref~106 wire_2 } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "13.100 ns" { f100hz fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { f100hz f100hz~out fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_2 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "13.100 ns" { f100hz fref~94 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { f100hz f100hz~out fref~94 fref~106 wire_2 } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "13.100 ns" { f100hz fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { f100hz f100hz~out fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW1 register wire_1 register wire_2 33.56 MHz 29.8 ns Internal " "Info: Clock \"SW1\" has Internal fmax of 33.56 MHz between source register \"wire_1\" and destination register \"wire_2\" (period= 29.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wire_1 1 REG LC5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns wire_2 2 REG LC6 2 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 72.22 % " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 27.78 % " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_2 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-9.200 ns - Smallest " "Info: - Smallest clock skew is -9.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 8.500 ns + Shortest register " "Info: + Shortest clock path from clock \"SW1\" to destination register is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW1 1 CLK PIN_16 15 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_16; Fanout = 15; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { SW1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 4.800 ns fref~106 2 COMB LOOP LC4 4 " "Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { SW1 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 8.500 ns wire_2 3 REG LC6 2 " "Info: 3: + IC(1.000 ns) + CELL(2.700 ns) = 8.500 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns 88.24 % " "Info: Total cell delay = 7.500 ns ( 88.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 11.76 % " "Info: Total interconnect delay = 1.000 ns ( 11.76 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.500 ns" { SW1 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { SW1 SW1~out fref~106 wire_2 } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 source 17.700 ns - Longest register " "Info: - Longest clock path from clock \"SW1\" to source register is 17.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW1 1 CLK PIN_16 15 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_16; Fanout = 15; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { SW1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~100 2 COMB LC9 1 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC9; Fanout = 1; COMB Node = 'fref~100'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { SW1 fref~100 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 9.400 ns fref~94 3 COMB LC8 3 " "Info: 3: + IC(1.000 ns) + CELL(3.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~100 fref~94 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 14.000 ns fref~106 4 COMB LOOP LC4 4 " "Info: 4: + IC(0.000 ns) + CELL(4.600 ns) = 14.000 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~94 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 17.700 ns wire_1 5 REG LC5 4 " "Info: 5: + IC(1.000 ns) + CELL(2.700 ns) = 17.700 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.700 ns 83.05 % " "Info: Total cell delay = 14.700 ns ( 83.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 16.95 % " "Info: Total interconnect delay = 3.000 ns ( 16.95 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { SW1 fref~100 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { SW1 SW1~out fref~100 fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.500 ns" { SW1 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { SW1 SW1~out fref~106 wire_2 } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { SW1 fref~100 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { SW1 SW1~out fref~100 fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_2 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.500 ns" { SW1 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { SW1 SW1~out fref~106 wire_2 } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { SW1 fref~100 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { SW1 SW1~out fref~100 fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "f10hz register wire_1 register wire_2 87.72 MHz 11.4 ns Internal " "Info: Clock \"f10hz\" has Internal fmax of 87.72 MHz between source register \"wire_1\" and destination register \"wire_2\" (period= 11.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wire_1 1 REG LC5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns wire_2 2 REG LC6 2 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 72.22 % " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 27.78 % " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_2 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f10hz destination 17.700 ns + Shortest register " "Info: + Shortest clock path from clock \"f10hz\" to destination register is 17.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns f10hz 1 CLK PIN_21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_21; Fanout = 1; CLK Node = 'f10hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { f10hz } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~100 2 COMB LC9 1 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC9; Fanout = 1; COMB Node = 'fref~100'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { f10hz fref~100 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 9.400 ns fref~94 3 COMB LC8 3 " "Info: 3: + IC(1.000 ns) + CELL(3.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~100 fref~94 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 14.000 ns fref~106 4 COMB LOOP LC4 4 " "Info: 4: + IC(0.000 ns) + CELL(4.600 ns) = 14.000 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~94 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 17.700 ns wire_2 5 REG LC6 2 " "Info: 5: + IC(1.000 ns) + CELL(2.700 ns) = 17.700 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.700 ns 83.05 % " "Info: Total cell delay = 14.700 ns ( 83.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 16.95 % " "Info: Total interconnect delay = 3.000 ns ( 16.95 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { f10hz fref~100 fref~94 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { f10hz f10hz~out fref~100 fref~94 fref~106 wire_2 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f10hz source 17.700 ns - Longest register " "Info: - Longest clock path from clock \"f10hz\" to source register is 17.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns f10hz 1 CLK PIN_21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_21; Fanout = 1; CLK Node = 'f10hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { f10hz } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~100 2 COMB LC9 1 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC9; Fanout = 1; COMB Node = 'fref~100'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { f10hz fref~100 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 9.400 ns fref~94 3 COMB LC8 3 " "Info: 3: + IC(1.000 ns) + CELL(3.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~100 fref~94 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 14.000 ns fref~106 4 COMB LOOP LC4 4 " "Info: 4: + IC(0.000 ns) + CELL(4.600 ns) = 14.000 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~94 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 17.700 ns wire_1 5 REG LC5 4 " "Info: 5: + IC(1.000 ns) + CELL(2.700 ns) = 17.700 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.700 ns 83.05 % " "Info: Total cell delay = 14.700 ns ( 83.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 16.95 % " "Info: Total interconnect delay = 3.000 ns ( 16.95 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { f10hz fref~100 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { f10hz f10hz~out fref~100 fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { f10hz fref~100 fref~94 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { f10hz f10hz~out fref~100 fref~94 fref~106 wire_2 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { f10hz fref~100 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { f10hz f10hz~out fref~100 fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_2 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { f10hz fref~100 fref~94 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { f10hz f10hz~out fref~100 fref~94 fref~106 wire_2 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { f10hz fref~100 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { f10hz f10hz~out fref~100 fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "f1hz register wire_1 register wire_2 87.72 MHz 11.4 ns Internal " "Info: Clock \"f1hz\" has Internal fmax of 87.72 MHz between source register \"wire_1\" and destination register \"wire_2\" (period= 11.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wire_1 1 REG LC5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns wire_2 2 REG LC6 2 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 72.22 % " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 27.78 % " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_2 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f1hz destination 17.700 ns + Shortest register " "Info: + Shortest clock path from clock \"f1hz\" to destination register is 17.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns f1hz 1 CLK PIN_20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_20; Fanout = 1; CLK Node = 'f1hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { f1hz } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~100 2 COMB LC9 1 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC9; Fanout = 1; COMB Node = 'fref~100'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { f1hz fref~100 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 9.400 ns fref~94 3 COMB LC8 3 " "Info: 3: + IC(1.000 ns) + CELL(3.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~100 fref~94 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 14.000 ns fref~106 4 COMB LOOP LC4 4 " "Info: 4: + IC(0.000 ns) + CELL(4.600 ns) = 14.000 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~94 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 17.700 ns wire_2 5 REG LC6 2 " "Info: 5: + IC(1.000 ns) + CELL(2.700 ns) = 17.700 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.700 ns 83.05 % " "Info: Total cell delay = 14.700 ns ( 83.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 16.95 % " "Info: Total interconnect delay = 3.000 ns ( 16.95 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { f1hz fref~100 fref~94 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { f1hz f1hz~out fref~100 fref~94 fref~106 wire_2 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f1hz source 17.700 ns - Longest register " "Info: - Longest clock path from clock \"f1hz\" to source register is 17.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns f1hz 1 CLK PIN_20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_20; Fanout = 1; CLK Node = 'f1hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { f1hz } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~100 2 COMB LC9 1 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC9; Fanout = 1; COMB Node = 'fref~100'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { f1hz fref~100 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 9.400 ns fref~94 3 COMB LC8 3 " "Info: 3: + IC(1.000 ns) + CELL(3.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~100 fref~94 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 14.000 ns fref~106 4 COMB LOOP LC4 4 " "Info: 4: + IC(0.000 ns) + CELL(4.600 ns) = 14.000 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~94 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 17.700 ns wire_1 5 REG LC5 4 " "Info: 5: + IC(1.000 ns) + CELL(2.700 ns) = 17.700 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.700 ns 83.05 % " "Info: Total cell delay = 14.700 ns ( 83.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 16.95 % " "Info: Total interconnect delay = 3.000 ns ( 16.95 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { f1hz fref~100 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { f1hz f1hz~out fref~100 fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { f1hz fref~100 fref~94 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { f1hz f1hz~out fref~100 fref~94 fref~106 wire_2 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { f1hz fref~100 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { f1hz f1hz~out fref~100 fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_2 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { f1hz fref~100 fref~94 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { f1hz f1hz~out fref~100 fref~94 fref~106 wire_2 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { f1hz fref~100 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { f1hz f1hz~out fref~100 fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW0 register wire_1 register wire_2 56.82 MHz 17.6 ns Internal " "Info: Clock \"SW0\" has Internal fmax of 56.82 MHz between source register \"wire_1\" and destination register \"wire_2\" (period= 17.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wire_1 1 REG LC5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns wire_2 2 REG LC6 2 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 72.22 % " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 27.78 % " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_2 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.100 ns - Smallest " "Info: - Smallest clock skew is -3.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW0 destination 8.500 ns + Shortest register " "Info: + Shortest clock path from clock \"SW0\" to destination register is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW0 1 CLK PIN_33 9 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_33; Fanout = 9; CLK Node = 'SW0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { SW0 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 4.800 ns fref~106 2 COMB LOOP LC4 4 " "Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { SW0 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 8.500 ns wire_2 3 REG LC6 2 " "Info: 3: + IC(1.000 ns) + CELL(2.700 ns) = 8.500 ns; Loc. = LC6; Fanout = 2; REG Node = 'wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns 88.24 % " "Info: Total cell delay = 7.500 ns ( 88.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 11.76 % " "Info: Total interconnect delay = 1.000 ns ( 11.76 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.500 ns" { SW0 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { SW0 SW0~out fref~106 wire_2 } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW0 source 11.600 ns - Longest register " "Info: - Longest clock path from clock \"SW0\" to source register is 11.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW0 1 CLK PIN_33 9 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_33; Fanout = 9; CLK Node = 'SW0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { SW0 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.100 ns) 4.300 ns always0~10sexp 2 COMB SEXP1 8 " "Info: 2: + IC(1.000 ns) + CELL(3.100 ns) = 4.300 ns; Loc. = SEXP1; Fanout = 8; COMB Node = 'always0~10sexp'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.100 ns" { SW0 always0~10sexp } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.600 ns) 7.900 ns fref~106 3 COMB LOOP LC4 4 " "Info: 3: + IC(0.000 ns) + CELL(3.600 ns) = 7.900 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { always0~10sexp fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 11.600 ns wire_1 4 REG LC5 4 " "Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 11.600 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.600 ns 82.76 % " "Info: Total cell delay = 9.600 ns ( 82.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 17.24 % " "Info: Total interconnect delay = 2.000 ns ( 17.24 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "11.600 ns" { SW0 always0~10sexp fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "11.600 ns" { SW0 SW0~out always0~10sexp fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.100ns 3.600ns 2.700ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.500 ns" { SW0 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { SW0 SW0~out fref~106 wire_2 } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "11.600 ns" { SW0 always0~10sexp fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "11.600 ns" { SW0 SW0~out always0~10sexp fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.100ns 3.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 63 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_2 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.500 ns" { SW0 fref~106 wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { SW0 SW0~out fref~106 wire_2 } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "11.600 ns" { SW0 always0~10sexp fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "11.600 ns" { SW0 SW0~out always0~10sexp fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.100ns 3.600ns 2.700ns } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "SW2 2 " "Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock \"SW2\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "wire_1 wire_1 SW2 1.4 ns " "Info: Found hold time violation between source  pin or register \"wire_1\" and destination pin or register \"wire_1\" for clock \"SW2\" (Hold time is 1.4 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.600 ns + Largest " "Info: + Largest clock skew is 4.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 destination 13.100 ns + Longest register " "Info: + Longest clock path from clock \"SW2\" to destination register is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW2 1 CLK PIN_28 17 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_28; Fanout = 17; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { SW2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~94 2 COMB LC8 3 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { SW2 fref~94 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.400 ns fref~106 3 COMB LOOP LC4 4 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~94 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 13.100 ns wire_1 4 REG LC5 4 " "Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.100 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.100 ns 84.73 % " "Info: Total cell delay = 11.100 ns ( 84.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.27 % " "Info: Total interconnect delay = 2.000 ns ( 15.27 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "13.100 ns" { SW2 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { SW2 SW2~out fref~94 fref~106 wire_1 } { 0.0ns 0.0ns 1.0ns 0.0ns 1.0ns } { 0.0ns 0.2ns 3.6ns 4.6ns 2.7ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 source 8.500 ns - Shortest register " "Info: - Shortest clock path from clock \"SW2\" to source register is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW2 1 CLK PIN_28 17 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_28; Fanout = 17; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { SW2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 4.800 ns fref~106 2 COMB LOOP LC4 4 " "Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { SW2 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 8.500 ns wire_1 3 REG LC5 4 " "Info: 3: + IC(1.000 ns) + CELL(2.700 ns) = 8.500 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns 88.24 % " "Info: Total cell delay = 7.500 ns ( 88.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 11.76 % " "Info: Total interconnect delay = 1.000 ns ( 11.76 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.500 ns" { SW2 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { SW2 SW2~out fref~106 wire_1 } { 0.0ns 0.0ns 0.0ns 1.0ns } { 0.0ns 0.2ns 4.6ns 2.7ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "13.100 ns" { SW2 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { SW2 SW2~out fref~94 fref~106 wire_1 } { 0.0ns 0.0ns 1.0ns 0.0ns 1.0ns } { 0.0ns 0.2ns 3.6ns 4.6ns 2.7ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.500 ns" { SW2 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { SW2 SW2~out fref~106 wire_1 } { 0.0ns 0.0ns 0.0ns 1.0ns } { 0.0ns 0.2ns 4.6ns 2.7ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns - " "Info: - Micro clock to output delay of source is 1.300 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns - Shortest register register " "Info: - Shortest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wire_1 1 REG LC5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.600 ns) 3.600 ns wire_1 2 REG LC5 4 " "Info: 2: + IC(0.000 ns) + CELL(3.600 ns) = 3.600 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_1 } { 0.0ns 0.0ns } { 0.0ns 3.6ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "13.100 ns" { SW2 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { SW2 SW2~out fref~94 fref~106 wire_1 } { 0.0ns 0.0ns 1.0ns 0.0ns 1.0ns } { 0.0ns 0.2ns 3.6ns 4.6ns 2.7ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.500 ns" { SW2 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { SW2 SW2~out fref~106 wire_1 } { 0.0ns 0.0ns 0.0ns 1.0ns } { 0.0ns 0.2ns 4.6ns 2.7ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_1 } { 0.0ns 0.0ns } { 0.0ns 3.6ns } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "SW1 2 " "Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock \"SW1\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "wire_1 wire_1 SW1 6.0 ns " "Info: Found hold time violation between source  pin or register \"wire_1\" and destination pin or register \"wire_1\" for clock \"SW1\" (Hold time is 6.0 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "9.200 ns + Largest " "Info: + Largest clock skew is 9.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 17.700 ns + Longest register " "Info: + Longest clock path from clock \"SW1\" to destination register is 17.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW1 1 CLK PIN_16 15 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_16; Fanout = 15; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { SW1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~100 2 COMB LC9 1 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC9; Fanout = 1; COMB Node = 'fref~100'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { SW1 fref~100 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 9.400 ns fref~94 3 COMB LC8 3 " "Info: 3: + IC(1.000 ns) + CELL(3.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~100 fref~94 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 14.000 ns fref~106 4 COMB LOOP LC4 4 " "Info: 4: + IC(0.000 ns) + CELL(4.600 ns) = 14.000 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~94 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 17.700 ns wire_1 5 REG LC5 4 " "Info: 5: + IC(1.000 ns) + CELL(2.700 ns) = 17.700 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.700 ns 83.05 % " "Info: Total cell delay = 14.700 ns ( 83.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 16.95 % " "Info: Total interconnect delay = 3.000 ns ( 16.95 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { SW1 fref~100 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { SW1 SW1~out fref~100 fref~94 fref~106 wire_1 } { 0.0ns 0.0ns 1.0ns 1.0ns 0.0ns 1.0ns } { 0.0ns 0.2ns 3.6ns 3.6ns 4.6ns 2.7ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 source 8.500 ns - Shortest register " "Info: - Shortest clock path from clock \"SW1\" to source register is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW1 1 CLK PIN_16 15 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_16; Fanout = 15; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { SW1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 4.800 ns fref~106 2 COMB LOOP LC4 4 " "Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { SW1 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 8.500 ns wire_1 3 REG LC5 4 " "Info: 3: + IC(1.000 ns) + CELL(2.700 ns) = 8.500 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns 88.24 % " "Info: Total cell delay = 7.500 ns ( 88.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 11.76 % " "Info: Total interconnect delay = 1.000 ns ( 11.76 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.500 ns" { SW1 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { SW1 SW1~out fref~106 wire_1 } { 0.0ns 0.0ns 0.0ns 1.0ns } { 0.0ns 0.2ns 4.6ns 2.7ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { SW1 fref~100 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { SW1 SW1~out fref~100 fref~94 fref~106 wire_1 } { 0.0ns 0.0ns 1.0ns 1.0ns 0.0ns 1.0ns } { 0.0ns 0.2ns 3.6ns 3.6ns 4.6ns 2.7ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.500 ns" { SW1 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { SW1 SW1~out fref~106 wire_1 } { 0.0ns 0.0ns 0.0ns 1.0ns } { 0.0ns 0.2ns 4.6ns 2.7ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns - " "Info: - Micro clock to output delay of source is 1.300 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns - Shortest register register " "Info: - Shortest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wire_1 1 REG LC5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.600 ns) 3.600 ns wire_1 2 REG LC5 4 " "Info: 2: + IC(0.000 ns) + CELL(3.600 ns) = 3.600 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns 100.00 % " "Info: Total cell delay = 3.600 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_1 } { 0.0ns 0.0ns } { 0.0ns 3.6ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { SW1 fref~100 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { SW1 SW1~out fref~100 fref~94 fref~106 wire_1 } { 0.0ns 0.0ns 1.0ns 1.0ns 0.0ns 1.0ns } { 0.0ns 0.2ns 3.6ns 3.6ns 4.6ns 2.7ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.500 ns" { SW1 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { SW1 SW1~out fref~106 wire_1 } { 0.0ns 0.0ns 0.0ns 1.0ns } { 0.0ns 0.2ns 4.6ns 2.7ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { wire_1 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { wire_1 wire_1 } { 0.0ns 0.0ns } { 0.0ns 3.6ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "f1hz Latch_EN wire_1 23.800 ns register " "Info: tco from clock \"f1hz\" to destination pin \"Latch_EN\" through register \"wire_1\" is 23.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f1hz source 17.700 ns + Longest register " "Info: + Longest clock path from clock \"f1hz\" to source register is 17.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns f1hz 1 CLK PIN_20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_20; Fanout = 1; CLK Node = 'f1hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { f1hz } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns fref~100 2 COMB LC9 1 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC9; Fanout = 1; COMB Node = 'fref~100'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { f1hz fref~100 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 9.400 ns fref~94 3 COMB LC8 3 " "Info: 3: + IC(1.000 ns) + CELL(3.600 ns) = 9.400 ns; Loc. = LC8; Fanout = 3; COMB Node = 'fref~94'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~100 fref~94 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 14.000 ns fref~106 4 COMB LOOP LC4 4 " "Info: 4: + IC(0.000 ns) + CELL(4.600 ns) = 14.000 ns; Loc. = LC4; Fanout = 4; COMB LOOP Node = 'fref~106'" { { "Info" "ITDB_PART_OF_SCC" "fref~106 LC4 " "Info: Loc. = LC4; Node \"fref~106\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { fref~94 fref~106 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 17.700 ns wire_1 5 REG LC5 4 " "Info: 5: + IC(1.000 ns) + CELL(2.700 ns) = 17.700 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.700 ns" { fref~106 wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.700 ns 83.05 % " "Info: Total cell delay = 14.700 ns ( 83.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 16.95 % " "Info: Total interconnect delay = 3.000 ns ( 16.95 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { f1hz fref~100 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { f1hz f1hz~out fref~100 fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.800 ns + Longest register pin " "Info: + Longest register to pin delay is 4.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wire_1 1 REG LC5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 4; REG Node = 'wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.600 ns Latch_EN~11 2 COMB LC7 1 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.600 ns; Loc. = LC7; Fanout = 1; COMB Node = 'Latch_EN~11'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.600 ns" { wire_1 Latch_EN~11 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.800 ns Latch_EN 3 PIN PIN_11 0 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 4.800 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'Latch_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "0.200 ns" { Latch_EN~11 Latch_EN } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 79.17 % " "Info: Total cell delay = 3.800 ns ( 79.17 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 20.83 % " "Info: Total interconnect delay = 1.000 ns ( 20.83 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.800 ns" { wire_1 Latch_EN~11 Latch_EN } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.800 ns" { wire_1 Latch_EN~11 Latch_EN } { 0.000ns 1.000ns 0.000ns } { 0.000ns 3.600ns 0.200ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "17.700 ns" { f1hz fref~100 fref~94 fref~106 wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "17.700 ns" { f1hz f1hz~out fref~100 fref~94 fref~106 wire_1 } { 0.000ns 0.000ns 1.000ns 1.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 3.600ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.800 ns" { wire_1 Latch_EN~11 Latch_EN } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.800 ns" { wire_1 Latch_EN~11 Latch_EN } { 0.000ns 1.000ns 0.000ns } { 0.000ns 3.600ns 0.200ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SW2 dp_s100hz 8.100 ns Longest " "Info: Longest tpd from source pin \"SW2\" to destination pin \"dp_s100hz\" is 8.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns SW2 1 CLK PIN_28 17 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_28; Fanout = 17; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { SW2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.100 ns) 4.300 ns always0~10sexp 2 COMB SEXP1 8 " "Info: 2: + IC(1.000 ns) + CELL(3.100 ns) = 4.300 ns; Loc. = SEXP1; Fanout = 8; COMB Node = 'always0~10sexp'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "4.100 ns" { SW2 always0~10sexp } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.600 ns) 7.900 ns dp_s100hz\$latch~10 3 COMB LOOP LC3 3 " "Info: 3: + IC(0.000 ns) + CELL(3.600 ns) = 7.900 ns; Loc. = LC3; Fanout = 3; COMB LOOP Node = 'dp_s100hz\$latch~10'" { { "Info" "ITDB_PART_OF_SCC" "dp_s100hz\$latch~10 LC3 " "Info: Loc. = LC3; Node \"dp_s100hz\$latch~10\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { dp_s100hz$latch~10 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "" { dp_s100hz$latch~10 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "3.600 ns" { always0~10sexp dp_s100hz$latch~10 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.100 ns dp_s100hz 4 PIN PIN_6 0 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 8.100 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'dp_s100hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "0.200 ns" { dp_s100hz$latch~10 dp_s100hz } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/gate_control.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.100 ns 87.65 % " "Info: Total cell delay = 7.100 ns ( 87.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 12.35 % " "Info: Total interconnect delay = 1.000 ns ( 12.35 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control_cmp.qrpt" Compiler "gate_control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/db/gate_control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/gate_control/" "" "8.100 ns" { SW2 always0~10sexp dp_s100hz$latch~10 dp_s100hz } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.100 ns" { SW2 SW2~out always0~10sexp dp_s100hz$latch~10 dp_s100hz } { 0.000ns 0.000ns 1.000ns 0.000ns 0.000ns } { 0.000ns 0.200ns 3.100ns 3.600ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 4 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 17 20:29:32 2006 " "Info: Processing ended: Mon Jul 17 20:29:32 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}
