
module scan(EN_in1,EN_in0,sdata);

output [1:0] sdata;
input  EN_in1;
input  EN_in0;

reg [1:0] sdata;
wire EN_in;

assign EN_in = EN_in1 | EN_in0;

always @(posedge EN_in)
begin
	sdata <= sdata + 2'b01;
end
endmodule








