{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 17 11:16:47 2006 " "Info: Processing started: Mon Jul 17 11:16:47 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off num1_1 -c num1_1 " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off num1_1 -c num1_1" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a y 5.000 ns Longest " "Info: Longest tpd from source pin \"a\" to destination pin \"y\" is 5.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns a 1 PIN PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 1; PIN Node = 'a'" {  } { { "E:/戴仙金/资料/Verilog书/num1_1/db/num1_1_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/num1_1/db/num1_1_cmp.qrpt" Compiler "num1_1" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/num1_1/db/num1_1.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/num1_1/" "" "" { a } "NODE_NAME" } "" } } { "num1_1.v" "" { Text "E:/戴仙金/资料/Verilog书/num1_1/num1_1.v" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns y~4 2 COMB LC1 1 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC1; Fanout = 1; COMB Node = 'y~4'" {  } { { "E:/戴仙金/资料/Verilog书/num1_1/db/num1_1_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/num1_1/db/num1_1_cmp.qrpt" Compiler "num1_1" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/num1_1/db/num1_1.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/num1_1/" "" "4.600 ns" { a y~4 } "NODE_NAME" } "" } } { "num1_1.v" "" { Text "E:/戴仙金/资料/Verilog书/num1_1/num1_1.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.000 ns y 3 PIN PIN_4 0 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 5.000 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'y'" {  } { { "E:/戴仙金/资料/Verilog书/num1_1/db/num1_1_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/num1_1/db/num1_1_cmp.qrpt" Compiler "num1_1" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/num1_1/db/num1_1.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/num1_1/" "" "0.200 ns" { y~4 y } "NODE_NAME" } "" } } { "num1_1.v" "" { Text "E:/戴仙金/资料/Verilog书/num1_1/num1_1.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 80.00 % " "Info: Total cell delay = 4.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 20.00 % " "Info: Total interconnect delay = 1.000 ns ( 20.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/num1_1/db/num1_1_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/num1_1/db/num1_1_cmp.qrpt" Compiler "num1_1" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/num1_1/db/num1_1.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/num1_1/" "" "5.000 ns" { a y~4 y } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.000 ns" { a a~out y~4 y } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 0.200ns 3.600ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 17 11:16:48 2006 " "Info: Processing ended: Mon Jul 17 11:16:48 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}
