{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 08 00:45:44 2006 " "Info: Processing started: Tue Aug 08 00:45:44 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off Now_Direction_Disp -c Now_Direction_Disp " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Now_Direction_Disp -c Now_Direction_Disp" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Direction_Disp_Row1\[1\]\$latch~10 " "Info: Node \"Direction_Disp_Row1\[1\]\$latch~10\"" {  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } }  } 0}  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Direction_Disp_Row1\[2\]\$latch~10 " "Info: Node \"Direction_Disp_Row1\[2\]\$latch~10\"" {  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } }  } 0}  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Direction_Disp_Row1\[4\]\$latch~10 " "Info: Node \"Direction_Disp_Row1\[4\]\$latch~10\"" {  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } }  } 0}  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Direction_Disp_Row1\[5\]\$latch~10 " "Info: Node \"Direction_Disp_Row1\[5\]\$latch~10\"" {  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } }  } 0}  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Direction_Disp_Row1\[6\]\$latch~14 " "Info: Node \"Direction_Disp_Row1\[6\]\$latch~14\"" {  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } }  } 0}  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clock_1KHz " "Info: Assuming node \"Clock_1KHz\" is an undefined clock" {  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 11 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Clock_1KHz" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clock_1KHz register Direction_Disp_Row2\[1\]~reg0 register Direction_Disp_Row2\[4\]~reg0 172.41 MHz 5.8 ns Internal " "Info: Clock \"Clock_1KHz\" has Internal fmax of 172.41 MHz between source register \"Direction_Disp_Row2\[1\]~reg0\" and destination register \"Direction_Disp_Row2\[4\]~reg0\" (period= 5.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.700 ns + Longest register register " "Info: + Longest register to register delay is 3.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Direction_Disp_Row2\[1\]~reg0 1 REG LC21 31 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC21; Fanout = 31; REG Node = 'Direction_Disp_Row2\[1\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "" { Direction_Disp_Row2[1]~reg0 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 25 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.600 ns) 3.700 ns Direction_Disp_Row2\[4\]~reg0 2 REG LC16 26 " "Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.700 ns; Loc. = LC16; Fanout = 26; REG Node = 'Direction_Disp_Row2\[4\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "3.700 ns" { Direction_Disp_Row2[1]~reg0 Direction_Disp_Row2[4]~reg0 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 70.27 % " "Info: Total cell delay = 2.600 ns ( 70.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 29.73 % " "Info: Total interconnect delay = 1.100 ns ( 29.73 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "3.700 ns" { Direction_Disp_Row2[1]~reg0 Direction_Disp_Row2[4]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.700 ns" { Direction_Disp_Row2[1]~reg0 Direction_Disp_Row2[4]~reg0 } { 0.000ns 1.100ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_1KHz destination 1.300 ns + Shortest register " "Info: + Shortest clock path from clock \"Clock_1KHz\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns Clock_1KHz 1 CLK PIN_43 5 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 5; CLK Node = 'Clock_1KHz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "" { Clock_1KHz } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns Direction_Disp_Row2\[4\]~reg0 2 REG LC16 26 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC16; Fanout = 26; REG Node = 'Direction_Disp_Row2\[4\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "0.100 ns" { Clock_1KHz Direction_Disp_Row2[4]~reg0 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "1.300 ns" { Clock_1KHz Direction_Disp_Row2[4]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_1KHz Clock_1KHz~out Direction_Disp_Row2[4]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_1KHz source 1.300 ns - Longest register " "Info: - Longest clock path from clock \"Clock_1KHz\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns Clock_1KHz 1 CLK PIN_43 5 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 5; CLK Node = 'Clock_1KHz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "" { Clock_1KHz } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns Direction_Disp_Row2\[1\]~reg0 2 REG LC21 31 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC21; Fanout = 31; REG Node = 'Direction_Disp_Row2\[1\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "0.100 ns" { Clock_1KHz Direction_Disp_Row2[1]~reg0 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "1.300 ns" { Clock_1KHz Direction_Disp_Row2[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_1KHz Clock_1KHz~out Direction_Disp_Row2[1]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "1.300 ns" { Clock_1KHz Direction_Disp_Row2[4]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_1KHz Clock_1KHz~out Direction_Disp_Row2[4]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "1.300 ns" { Clock_1KHz Direction_Disp_Row2[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_1KHz Clock_1KHz~out Direction_Disp_Row2[1]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 25 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 25 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "3.700 ns" { Direction_Disp_Row2[1]~reg0 Direction_Disp_Row2[4]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.700 ns" { Direction_Disp_Row2[1]~reg0 Direction_Disp_Row2[4]~reg0 } { 0.000ns 1.100ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "1.300 ns" { Clock_1KHz Direction_Disp_Row2[4]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_1KHz Clock_1KHz~out Direction_Disp_Row2[4]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "1.300 ns" { Clock_1KHz Direction_Disp_Row2[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_1KHz Clock_1KHz~out Direction_Disp_Row2[1]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clock_1KHz Direction_Disp_Row1\[0\] Direction_Disp_Row2\[1\]~reg0 17.600 ns register " "Info: tco from clock \"Clock_1KHz\" to destination pin \"Direction_Disp_Row1\[0\]\" through register \"Direction_Disp_Row2\[1\]~reg0\" is 17.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_1KHz source 1.300 ns + Longest register " "Info: + Longest clock path from clock \"Clock_1KHz\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns Clock_1KHz 1 CLK PIN_43 5 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 5; CLK Node = 'Clock_1KHz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "" { Clock_1KHz } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns Direction_Disp_Row2\[1\]~reg0 2 REG LC21 31 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC21; Fanout = 31; REG Node = 'Direction_Disp_Row2\[1\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "0.100 ns" { Clock_1KHz Direction_Disp_Row2[1]~reg0 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "1.300 ns" { Clock_1KHz Direction_Disp_Row2[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_1KHz Clock_1KHz~out Direction_Disp_Row2[1]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 25 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.000 ns + Longest register pin " "Info: + Longest register to pin delay is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Direction_Disp_Row2\[1\]~reg0 1 REG LC21 31 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC21; Fanout = 31; REG Node = 'Direction_Disp_Row2\[1\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "" { Direction_Disp_Row2[1]~reg0 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 25 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.600 ns) 3.700 ns Direction_Disp_Row1~1105 2 COMB LC9 1 " "Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.700 ns; Loc. = LC9; Fanout = 1; COMB Node = 'Direction_Disp_Row1~1105'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "3.700 ns" { Direction_Disp_Row2[1]~reg0 Direction_Disp_Row1~1105 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 5.600 ns Direction_Disp_Row1~1070 3 COMB LC10 3 " "Info: 3: + IC(0.000 ns) + CELL(1.900 ns) = 5.600 ns; Loc. = LC10; Fanout = 3; COMB Node = 'Direction_Disp_Row1~1070'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "1.900 ns" { Direction_Disp_Row1~1105 Direction_Disp_Row1~1070 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 10.200 ns Direction_Disp_Row1\[6\]\$latch~14 4 COMB LOOP LC17 5 " "Info: 4: + IC(0.000 ns) + CELL(4.600 ns) = 10.200 ns; Loc. = LC17; Fanout = 5; COMB LOOP Node = 'Direction_Disp_Row1\[6\]\$latch~14'" { { "Info" "ITDB_PART_OF_SCC" "Direction_Disp_Row1\[6\]\$latch~14 LC17 " "Info: Loc. = LC17; Node \"Direction_Disp_Row1\[6\]\$latch~14\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "" { Direction_Disp_Row1[6]$latch~14 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "" { Direction_Disp_Row1[6]$latch~14 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "4.600 ns" { Direction_Disp_Row1~1070 Direction_Disp_Row1[6]$latch~14 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 14.800 ns Direction_Disp_Row1\[6\]\$latch~18 5 COMB LC22 1 " "Info: 5: + IC(1.000 ns) + CELL(3.600 ns) = 14.800 ns; Loc. = LC22; Fanout = 1; COMB Node = 'Direction_Disp_Row1\[6\]\$latch~18'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "4.600 ns" { Direction_Disp_Row1[6]$latch~14 Direction_Disp_Row1[6]$latch~18 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 15.000 ns Direction_Disp_Row1\[0\] 6 PIN PIN_36 0 " "Info: 6: + IC(0.000 ns) + CELL(0.200 ns) = 15.000 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'Direction_Disp_Row1\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "0.200 ns" { Direction_Disp_Row1[6]$latch~18 Direction_Disp_Row1[0] } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.900 ns 86.00 % " "Info: Total cell delay = 12.900 ns ( 86.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 14.00 % " "Info: Total interconnect delay = 2.100 ns ( 14.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "15.000 ns" { Direction_Disp_Row2[1]~reg0 Direction_Disp_Row1~1105 Direction_Disp_Row1~1070 Direction_Disp_Row1[6]$latch~14 Direction_Disp_Row1[6]$latch~18 Direction_Disp_Row1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "15.000 ns" { Direction_Disp_Row2[1]~reg0 Direction_Disp_Row1~1105 Direction_Disp_Row1~1070 Direction_Disp_Row1[6]$latch~14 Direction_Disp_Row1[6]$latch~18 Direction_Disp_Row1[0] } { 0.000ns 1.100ns 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 2.600ns 1.900ns 4.600ns 3.600ns 0.200ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "1.300 ns" { Clock_1KHz Direction_Disp_Row2[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_1KHz Clock_1KHz~out Direction_Disp_Row2[1]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "15.000 ns" { Direction_Disp_Row2[1]~reg0 Direction_Disp_Row1~1105 Direction_Disp_Row1~1070 Direction_Disp_Row1[6]$latch~14 Direction_Disp_Row1[6]$latch~18 Direction_Disp_Row1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "15.000 ns" { Direction_Disp_Row2[1]~reg0 Direction_Disp_Row1~1105 Direction_Disp_Row1~1070 Direction_Disp_Row1[6]$latch~14 Direction_Disp_Row1[6]$latch~18 Direction_Disp_Row1[0] } { 0.000ns 1.100ns 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 2.600ns 1.900ns 4.600ns 3.600ns 0.200ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "En Direction_Disp_Row1\[0\] 14.200 ns Longest " "Info: Longest tpd from source pin \"En\" to destination pin \"Direction_Disp_Row1\[0\]\" is 14.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns En 1 PIN PIN_16 6 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_16; Fanout = 6; PIN Node = 'En'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "" { En } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns Direction_Disp_Row1~1070 2 COMB LC10 3 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC10; Fanout = 3; COMB Node = 'Direction_Disp_Row1~1070'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "4.600 ns" { En Direction_Disp_Row1~1070 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.400 ns Direction_Disp_Row1\[6\]\$latch~14 3 COMB LOOP LC17 5 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.400 ns; Loc. = LC17; Fanout = 5; COMB LOOP Node = 'Direction_Disp_Row1\[6\]\$latch~14'" { { "Info" "ITDB_PART_OF_SCC" "Direction_Disp_Row1\[6\]\$latch~14 LC17 " "Info: Loc. = LC17; Node \"Direction_Disp_Row1\[6\]\$latch~14\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "" { Direction_Disp_Row1[6]$latch~14 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "" { Direction_Disp_Row1[6]$latch~14 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "4.600 ns" { Direction_Disp_Row1~1070 Direction_Disp_Row1[6]$latch~14 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 14.000 ns Direction_Disp_Row1\[6\]\$latch~18 4 COMB LC22 1 " "Info: 4: + IC(1.000 ns) + CELL(3.600 ns) = 14.000 ns; Loc. = LC22; Fanout = 1; COMB Node = 'Direction_Disp_Row1\[6\]\$latch~18'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "4.600 ns" { Direction_Disp_Row1[6]$latch~14 Direction_Disp_Row1[6]$latch~18 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 14.200 ns Direction_Disp_Row1\[0\] 5 PIN PIN_36 0 " "Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 14.200 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'Direction_Disp_Row1\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "0.200 ns" { Direction_Disp_Row1[6]$latch~18 Direction_Disp_Row1[0] } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.200 ns 85.92 % " "Info: Total cell delay = 12.200 ns ( 85.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 14.08 % " "Info: Total interconnect delay = 2.000 ns ( 14.08 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Slave_Control/Now_Direction_Disp/" "" "14.200 ns" { En Direction_Disp_Row1~1070 Direction_Disp_Row1[6]$latch~14 Direction_Disp_Row1[6]$latch~18 Direction_Disp_Row1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "14.200 ns" { En En~out Direction_Disp_Row1~1070 Direction_Disp_Row1[6]$latch~14 Direction_Disp_Row1[6]$latch~18 Direction_Disp_Row1[0] } { 0.000ns 0.000ns 1.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 3.600ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 08 00:45:45 2006 " "Info: Processing ended: Tue Aug 08 00:45:45 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}
