Analysis & Synthesis report for Data_Read
Thu Aug 03 20:39:49 2006
Version 4.2 Build 157 12/07/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Hierarchy
  5. Analysis & Synthesis Resource Utilization by Entity
  6. Analysis & Synthesis Equations
  7. Analysis & Synthesis Source Files Read
  8. Analysis & Synthesis Resource Usage Summary
  9. WYSIWYG Cells
 10. General Register Statistics
 11. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
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licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Aug 03 20:39:49 2006    ;
; Quartus II Version          ; 4.2 Build 157 12/07/2004 SJ Full Version ;
; Revision Name               ; Data_Read                                ;
; Top-level Entity Name       ; Data_Read                                ;
; Family                      ; ACEX1K                                   ;
; Total logic elements        ; 28                                       ;
; Total pins                  ; 16                                       ;
; Total memory bits           ; 0                                        ;
; Total PLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                       ;
+------------------------------------------------------+--------------+---------------+
; Option                                               ; Setting      ; Default Value ;
+------------------------------------------------------+--------------+---------------+
; Family name                                          ; ACEX1K       ; Stratix       ;
; Use smart compilation                                ; Normal       ; Normal        ;
; Create Debugging Nodes for IP Cores                  ; off          ; off           ;
; Preserve fewer node names                            ; On           ; On            ;
; Disable OpenCore Plus hardware evaluation            ; Off          ; Off           ;
; Verilog Version                                      ; Verilog_2001 ; Verilog_2001  ;
; VHDL Version                                         ; VHDL93       ; VHDL93        ;
; Top-level entity name                                ; Data_Read    ; Data_Read     ;
; State Machine Processing                             ; Auto         ; Auto          ;
; Extract Verilog State Machines                       ; On           ; On            ;
; Extract VHDL State Machines                          ; On           ; On            ;
; NOT Gate Push-Back                                   ; On           ; On            ;
; Power-Up Don't Care                                  ; On           ; On            ;
; Remove Redundant Logic Cells                         ; Off          ; Off           ;
; Remove Duplicate Registers                           ; On           ; On            ;
; Ignore CARRY Buffers                                 ; Off          ; Off           ;
; Ignore CASCADE Buffers                               ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                            ; Off          ; Off           ;
; Ignore LCELL Buffers                                 ; Off          ; Off           ;
; Ignore SOFT Buffers                                  ; On           ; On            ;
; Limit AHDL Integers to 32 Bits                       ; Off          ; Off           ;
; Auto Implement in ROM                                ; Off          ; Off           ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K ; Area         ; Area          ;
; Carry Chain Length -- FLEX 10K                       ; 32           ; 32            ;
; Cascade Chain Length                                 ; 2            ; 2             ;
; Auto Carry Chains                                    ; On           ; On            ;
; Auto Open-Drain Pins                                 ; On           ; On            ;
; Remove Duplicate Logic                               ; On           ; On            ;
; Auto ROM Replacement                                 ; On           ; On            ;
; Auto RAM Replacement                                 ; On           ; On            ;
; Auto Clock Enable Replacement                        ; On           ; On            ;
; Auto Resource Sharing                                ; Off          ; Off           ;
; Allow Any RAM Size For Recognition                   ; Off          ; Off           ;
; Allow Any ROM Size For Recognition                   ; Off          ; Off           ;
+------------------------------------------------------+--------------+---------------+


+-----------+
; Hierarchy ;
+-----------+
Data_Read
 |-- lpm_counter:cnt_rtl_0
      |-- alt_counter_f10ke:wysi_counter


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------+
; Compilation Hierarchy Node             ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                             ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------+
; |Data_Read                             ; 28 (24)     ; 16           ; 0           ; 16   ; 12 (12)      ; 12 (12)           ; 4 (0)            ; 4 (0)           ; |Data_Read                                                      ;
;    |lpm_counter:cnt_rtl_0|             ; 4 (0)       ; 4            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |Data_Read|lpm_counter:cnt_rtl_0                                ;
;       |alt_counter_f10ke:wysi_counter| ; 4 (4)       ; 4            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |Data_Read|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+-----------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.map.eqn.


+--------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                               ;
+----------------------------------+-----------------+---------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                                                    ;
+----------------------------------+-----------------+---------------------------------------------------------------------------------+
; Data_Read.v                      ; yes             ; E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v ;
; lpm_counter.tdf                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf                     ;
; lpm_constant.inc                 ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_constant.inc                    ;
; lpm_decode.inc                   ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_decode.inc                      ;
; lpm_add_sub.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_add_sub.inc                     ;
; cmpconst.inc                     ; yes             ; d:/altera/quartus42/libraries/megafunctions/cmpconst.inc                        ;
; lpm_compare.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_compare.inc                     ;
; lpm_counter.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.inc                     ;
; dffeea.inc                       ; yes             ; d:/altera/quartus42/libraries/megafunctions/dffeea.inc                          ;
; alt_synch_counter.inc            ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter.inc               ;
; alt_synch_counter_f.inc          ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter_f.inc             ;
; alt_counter_f10ke.inc            ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.inc               ;
; alt_counter_stratix.inc          ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_counter_stratix.inc             ;
; aglobal42.inc                    ; yes             ; d:/altera/quartus42/libraries/megafunctions/aglobal42.inc                       ;
; alt_counter_f10ke.tdf            ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf               ;
; flex10ke_lcell.inc               ; yes             ; d:/altera/quartus42/libraries/megafunctions/flex10ke_lcell.inc                  ;
+----------------------------------+-----------------+---------------------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 28      ;
; Total combinational functions     ; 16      ;
; Total 4-input functions           ; 12      ;
; Total 3-input functions           ; 0       ;
; Total 2-input functions           ; 0       ;
; Total 1-input functions           ; 0       ;
; Total 0-input functions           ; 4       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 16      ;
; Total logic cells in carry chains ; 4       ;
; I/O pins                          ; 16      ;
; Maximum fan-out node              ; Adc_SCL ;
; Maximum fan-out                   ; 16      ;
; Total fan-out                     ; 103     ;
; Average fan-out                   ; 2.34    ;
+-----------------------------------+---------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 4     ;
; Number of synthesis-generated cells                    ; 24    ;
; Number of WYSIWYG LUTs                                 ; 4     ;
; Number of synthesis-generated LUTs                     ; 12    ;
; Number of WYSIWYG registers                            ; 4     ;
; Number of synthesis-generated registers                ; 12    ;
; Number of cells with combinational logic only          ; 12    ;
; Number of cells with registers only                    ; 12    ;
; Number of cells with combinational logic and registers ; 4     ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 16    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 12    ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Thu Aug 03 20:39:46 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Data_Read -c Data_Read
Info: Found 1 design units, including 1 entities, in source file Data_Read.v
    Info: Found entity 1: Data_Read
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "cnt[0]~4"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Warning: Design contains 2 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "En"
    Warning: No output dependent on input pin "Reset"
Info: Implemented 44 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 12 output pins
    Info: Implemented 28 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Processing ended: Thu Aug 03 20:39:49 2006
    Info: Elapsed time: 00:00:04


