module  Serial(Clock,Serial_Out);
input   Clock;
output  [7:0]Serial_Out;

reg  [7:0]Serial_Out;

always  @(posedge Clock)

begin
  if(Serial_Out != 8'b10000000)
    Serial_Out <= (1 << Serial_Out);
  else
    Serial_Out <= 8'b10000000;
end

endmodule