module Data_drive(
					En,
					Reset,
					Clk_SCL,
					SampleCtrl_in,
					Adc_Conv,
					Adc_SCL
					);
input  En;
input  Reset;
input  Clk_SCL;
input  SampleCtrl_in;
output Adc_Conv;
output Adc_SCL;

reg Adc_Conv;
//reg Adc_SCL;
reg [5:0] cnt1;
reg Adc_SCL_Select;

always @(posedge Clk_SCL)
begin
  if((Reset == 1'b1) || (En == 1'b1))
  begin
	Adc_Conv <= 1'b1;
	//Adc_SCL  <= 1'b0;
  end
  else
  begin
    if(SampleCtrl_in == 1'b1)
    begin
      if(cnt1 == 5'b11111)
      begin
        cnt1 <= 5'b0;
        Adc_Conv <= 1'b1;
        Adc_SCL_Select <= 1'b0;
      end
      else if(cnt1 < 5'b01111)
      begin
        cnt1 <= cnt1 + 5'b1;
        Adc_Conv <= 1'b0;
        Adc_SCL_Select <= 1'b1;
      end
      else if(cnt1 > 5'b11100)
      begin
        cnt1 <= cnt1 + 5'b1;
        Adc_Conv <= 1'b1;
        Adc_SCL_Select <= 1'b0;
      end
      else
      begin
        cnt1 <= cnt1 + 5'b1;
        Adc_Conv <= 1'b0;
        Adc_SCL_Select <= 1'b0;
      end
    end
  end
end
/*
always @(Clk_SCL or Reset or En or SampleCtrl_in or Adc_SCL_Select)
begin
  if((Reset == 1'b1) || (En == 1'b1))
  begin
	//Adc_Conv <= 1'b1;
	Adc_SCL  <= 1'b0;
  end
  else
  begin
    if(SampleCtrl_in == 1'b1)
    begin
      Adc_SCL  <= (Clk_SCL && Adc_Conv);
      //Adc_Conv <= 1'b0;       
    end
    else
    begin
	  //Adc_Conv <= 1'b1;
      Adc_SCL  <= 1'b0;
    end
  end
end
*/

assign Adc_SCL = Clk_SCL && Adc_SCL_Select;

endmodule