Timing Analyzer report for maincontrol
Sat Jul 15 14:59:31 2006
Version 4.2 Build 157 12/07/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'SW3'
  6. tco
  7. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                           ;
+------------------------------+-------+---------------+----------------------------------+-------------------+--------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From              ; To           ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-------------------+--------------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 2.800 ns                         ; Timepiece_EN~reg0 ; Timepiece_EN ; SW3        ;          ; 0            ;
; Clock Setup: 'SW3'           ; N/A   ; None          ; 175.44 MHz ( period = 5.700 ns ) ; Function[2]       ; Function[0]  ; SW3        ; SW3      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                   ;              ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+-------------------+--------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM7032SLC44-5     ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; SW3             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'SW3'                                                                                                                                                                      ;
+-------+----------------------------------+-------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)             ; From        ; To                 ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+-------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[0] ; Alarmclock_EN~reg0 ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[1] ; Alarmclock_EN~reg0 ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[2] ; Alarmclock_EN~reg0 ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[0] ; TimeSet_EN~reg0    ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[1] ; TimeSet_EN~reg0    ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[2] ; TimeSet_EN~reg0    ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[0] ; DateSet_EN~reg0    ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[1] ; DateSet_EN~reg0    ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[2] ; DateSet_EN~reg0    ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[0] ; Date_EN~reg0       ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[1] ; Date_EN~reg0       ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[2] ; Date_EN~reg0       ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[0] ; Stopwatch_EN~reg0  ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[1] ; Stopwatch_EN~reg0  ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[2] ; Stopwatch_EN~reg0  ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[0] ; Timepiece_EN~reg0  ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[1] ; Timepiece_EN~reg0  ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[2] ; Timepiece_EN~reg0  ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[0] ; Function[2]        ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[1] ; Function[2]        ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[2] ; Function[2]        ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[0] ; Function[1]        ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[1] ; Function[1]        ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[2] ; Function[1]        ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[0] ; Function[0]        ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[1] ; Function[0]        ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; Function[2] ; Function[0]        ; SW3        ; SW3      ; None                        ; None                      ; 3.600 ns                ;
+-------+----------------------------------+-------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------------------+
; tco                                                                                 ;
+-------+--------------+------------+--------------------+---------------+------------+
; Slack ; Required tco ; Actual tco ; From               ; To            ; From Clock ;
+-------+--------------+------------+--------------------+---------------+------------+
; N/A   ; None         ; 2.800 ns   ; Alarmclock_EN~reg0 ; Alarmclock_EN ; SW3        ;
; N/A   ; None         ; 2.800 ns   ; TimeSet_EN~reg0    ; TimeSet_EN    ; SW3        ;
; N/A   ; None         ; 2.800 ns   ; DateSet_EN~reg0    ; DateSet_EN    ; SW3        ;
; N/A   ; None         ; 2.800 ns   ; Date_EN~reg0       ; Date_EN       ; SW3        ;
; N/A   ; None         ; 2.800 ns   ; Stopwatch_EN~reg0  ; Stopwatch_EN  ; SW3        ;
; N/A   ; None         ; 2.800 ns   ; Timepiece_EN~reg0  ; Timepiece_EN  ; SW3        ;
+-------+--------------+------------+--------------------+---------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Sat Jul 15 14:59:31 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off maincontrol -c maincontrol
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "SW3" is an undefined clock
Info: Clock "SW3" has Internal fmax of 175.44 MHz between source register "Function[0]" and destination register "Alarmclock_EN~reg0" (period= 5.7 ns)
    Info: + Longest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC15; Fanout = 12; REG Node = 'Function[0]'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC7; Fanout = 1; REG Node = 'Alarmclock_EN~reg0'
        Info: Total cell delay = 2.600 ns ( 72.22 % )
        Info: Total interconnect delay = 1.000 ns ( 27.78 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "SW3" to destination register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'SW3'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC7; Fanout = 1; REG Node = 'Alarmclock_EN~reg0'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
        Info: - Longest clock path from clock "SW3" to source register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'SW3'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC15; Fanout = 12; REG Node = 'Function[0]'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
Info: tco from clock "SW3" to destination pin "Alarmclock_EN" through register "Alarmclock_EN~reg0" is 2.800 ns
    Info: + Longest clock path from clock "SW3" to source register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 9; CLK Node = 'SW3'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC7; Fanout = 1; REG Node = 'Alarmclock_EN~reg0'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Longest register to pin delay is 0.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7; Fanout = 1; REG Node = 'Alarmclock_EN~reg0'
        Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'Alarmclock_EN'
        Info: Total cell delay = 0.200 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Jul 15 14:59:31 2006
    Info: Elapsed time: 00:00:01


