{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 08 23:59:43 2006 " "Info: Processing started: Tue Aug 08 23:59:43 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off Serial -c Serial " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Serial -c Serial" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Serial.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Serial.v" { { "Info" "ISGN_ENTITY_NAME" "1 Serial " "Info: Found entity 1: Serial" {  } { { "Serial.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Serial/Serial.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 Serial.v(11) " "Warning: Verilog HDL assignment warning at Serial.v(11): truncated value with size 32 to match size of target (8)" {  } { { "Serial.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/Serial/Serial.v" 11 0 0 } }  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "Clock " "Info: Promoted clock signal driven by pin \"Clock\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "17 " "Info: Implemented 17 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "8 " "Info: Implemented 8 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 08 23:59:44 2006 " "Info: Processing ended: Tue Aug 08 23:59:44 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}
