Analysis & Synthesis report for dispdecoder
Mon Jul 17 22:27:22 2006
Version 4.2 Build 157 12/07/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Hierarchy
  5. User-Specified and Inferred Latches
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis Equations
  8. Analysis & Synthesis Source Files Read
  9. Analysis & Synthesis Resource Usage Summary
 10. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Jul 17 22:27:22 2006    ;
; Quartus II Version          ; 4.2 Build 157 12/07/2004 SJ Full Version ;
; Revision Name               ; dispdecoder                              ;
; Top-level Entity Name       ; dispdecoder                              ;
; Family                      ; MAX7000S                                 ;
; Total macrocells            ; 10                                       ;
; Total pins                  ; 43                                       ;
+-----------------------------+------------------------------------------+


+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                       ;
+----------------------------------------------------------------------+--------------+---------------+
; Option                                                               ; Setting      ; Default Value ;
+----------------------------------------------------------------------+--------------+---------------+
; Family name                                                          ; MAX7000S     ; Stratix       ;
; Use smart compilation                                                ; Normal       ; Normal        ;
; Create Debugging Nodes for IP Cores                                  ; off          ; off           ;
; Preserve fewer node names                                            ; On           ; On            ;
; Disable OpenCore Plus hardware evaluation                            ; Off          ; Off           ;
; Verilog Version                                                      ; Verilog_2001 ; Verilog_2001  ;
; VHDL Version                                                         ; VHDL93       ; VHDL93        ;
; Top-level entity name                                                ; dispdecoder  ; dispdecoder   ;
; State Machine Processing                                             ; Auto         ; Auto          ;
; Extract Verilog State Machines                                       ; On           ; On            ;
; Extract VHDL State Machines                                          ; On           ; On            ;
; NOT Gate Push-Back                                                   ; On           ; On            ;
; Power-Up Don't Care                                                  ; On           ; On            ;
; Remove Redundant Logic Cells                                         ; Off          ; Off           ;
; Remove Duplicate Registers                                           ; On           ; On            ;
; Ignore CARRY Buffers                                                 ; Off          ; Off           ;
; Ignore CASCADE Buffers                                               ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                                ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                                            ; Off          ; Off           ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A           ; Auto         ; Auto          ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A            ; Off          ; Off           ;
; Limit AHDL Integers to 32 Bits                                       ; Off          ; Off           ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A         ; Speed        ; Speed         ;
; Allow XOR Gate Usage                                                 ; On           ; On            ;
; Auto Logic Cell Insertion                                            ; On           ; On            ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4            ; 4             ;
; Auto Parallel Expanders                                              ; On           ; On            ;
; Auto Open-Drain Pins                                                 ; On           ; On            ;
; Remove Duplicate Logic                                               ; On           ; On            ;
; Auto Resource Sharing                                                ; Off          ; Off           ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A   ; 100          ; 100           ;
+----------------------------------------------------------------------+--------------+---------------+


+-----------+
; Hierarchy ;
+-----------+
dispdecoder


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; data_out[6]$latch                             ;   ;
; data_out[5]$latch                             ;   ;
; data_out[4]$latch                             ;   ;
; data_out[3]$latch                             ;   ;
; data_out[2]$latch                             ;   ;
; data_out[1]$latch                             ;   ;
; data_out[0]$latch                             ;   ;
; Number of user-specified and inferred latches ; 7 ;
+-----------------------------------------------+---+


+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                  ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |dispdecoder               ; 10         ; 43   ; |dispdecoder        ;
+----------------------------+------------+------+---------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.map.eqn.


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                   ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                                        ;
+----------------------------------+-----------------+---------------------------------------------------------------------+
; dispdecoder.v                    ; yes             ; E:/戴仙金/资料/Verilog书/源代码/cymometer/dispdecoder/dispdecoder.v ;
+----------------------------------+-----------------+---------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 10                   ;
; Total registers      ; 0                    ;
; I/O pins             ; 43                   ;
; Shareable expanders  ; 13                   ;
; Maximum fan-out node ; data_in[2]           ;
; Maximum fan-out      ; 12                   ;
; Total fan-out        ; 117                  ;
; Average fan-out      ; 1.77                 ;
+----------------------+----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Mon Jul 17 22:27:19 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off dispdecoder -c dispdecoder
Info: Found 1 design units, including 1 entities, in source file dispdecoder.v
    Info: Found entity 1: dispdecoder
Warning: Verilog HDL unsupported feature warning at dispdecoder.v(26): Initial Construct is not supported and will be ignored
Warning: Verilog HDL Always Construct warning at dispdecoder.v(28): variable data_out may not be assigned a new value in every possible path through the Always Construct.  Variable data_out holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Design contains 4 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "Q0[3]"
    Warning: No output dependent on input pin "Q0[2]"
    Warning: No output dependent on input pin "Q0[1]"
    Warning: No output dependent on input pin "Q0[0]"
Info: Implemented 66 device resources after synthesis - the final resource count might be different
    Info: Implemented 35 input pins
    Info: Implemented 8 output pins
    Info: Implemented 10 macrocells
    Info: Implemented 13 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
    Info: Processing ended: Mon Jul 17 22:27:22 2006
    Info: Elapsed time: 00:00:04


