--A1L431Q is fifo_out[15]~reg0 at LC5_C20
--operation mode is normal

A1L431Q_lut_out = A1L42 # !A1L07 & A1L32 & B1_q[15];
A1L431Q = DFFEA(A1L431Q_lut_out, GLOBAL(clock), , , , , );


--A1L231Q is fifo_out[14]~reg0 at LC5_C21
--operation mode is normal

A1L231Q_lut_out = A1L62 # !A1L07 & B1_q[14] & A1L32;
A1L231Q = DFFEA(A1L231Q_lut_out, GLOBAL(clock), , , , , );


--A1L031Q is fifo_out[13]~reg0 at LC7_C21
--operation mode is normal

A1L031Q_lut_out = A1L82 # !A1L07 & B1_q[13] & A1L32;
A1L031Q = DFFEA(A1L031Q_lut_out, GLOBAL(clock), , , , , );


--A1L821Q is fifo_out[12]~reg0 at LC1_C21
--operation mode is normal

A1L821Q_lut_out = A1L03 # !A1L07 & B1_q[12] & A1L32;
A1L821Q = DFFEA(A1L821Q_lut_out, GLOBAL(clock), , , , , );


--A1L621Q is fifo_out[11]~reg0 at LC5_C17
--operation mode is normal

A1L621Q_lut_out = A1L23 # !A1L07 & B1_q[11] & A1L32;
A1L621Q = DFFEA(A1L621Q_lut_out, GLOBAL(clock), , , , , );


--A1L421Q is fifo_out[10]~reg0 at LC1_C17
--operation mode is normal

A1L421Q_lut_out = A1L43 # !A1L07 & B1_q[10] & A1L32;
A1L421Q = DFFEA(A1L421Q_lut_out, GLOBAL(clock), , , , , );


--A1L221Q is fifo_out[9]~reg0 at LC3_C16
--operation mode is normal

A1L221Q_lut_out = A1L63 # !A1L07 & B1_q[9] & A1L32;
A1L221Q = DFFEA(A1L221Q_lut_out, GLOBAL(clock), , , , , );


--A1L021Q is fifo_out[8]~reg0 at LC8_C18
--operation mode is normal

A1L021Q_lut_out = A1L83 # !A1L07 & B1_q[8] & A1L32;
A1L021Q = DFFEA(A1L021Q_lut_out, GLOBAL(clock), , , , , );


--A1L811Q is fifo_out[7]~reg0 at LC4_C23
--operation mode is normal

A1L811Q_lut_out = A1L04 # !A1L07 & B1_q[7] & A1L32;
A1L811Q = DFFEA(A1L811Q_lut_out, GLOBAL(clock), , , , , );


--A1L611Q is fifo_out[6]~reg0 at LC1_C22
--operation mode is normal

A1L611Q_lut_out = A1L24 # !A1L07 & B1_q[6] & A1L32;
A1L611Q = DFFEA(A1L611Q_lut_out, GLOBAL(clock), , , , , );


--A1L411Q is fifo_out[5]~reg0 at LC1_C24
--operation mode is normal

A1L411Q_lut_out = A1L44 # !A1L07 & B1_q[5] & A1L32;
A1L411Q = DFFEA(A1L411Q_lut_out, GLOBAL(clock), , , , , );


--A1L211Q is fifo_out[4]~reg0 at LC8_C24
--operation mode is normal

A1L211Q_lut_out = A1L64 # !A1L07 & B1_q[4] & A1L32;
A1L211Q = DFFEA(A1L211Q_lut_out, GLOBAL(clock), , , , , );


--A1L011Q is fifo_out[3]~reg0 at LC6_C17
--operation mode is normal

A1L011Q_lut_out = A1L84 # !A1L07 & B1_q[3] & A1L32;
A1L011Q = DFFEA(A1L011Q_lut_out, GLOBAL(clock), , , , , );


--A1L801Q is fifo_out[2]~reg0 at LC1_C16
--operation mode is normal

A1L801Q_lut_out = A1L05 # !A1L07 & B1_q[2] & A1L32;
A1L801Q = DFFEA(A1L801Q_lut_out, GLOBAL(clock), , , , , );


--A1L601Q is fifo_out[1]~reg0 at LC1_C23
--operation mode is normal

A1L601Q_lut_out = A1L25 # !A1L07 & B1_q[1] & A1L32;
A1L601Q = DFFEA(A1L601Q_lut_out, GLOBAL(clock), , , , , );


--A1L401Q is fifo_out[0]~reg0 at LC4_C22
--operation mode is normal

A1L401Q_lut_out = A1L45 # !A1L07 & B1_q[0] & A1L32;
A1L401Q = DFFEA(A1L401Q_lut_out, GLOBAL(clock), , , , , );


--counter[3] is counter[3] at LC3_C19
--operation mode is normal

counter[3]_lut_out = !reset & counter[3] $ (A1L12 & !A1L55);
counter[3] = DFFEA(counter[3]_lut_out, GLOBAL(clock), , , , , );


--counter[2] is counter[2] at LC5_C19
--operation mode is normal

counter[2]_lut_out = !reset & counter[2] $ (A1L12 & !A1L65);
counter[2] = DFFEA(counter[2]_lut_out, GLOBAL(clock), , , , , );


--counter[1] is counter[1] at LC2_C19
--operation mode is normal

counter[1]_lut_out = !reset & counter[1] $ (A1L75 & A1L12);
counter[1] = DFFEA(counter[1]_lut_out, GLOBAL(clock), , , , , );


--counter[0] is counter[0] at LC1_C18
--operation mode is normal

counter[0]_lut_out = !reset & read $ write $ counter[0];
counter[0] = DFFEA(counter[0]_lut_out, GLOBAL(clock), , , , , );


--A1L241 is reduce_nor~0 at LC7_C19
--operation mode is normal

A1L241 = counter[0] # counter[1] # counter[2] # counter[3];


--A1L441 is reduce_nor~5 at LC1_C19
--operation mode is normal

A1L441 = counter[0] # counter[1] # counter[2] # !counter[3];


--A1L341 is reduce_nor~4 at LC4_C19
--operation mode is normal

A1L341 = !counter[3] # !counter[2] # !counter[1] # !counter[0];


--A1L22 is Select~4925 at LC1_C20
--operation mode is normal

A1L22 = !read & !reset & A1L431Q;


--A1L32 is Select~4926 at LC1_C15
--operation mode is normal

A1L32 = !reset & read;


--A1L42 is Select~4927 at LC2_C20
--operation mode is normal

A1L42 = A1L22 # A1L32 & A1L07 & fifo_in[15];


--B1_q[15] is altdpram:ram_rtl_0|q[15] at EC5_C
B1_q[15]_data_in = A1L61;
B1_q[15]_write_enable = A1L85;
B1_q[15]_clock_0 = GLOBAL(clock);
B1_q[15]_clock_1 = GLOBAL(clock);
B1_q[15]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02, A1L02, A1L02, A1L02, A1L02);
B1_q[15]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56, A1L56, A1L56, A1L56, A1L56);
B1_q[15] = MEMORY_SEGMENT(B1_q[15]_data_in, B1_q[15]_write_enable, B1_q[15]_clock_0, B1_q[15]_clock_1, , , , VCC, B1_q[15]_write_address, B1_q[15]_read_address);


--A1L52 is Select~4929 at LC2_C21
--operation mode is normal

A1L52 = !read & !reset & A1L231Q;


--A1L62 is Select~4930 at LC3_C21
--operation mode is normal

A1L62 = A1L52 # fifo_in[14] & A1L32 & A1L07;


--B1_q[14] is altdpram:ram_rtl_0|q[14] at EC15_C
B1_q[14]_data_in = A1L51;
B1_q[14]_write_enable = A1L85;
B1_q[14]_clock_0 = GLOBAL(clock);
B1_q[14]_clock_1 = GLOBAL(clock);
B1_q[14]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02, A1L02, A1L02, A1L02, A1L02);
B1_q[14]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56, A1L56, A1L56, A1L56, A1L56);
B1_q[14] = MEMORY_SEGMENT(B1_q[14]_data_in, B1_q[14]_write_enable, B1_q[14]_clock_0, B1_q[14]_clock_1, , , , VCC, B1_q[14]_write_address, B1_q[14]_read_address);


--A1L72 is Select~4932 at LC4_C21
--operation mode is normal

A1L72 = !read & !reset & A1L031Q;


--A1L82 is Select~4933 at LC6_C21
--operation mode is normal

A1L82 = A1L72 # fifo_in[13] & A1L32 & A1L07;


--B1_q[13] is altdpram:ram_rtl_0|q[13] at EC4_C
B1_q[13]_data_in = A1L41;
B1_q[13]_write_enable = A1L85;
B1_q[13]_clock_0 = GLOBAL(clock);
B1_q[13]_clock_1 = GLOBAL(clock);
B1_q[13]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02, A1L02, A1L02, A1L02, A1L02);
B1_q[13]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56, A1L56, A1L56, A1L56, A1L56);
B1_q[13] = MEMORY_SEGMENT(B1_q[13]_data_in, B1_q[13]_write_enable, B1_q[13]_clock_0, B1_q[13]_clock_1, , , , VCC, B1_q[13]_write_address, B1_q[13]_read_address);


--A1L92 is Select~4935 at LC4_C10
--operation mode is normal

A1L92 = !read & !reset & A1L821Q;


--A1L03 is Select~4936 at LC8_C21
--operation mode is normal

A1L03 = A1L92 # fifo_in[12] & A1L32 & A1L07;


--B1_q[12] is altdpram:ram_rtl_0|q[12] at EC12_C
B1_q[12]_data_in = A1L31;
B1_q[12]_write_enable = A1L85;
B1_q[12]_clock_0 = GLOBAL(clock);
B1_q[12]_clock_1 = GLOBAL(clock);
B1_q[12]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02, A1L02, A1L02, A1L02, A1L02);
B1_q[12]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56, A1L56, A1L56, A1L56, A1L56);
B1_q[12] = MEMORY_SEGMENT(B1_q[12]_data_in, B1_q[12]_write_enable, B1_q[12]_clock_0, B1_q[12]_clock_1, , , , VCC, B1_q[12]_write_address, B1_q[12]_read_address);


--A1L13 is Select~4938 at LC6_C18
--operation mode is normal

A1L13 = !read & !reset & A1L621Q;


--A1L23 is Select~4939 at LC2_C17
--operation mode is normal

A1L23 = A1L13 # fifo_in[11] & A1L32 & A1L07;


--B1_q[11] is altdpram:ram_rtl_0|q[11] at EC7_C
B1_q[11]_data_in = A1L21;
B1_q[11]_write_enable = A1L85;
B1_q[11]_clock_0 = GLOBAL(clock);
B1_q[11]_clock_1 = GLOBAL(clock);
B1_q[11]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02, A1L02, A1L02, A1L02, A1L02);
B1_q[11]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56, A1L56, A1L56, A1L56, A1L56);
B1_q[11] = MEMORY_SEGMENT(B1_q[11]_data_in, B1_q[11]_write_enable, B1_q[11]_clock_0, B1_q[11]_clock_1, , , , VCC, B1_q[11]_write_address, B1_q[11]_read_address);


--A1L33 is Select~4941 at LC3_C17
--operation mode is normal

A1L33 = !read & !reset & A1L421Q;


--A1L43 is Select~4942 at LC4_C17
--operation mode is normal

A1L43 = A1L33 # fifo_in[10] & A1L32 & A1L07;


--B1_q[10] is altdpram:ram_rtl_0|q[10] at EC14_C
B1_q[10]_data_in = A1L11;
B1_q[10]_write_enable = A1L85;
B1_q[10]_clock_0 = GLOBAL(clock);
B1_q[10]_clock_1 = GLOBAL(clock);
B1_q[10]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02, A1L02, A1L02, A1L02, A1L02);
B1_q[10]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56, A1L56, A1L56, A1L56, A1L56);
B1_q[10] = MEMORY_SEGMENT(B1_q[10]_data_in, B1_q[10]_write_enable, B1_q[10]_clock_0, B1_q[10]_clock_1, , , , VCC, B1_q[10]_write_address, B1_q[10]_read_address);


--A1L53 is Select~4944 at LC4_C16
--operation mode is normal

A1L53 = !read & !reset & A1L221Q;


--A1L63 is Select~4945 at LC6_C16
--operation mode is normal

A1L63 = A1L53 # fifo_in[9] & A1L32 & A1L07;


--B1_q[9] is altdpram:ram_rtl_0|q[9] at EC8_C
B1_q[9]_data_in = A1L01;
B1_q[9]_write_enable = A1L85;
B1_q[9]_clock_0 = GLOBAL(clock);
B1_q[9]_clock_1 = GLOBAL(clock);
B1_q[9]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02, A1L02, A1L02, A1L02, A1L02);
B1_q[9]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56, A1L56, A1L56, A1L56, A1L56);
B1_q[9] = MEMORY_SEGMENT(B1_q[9]_data_in, B1_q[9]_write_enable, B1_q[9]_clock_0, B1_q[9]_clock_1, , , , VCC, B1_q[9]_write_address, B1_q[9]_read_address);


--A1L73 is Select~4947 at LC3_C18
--operation mode is normal

A1L73 = !read & !reset & A1L021Q;


--A1L83 is Select~4948 at LC4_C18
--operation mode is normal

A1L83 = A1L73 # fifo_in[8] & A1L32 & A1L07;


--B1_q[8] is altdpram:ram_rtl_0|q[8] at EC13_C
B1_q[8]_data_in = A1L9;
B1_q[8]_write_enable = A1L85;
B1_q[8]_clock_0 = GLOBAL(clock);
B1_q[8]_clock_1 = GLOBAL(clock);
B1_q[8]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02, A1L02, A1L02, A1L02, A1L02);
B1_q[8]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56, A1L56, A1L56, A1L56, A1L56);
B1_q[8] = MEMORY_SEGMENT(B1_q[8]_data_in, B1_q[8]_write_enable, B1_q[8]_clock_0, B1_q[8]_clock_1, , , , VCC, B1_q[8]_write_address, B1_q[8]_read_address);


--A1L93 is Select~4950 at LC2_C23
--operation mode is normal

A1L93 = !read & !reset & A1L811Q;


--A1L04 is Select~4951 at LC3_C23
--operation mode is normal

A1L04 = A1L93 # fifo_in[7] & A1L32 & A1L07;


--B1_q[7] is altdpram:ram_rtl_0|q[7] at EC3_C
B1_q[7]_data_in = A1L8;
B1_q[7]_write_enable = A1L85;
B1_q[7]_clock_0 = GLOBAL(clock);
B1_q[7]_clock_1 = GLOBAL(clock);
B1_q[7]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02, A1L02, A1L02, A1L02, A1L02);
B1_q[7]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56, A1L56, A1L56, A1L56, A1L56);
B1_q[7] = MEMORY_SEGMENT(B1_q[7]_data_in, B1_q[7]_write_enable, B1_q[7]_clock_0, B1_q[7]_clock_1, , , , VCC, B1_q[7]_write_address, B1_q[7]_read_address);


--A1L14 is Select~4953 at LC2_C22
--operation mode is normal

A1L14 = !read & !reset & A1L611Q;


--A1L24 is Select~4954 at LC3_C22
--operation mode is normal

A1L24 = A1L14 # fifo_in[6] & A1L32 & A1L07;


--B1_q[6] is altdpram:ram_rtl_0|q[6] at EC11_C
B1_q[6]_data_in = A1L7;
B1_q[6]_write_enable = A1L85;
B1_q[6]_clock_0 = GLOBAL(clock);
B1_q[6]_clock_1 = GLOBAL(clock);
B1_q[6]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02, A1L02, A1L02, A1L02, A1L02);
B1_q[6]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56, A1L56, A1L56, A1L56, A1L56);
B1_q[6] = MEMORY_SEGMENT(B1_q[6]_data_in, B1_q[6]_write_enable, B1_q[6]_clock_0, B1_q[6]_clock_1, , , , VCC, B1_q[6]_write_address, B1_q[6]_read_address);


--A1L34 is Select~4956 at LC3_C24
--operation mode is normal

A1L34 = !read & !reset & A1L411Q;


--A1L44 is Select~4957 at LC4_C24
--operation mode is normal

A1L44 = A1L34 # fifo_in[5] & A1L32 & A1L07;


--B1_q[5] is altdpram:ram_rtl_0|q[5] at EC1_C
B1_q[5]_data_in = A1L6;
B1_q[5]_write_enable = A1L85;
B1_q[5]_clock_0 = GLOBAL(clock);
B1_q[5]_clock_1 = GLOBAL(clock);
B1_q[5]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02, A1L02, A1L02, A1L02, A1L02);
B1_q[5]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56, A1L56, A1L56, A1L56, A1L56);
B1_q[5] = MEMORY_SEGMENT(B1_q[5]_data_in, B1_q[5]_write_enable, B1_q[5]_clock_0, B1_q[5]_clock_1, , , , VCC, B1_q[5]_write_address, B1_q[5]_read_address);


--A1L54 is Select~4959 at LC5_C24
--operation mode is normal

A1L54 = !read & !reset & A1L211Q;


--A1L64 is Select~4960 at LC6_C24
--operation mode is normal

A1L64 = A1L54 # fifo_in[4] & A1L32 & A1L07;


--B1_q[4] is altdpram:ram_rtl_0|q[4] at EC9_C
B1_q[4]_data_in = A1L5;
B1_q[4]_write_enable = A1L85;
B1_q[4]_clock_0 = GLOBAL(clock);
B1_q[4]_clock_1 = GLOBAL(clock);
B1_q[4]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02, A1L02, A1L02, A1L02, A1L02);
B1_q[4]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56, A1L56, A1L56, A1L56, A1L56);
B1_q[4] = MEMORY_SEGMENT(B1_q[4]_data_in, B1_q[4]_write_enable, B1_q[4]_clock_0, B1_q[4]_clock_1, , , , VCC, B1_q[4]_write_address, B1_q[4]_read_address);


--A1L74 is Select~4962 at LC7_C17
--operation mode is normal

A1L74 = !read & !reset & A1L011Q;


--A1L84 is Select~4963 at LC8_C17
--operation mode is normal

A1L84 = A1L74 # fifo_in[3] & A1L32 & A1L07;


--B1_q[3] is altdpram:ram_rtl_0|q[3] at EC6_C
B1_q[3]_data_in = A1L4;
B1_q[3]_write_enable = A1L85;
B1_q[3]_clock_0 = GLOBAL(clock);
B1_q[3]_clock_1 = GLOBAL(clock);
B1_q[3]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02, A1L02, A1L02, A1L02, A1L02);
B1_q[3]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56, A1L56, A1L56, A1L56, A1L56);
B1_q[3] = MEMORY_SEGMENT(B1_q[3]_data_in, B1_q[3]_write_enable, B1_q[3]_clock_0, B1_q[3]_clock_1, , , , VCC, B1_q[3]_write_address, B1_q[3]_read_address);


--A1L94 is Select~4965 at LC7_C16
--operation mode is normal

A1L94 = !read & !reset & A1L801Q;


--A1L05 is Select~4966 at LC8_C16
--operation mode is normal

A1L05 = A1L94 # fifo_in[2] & A1L32 & A1L07;


--B1_q[2] is altdpram:ram_rtl_0|q[2] at EC16_C
B1_q[2]_data_in = A1L3;
B1_q[2]_write_enable = A1L85;
B1_q[2]_clock_0 = GLOBAL(clock);
B1_q[2]_clock_1 = GLOBAL(clock);
B1_q[2]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02, A1L02, A1L02, A1L02, A1L02);
B1_q[2]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56, A1L56, A1L56, A1L56, A1L56);
B1_q[2] = MEMORY_SEGMENT(B1_q[2]_data_in, B1_q[2]_write_enable, B1_q[2]_clock_0, B1_q[2]_clock_1, , , , VCC, B1_q[2]_write_address, B1_q[2]_read_address);


--A1L15 is Select~4968 at LC5_C23
--operation mode is normal

A1L15 = !read & !reset & A1L601Q;


--A1L25 is Select~4969 at LC6_C23
--operation mode is normal

A1L25 = A1L15 # fifo_in[1] & A1L32 & A1L07;


--B1_q[1] is altdpram:ram_rtl_0|q[1] at EC2_C
B1_q[1]_data_in = A1L2;
B1_q[1]_write_enable = A1L85;
B1_q[1]_clock_0 = GLOBAL(clock);
B1_q[1]_clock_1 = GLOBAL(clock);
B1_q[1]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02, A1L02, A1L02, A1L02, A1L02);
B1_q[1]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56, A1L56, A1L56, A1L56, A1L56);
B1_q[1] = MEMORY_SEGMENT(B1_q[1]_data_in, B1_q[1]_write_enable, B1_q[1]_clock_0, B1_q[1]_clock_1, , , , VCC, B1_q[1]_write_address, B1_q[1]_read_address);


--A1L35 is Select~4971 at LC5_C22
--operation mode is normal

A1L35 = !read & !reset & A1L401Q;


--A1L45 is Select~4972 at LC6_C22
--operation mode is normal

A1L45 = A1L35 # fifo_in[0] & A1L32 & A1L07;


--B1_q[0] is altdpram:ram_rtl_0|q[0] at EC10_C
B1_q[0]_data_in = A1L1;
B1_q[0]_write_enable = A1L85;
B1_q[0]_clock_0 = GLOBAL(clock);
B1_q[0]_clock_1 = GLOBAL(clock);
B1_q[0]_write_address = WR_ADDR(A1L71, A1L81, A1L91, A1L02, A1L02, A1L02, A1L02, A1L02);
B1_q[0]_read_address = RD_ADDR(A1L06, A1L36, A1L46, A1L56, A1L56, A1L56, A1L56, A1L56);
B1_q[0] = MEMORY_SEGMENT(B1_q[0]_data_in, B1_q[0]_write_enable, B1_q[0]_clock_0, B1_q[0]_clock_1, , , , VCC, B1_q[0]_write_address, B1_q[0]_read_address);


--A1L55 is Select~4974 at LC6_C19
--operation mode is normal

A1L55 = counter[0] & read # !counter[2] # !counter[1] # !counter[0] & counter[1] # counter[2] # !read;


--A1L12 is Select~478 at LC4_C15
--operation mode is normal

A1L12 = read $ write;


--A1L65 is Select~4976 at LC2_C18
--operation mode is normal

A1L65 = counter[0] & read # !counter[1] # !counter[0] & counter[1] # !read;


--A1L75 is Select~4978 at LC8_C19
--operation mode is normal

A1L75 = read $ counter[0];


--A1L61 is Select~288 at LC8_C20
--operation mode is normal

A1L61 = fifo_in[15] & write;


--A1L85 is Select~4982 at LC5_C15
--operation mode is normal

A1L85 = !reset & write & A1L241 # !read;


--write_ptr[0] is write_ptr[0] at LC2_C15
--operation mode is normal

write_ptr[0]_lut_out = !reset & !write & write_ptr[0] # !A1L17;
write_ptr[0] = DFFEA(write_ptr[0]_lut_out, GLOBAL(clock), , , , , );


--A1L71 is Select~289 at LC8_C15
--operation mode is normal

A1L71 = write & write_ptr[0];


--write_ptr[1] is write_ptr[1] at LC2_C12
--operation mode is normal

write_ptr[1]_lut_out = write_ptr[1] & A1L86 # !write_ptr[0] & A1L85 # !write_ptr[1] & write_ptr[0] & A1L85;
write_ptr[1] = DFFEA(write_ptr[1]_lut_out, GLOBAL(clock), , , , , );


--A1L81 is Select~290 at LC4_C12
--operation mode is normal

A1L81 = write & write_ptr[1];


--write_ptr[2] is write_ptr[2] at LC3_C12
--operation mode is normal

write_ptr[2]_lut_out = write_ptr[2] & A1L86 # !A1L47 & A1L85 # !write_ptr[2] & A1L47 & A1L85;
write_ptr[2] = DFFEA(write_ptr[2]_lut_out, GLOBAL(clock), , , , , );


--A1L91 is Select~291 at LC8_C12
--operation mode is normal

A1L91 = write & write_ptr[2];


--write_ptr[3] is write_ptr[3] at LC5_C12
--operation mode is normal

write_ptr[3]_lut_out = write_ptr[3] & A1L86 # !A1L57 & A1L85 # !write_ptr[3] & A1L57 & A1L85;
write_ptr[3] = DFFEA(write_ptr[3]_lut_out, GLOBAL(clock), , , , , );


--A1L02 is Select~292 at LC6_C12
--operation mode is normal

A1L02 = write & write_ptr[3];


--read_ptr[0] is read_ptr[0] at LC2_C14
--operation mode is normal

read_ptr[0]_lut_out = A1L95 # !read & !reset & read_ptr[0];
read_ptr[0] = DFFEA(read_ptr[0]_lut_out, GLOBAL(clock), , , , , );


--A1L95 is Select~4983 at LC3_C14
--operation mode is normal

A1L95 = A1L32 & read_ptr[0] $ (A1L241 # !write);


--A1L06 is Select~4984 at LC1_C14
--operation mode is normal

A1L06 = A1L95 # !read & !reset & read_ptr[0];


--A1L16 is Select~4985 at LC1_C13
--operation mode is normal

A1L16 = !reset & !A1L241 & write # !read;


--A1L26 is Select~4986 at LC2_C13
--operation mode is normal

A1L26 = !reset & read & A1L241 # !write;


--read_ptr[1] is read_ptr[1] at LC6_C13
--operation mode is normal

read_ptr[1]_lut_out = read_ptr[1] & A1L16 # !read_ptr[0] & A1L26 # !read_ptr[1] & read_ptr[0] & A1L26;
read_ptr[1] = DFFEA(read_ptr[1]_lut_out, GLOBAL(clock), , , , , );


--A1L36 is Select~4987 at LC8_C13
--operation mode is normal

A1L36 = read_ptr[1] & A1L16 # !read_ptr[0] & A1L26 # !read_ptr[1] & read_ptr[0] & A1L26;


--read_ptr[2] is read_ptr[2] at LC7_C13
--operation mode is normal

read_ptr[2]_lut_out = read_ptr[2] & A1L16 # !A1L27 & A1L26 # !read_ptr[2] & A1L27 & A1L26;
read_ptr[2] = DFFEA(read_ptr[2]_lut_out, GLOBAL(clock), , , , , );


--A1L27 is add~12 at LC5_C14
--operation mode is normal

A1L27 = read_ptr[0] & read_ptr[1];


--A1L46 is Select~4988 at LC4_C13
--operation mode is normal

A1L46 = read_ptr[2] & A1L16 # !A1L27 & A1L26 # !read_ptr[2] & A1L27 & A1L26;


--read_ptr[3] is read_ptr[3] at LC5_C13
--operation mode is normal

read_ptr[3]_lut_out = read_ptr[3] & A1L16 # !A1L37 & A1L26 # !read_ptr[3] & A1L37 & A1L26;
read_ptr[3] = DFFEA(read_ptr[3]_lut_out, GLOBAL(clock), , , , , );


--A1L37 is add~17 at LC4_C14
--operation mode is normal

A1L37 = read_ptr[0] & read_ptr[1] & read_ptr[2];


--A1L56 is Select~4989 at LC3_C13
--operation mode is normal

A1L56 = read_ptr[3] & A1L16 # !A1L37 & A1L26 # !read_ptr[3] & A1L37 & A1L26;


--A1L51 is Select~287 at LC1_C3
--operation mode is normal

A1L51 = fifo_in[14] & write;


--A1L41 is Select~286 at LC4_C11
--operation mode is normal

A1L41 = fifo_in[13] & write;


--A1L31 is Select~285 at LC1_C8
--operation mode is normal

A1L31 = fifo_in[12] & write;


--A1L21 is Select~284 at LC1_C6
--operation mode is normal

A1L21 = fifo_in[11] & write;


--A1L11 is Select~283 at LC1_C7
--operation mode is normal

A1L11 = fifo_in[10] & write;


--A1L01 is Select~282 at LC5_C16
--operation mode is normal

A1L01 = fifo_in[9] & write;


--A1L9 is Select~281 at LC7_C18
--operation mode is normal

A1L9 = fifo_in[8] & write;


--A1L8 is Select~280 at LC7_C23
--operation mode is normal

A1L8 = fifo_in[7] & write;


--A1L7 is Select~279 at LC2_C8
--operation mode is normal

A1L7 = fifo_in[6] & write;


--A1L6 is Select~278 at LC2_C24
--operation mode is normal

A1L6 = fifo_in[5] & write;


--A1L5 is Select~277 at LC1_C5
--operation mode is normal

A1L5 = fifo_in[4] & write;


--A1L4 is Select~276 at LC1_C1
--operation mode is normal

A1L4 = fifo_in[3] & write;


--A1L3 is Select~275 at LC2_C16
--operation mode is normal

A1L3 = fifo_in[2] & write;


--A1L2 is Select~274 at LC8_C23
--operation mode is normal

A1L2 = fifo_in[1] & write;


--A1L1 is Select~273 at LC8_C22
--operation mode is normal

A1L1 = fifo_in[0] & write;


--A1L531 is fifo_out~0 at LC3_C20
--operation mode is normal

A1L531 = write_ptr[0] $ read_ptr[0];


--A1L66 is Select~4990 at LC4_C20
--operation mode is normal

A1L66 = !A1L531 & write_ptr[1] $ !read_ptr[1] # !A1L241;


--A1L76 is Select~4991 at LC6_C20
--operation mode is normal

A1L76 = A1L66 & write_ptr[3] $ !read_ptr[3] # !A1L241;


--A1L07 is Select~5007 at LC7_C20
--operation mode is normal

A1L07 = (write & write_ptr[2] $ !read_ptr[2] # !A1L241) & CASCADE(A1L76);


--A1L86 is Select~4995 at LC3_C15
--operation mode is normal

A1L86 = !reset & !A1L241 & read # !write;


--A1L47 is add~72 at LC1_C12
--operation mode is normal

A1L47 = write_ptr[0] & write_ptr[1];


--A1L57 is add~77 at LC7_C12
--operation mode is normal

A1L57 = write_ptr[0] & write_ptr[1] & write_ptr[2];


--A1L96 is Select~5001 at LC6_C15
--operation mode is normal

A1L96 = write_ptr[0] # read # reset # !write;


--A1L17 is Select~5008 at LC7_C15
--operation mode is normal

A1L17 = (write_ptr[0] $ !A1L241 # !write # !A1L32) & CASCADE(A1L96);


--reset is reset at PIN_89
--operation mode is input

reset = INPUT();


--read is read at PIN_38
--operation mode is input

read = INPUT();


--fifo_in[15] is fifo_in[15] at PIN_40
--operation mode is input

fifo_in[15] = INPUT();


--clock is clock at PIN_39
--operation mode is input

clock = INPUT();


--fifo_in[14] is fifo_in[14] at PIN_90
--operation mode is input

fifo_in[14] = INPUT();


--fifo_in[13] is fifo_in[13] at PIN_84
--operation mode is input

fifo_in[13] = INPUT();


--fifo_in[12] is fifo_in[12] at PIN_56
--operation mode is input

fifo_in[12] = INPUT();


--fifo_in[11] is fifo_in[11] at PIN_55
--operation mode is input

fifo_in[11] = INPUT();


--fifo_in[10] is fifo_in[10] at PIN_46
--operation mode is input

fifo_in[10] = INPUT();


--fifo_in[9] is fifo_in[9] at PIN_98
--operation mode is input

fifo_in[9] = INPUT();


--fifo_in[8] is fifo_in[8] at PIN_32
--operation mode is input

fifo_in[8] = INPUT();


--fifo_in[7] is fifo_in[7] at PIN_28
--operation mode is input

fifo_in[7] = INPUT();


--fifo_in[6] is fifo_in[6] at PIN_45
--operation mode is input

fifo_in[6] = INPUT();


--fifo_in[5] is fifo_in[5] at PIN_31
--operation mode is input

fifo_in[5] = INPUT();


--fifo_in[4] is fifo_in[4] at PIN_57
--operation mode is input

fifo_in[4] = INPUT();


--fifo_in[3] is fifo_in[3] at PIN_20
--operation mode is input

fifo_in[3] = INPUT();


--fifo_in[2] is fifo_in[2] at PIN_34
--operation mode is input

fifo_in[2] = INPUT();


--fifo_in[1] is fifo_in[1] at PIN_29
--operation mode is input

fifo_in[1] = INPUT();


--fifo_in[0] is fifo_in[0] at PIN_96
--operation mode is input

fifo_in[0] = INPUT();


--write is write at PIN_91
--operation mode is input

write = INPUT();


--fifo_out[15] is fifo_out[15] at PIN_94
--operation mode is output

fifo_out[15] = OUTPUT(A1L431Q);


--fifo_out[14] is fifo_out[14] at PIN_8
--operation mode is output

fifo_out[14] = OUTPUT(A1L231Q);


--fifo_out[13] is fifo_out[13] at PIN_9
--operation mode is output

fifo_out[13] = OUTPUT(A1L031Q);


--fifo_out[12] is fifo_out[12] at PIN_58
--operation mode is output

fifo_out[12] = OUTPUT(A1L821Q);


--fifo_out[11] is fifo_out[11] at PIN_22
--operation mode is output

fifo_out[11] = OUTPUT(A1L621Q);


--fifo_out[10] is fifo_out[10] at PIN_71
--operation mode is output

fifo_out[10] = OUTPUT(A1L421Q);


--fifo_out[9] is fifo_out[9] at PIN_33
--operation mode is output

fifo_out[9] = OUTPUT(A1L221Q);


--fifo_out[8] is fifo_out[8] at PIN_10
--operation mode is output

fifo_out[8] = OUTPUT(A1L021Q);


--fifo_out[7] is fifo_out[7] at PIN_99
--operation mode is output

fifo_out[7] = OUTPUT(A1L811Q);


--fifo_out[6] is fifo_out[6] at PIN_6
--operation mode is output

fifo_out[6] = OUTPUT(A1L611Q);


--fifo_out[5] is fifo_out[5] at PIN_97
--operation mode is output

fifo_out[5] = OUTPUT(A1L411Q);


--fifo_out[4] is fifo_out[4] at PIN_15
--operation mode is output

fifo_out[4] = OUTPUT(A1L211Q);


--fifo_out[3] is fifo_out[3] at PIN_30
--operation mode is output

fifo_out[3] = OUTPUT(A1L011Q);


--fifo_out[2] is fifo_out[2] at PIN_19
--operation mode is output

fifo_out[2] = OUTPUT(A1L801Q);


--fifo_out[1] is fifo_out[1] at PIN_26
--operation mode is output

fifo_out[1] = OUTPUT(A1L601Q);


--fifo_out[0] is fifo_out[0] at PIN_27
--operation mode is output

fifo_out[0] = OUTPUT(A1L401Q);


--fifo_empty is fifo_empty at PIN_23
--operation mode is output

fifo_empty = OUTPUT(!A1L241);


--fifo_half is fifo_half at PIN_13
--operation mode is output

fifo_half = OUTPUT(!A1L441);


--fifo_full is fifo_full at PIN_21
--operation mode is output

fifo_full = OUTPUT(!A1L341);


