{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 03 20:39:46 2006 " "Info: Processing started: Thu Aug 03 20:39:46 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off Data_Read -c Data_Read " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Data_Read -c Data_Read" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Data_Read.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Data_Read.v" { { "Info" "ISGN_ENTITY_NAME" "1 Data_Read " "Info: Found entity 1: Data_Read" {  } { { "Data_Read.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt\[0\]~4 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"cnt\[0\]~4\"" {  } { { "Data_Read.v" "cnt\[0\]~4" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 27 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 256 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "2 " "Warning: Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "En " "Warning: No output dependent on input pin \"En\"" {  } { { "Data_Read.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 8 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "Reset " "Warning: No output dependent on input pin \"Reset\"" {  } { { "Data_Read.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "44 " "Info: Implemented 44 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "28 " "Info: Implemented 28 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 03 20:39:49 2006 " "Info: Processing ended: Thu Aug 03 20:39:49 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}
