module  Shift_Latch(CLK,CLR,S1,S0,LIN,RIN,D,C,B,A,QD,QC,QB,QA);
input   CLK,CLR;
input   S1,S0;
input   LIN,RIN;
input   D,C,B,A;
output  QD,QC,QB,QA;

reg  QD,QC,QB,QA;

always  @(posedge CLK)
begin
  if(CLR == 1'b0)
    {QA,QB,QC,QD} <= 4'b0;
  else
    begin
      case({S1,S0})
        2'b00   :  {QA,QB,QC,QD} <= {QA,QB,QC,QD};   
        2'b01   :  {QA,QB,QC,QD} <= {RIN,QA,QB,QC};
        2'b10   :  {QA,QB,QC,QD} <= {QB,QC,QD,LIN};
        2'b11   :  {QA,QB,QC,QD} <= {A,B,C,D};
        default :  {QA,QB,QC,QD} <= {QA,QB,QC,QD};
      endcase
    end
end

endmodule