// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

module main(
	En,
	Reset,
	Adc_Busy,
	Adc_Data,
	Clk_SCL,
	Current_Data
);

input	En;
input	Reset;
input	Adc_Busy;
input	Adc_Data;
input	Clk_SCL;
output	[11:0] Current_Data;

wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;





Data_drive	b2v_inst(.En(En),
.Reset(Reset),.Clk_SCL(Clk_SCL),.SampleCtrl_in(SYNTHESIZED_WIRE_0),.Adc_SCL(SYNTHESIZED_WIRE_1));

Data_Read	b2v_inst1(.En(En),
.Reset(Reset),.Adc_Sdata(Adc_Data),.Adc_SCL(SYNTHESIZED_WIRE_1),.Current_Data(Current_Data));

Sample_Ctrl	b2v_inst2(.En(En),
.Reset(Reset),.Adc_Busy(Adc_Busy),.Sample_Ctrl_out(SYNTHESIZED_WIRE_0));


endmodule
