--A1L4Q is Adc_Conv~reg0
--operation mode is normal

A1L4Q_lut_out = A1L2 # A1L3 & cnt1[4] & SampleCtrl_in;
A1L4Q = DFFEA(A1L4Q_lut_out, Clk_SCL, , , , , );


--Adc_SCL_Select is Adc_SCL_Select
--operation mode is normal

Adc_SCL_Select_lut_out = !A1L22 & !cnt1[4] & !cnt1[5];
Adc_SCL_Select = DFFEA(Adc_SCL_Select_lut_out, Clk_SCL, , , A1L8, , );


--A1L9 is Adc_SCL~0
--operation mode is normal

A1L9 = Adc_SCL_Select & Clk_SCL;


--cnt1[5] is cnt1[5]
--operation mode is normal

cnt1[5]_lut_out = !A1L12;
cnt1[5] = DFFEA(cnt1[5]_lut_out, Clk_SCL, , , A1L8, , );


--A1L7 is Adc_SCL_Select~15
--operation mode is normal

A1L7 = !En & !Reset;


--A1L2 is Adc_Conv~128
--operation mode is normal

A1L2 = SampleCtrl_in & cnt1[5] # !SampleCtrl_in & A1L4Q # !A1L7;


--cnt1[3] is cnt1[3]
--operation mode is normal

cnt1[3]_lut_out = E3_cs_buffer[3];
cnt1[3] = DFFEA(cnt1[3]_lut_out, Clk_SCL, , , A1L8, , );


--cnt1[2] is cnt1[2]
--operation mode is normal

cnt1[2]_lut_out = E3_cs_buffer[2];
cnt1[2] = DFFEA(cnt1[2]_lut_out, Clk_SCL, , , A1L8, , );


--cnt1[1] is cnt1[1]
--operation mode is normal

cnt1[1]_lut_out = E3_cs_buffer[1];
cnt1[1] = DFFEA(cnt1[1]_lut_out, Clk_SCL, , , A1L8, , );


--cnt1[0] is cnt1[0]
--operation mode is arithmetic

cnt1[0]_lut_out = !cnt1[0];
cnt1[0] = DFFEA(cnt1[0]_lut_out, Clk_SCL, , , A1L8, , );

--E3_cout[0] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

E3_cout[0] = CARRY(cnt1[0]);


--A1L3 is Adc_Conv~129
--operation mode is normal

A1L3 = cnt1[3] & cnt1[2] & cnt1[1] # cnt1[0];


--cnt1[4] is cnt1[4]
--operation mode is normal

cnt1[4]_lut_out = E3_cs_buffer[4];
cnt1[4] = DFFEA(cnt1[4]_lut_out, Clk_SCL, , , A1L8, , );


--E3_cs_buffer[3] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

E3_cs_buffer[3] = cnt1[3] $ (E3_cout[2]);

--E3_cout[3] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

E3_cout[3] = CARRY(cnt1[3] & E3_cout[2]);


--E3_cs_buffer[2] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

E3_cs_buffer[2] = cnt1[2] $ (E3_cout[1]);

--E3_cout[2] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

E3_cout[2] = CARRY(cnt1[2] & E3_cout[1]);


--E3_cs_buffer[1] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

E3_cs_buffer[1] = cnt1[1] $ (E3_cout[0]);

--E3_cout[1] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

E3_cout[1] = CARRY(cnt1[1] & E3_cout[0]);


--E3_cs_buffer[4] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

E3_cs_buffer[4] = cnt1[4] $ (E3_cout[3]);

--E3_cout[4] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

E3_cout[4] = CARRY(cnt1[4] & E3_cout[3]);


--A1L22 is reduce_nor~27
--operation mode is normal

A1L22 = cnt1[3] & cnt1[2] & cnt1[1] & cnt1[0];


--A1L8 is Adc_SCL_Select~18
--operation mode is normal

A1L8 = SampleCtrl_in & !En & !Reset;


--A1L12 is cnt1~12
--operation mode is normal

A1L12 = C1_unreg_res_node[5] $ (cnt1[5] # !cnt1[4] # !A1L22);


--C1_unreg_res_node[5] is lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[5]
--operation mode is normal

C1_unreg_res_node[5] = E3_cout[4] $ cnt1[5];


--Clk_SCL is Clk_SCL
--operation mode is input

Clk_SCL = INPUT();


--SampleCtrl_in is SampleCtrl_in
--operation mode is input

SampleCtrl_in = INPUT();


--En is En
--operation mode is input

En = INPUT();


--Reset is Reset
--operation mode is input

Reset = INPUT();


--Adc_Conv is Adc_Conv
--operation mode is output

Adc_Conv = OUTPUT(A1L4Q);


--Adc_SCL is Adc_SCL
--operation mode is output

Adc_SCL = OUTPUT(A1L9);


