module stopwatch(clk1,clk2,EN,F_out);

output F_out;
input  EN;
input  clk1,clk2;

reg F_out;

always @(EN,clk1,clk2)
begin
  case(EN)
	1'b0: F_out <= clk1;
	1'b1: F_out <= clk2;
	default: F_out <= 1'b0;
  endcase
end
endmodule