{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jul 15 21:02:17 2006 " "Info: Processing started: Sat Jul 15 21:02:17 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off time_disp_select -c time_disp_select " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off time_disp_select -c time_disp_select" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_drive\[0\]~70 " "Info: Node \"disp_drive\[0\]~70\"" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0}  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_drive\[2\]~66 " "Info: Node \"disp_drive\[2\]~66\"" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0}  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_drive\[1\]~56 " "Info: Node \"disp_drive\[1\]~56\"" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0}  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "clk~24 " "Info: Node \"clk~24\"" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0}  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_1khz " "Info: Assuming node \"clk_1khz\" is an undefined clock" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 11 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk_1khz" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "Time_EN " "Info: Assuming node \"Time_EN\" is an undefined clock" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 13 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Time_EN" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_200hz " "Info: Assuming node \"clk_200hz\" is an undefined clock" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 12 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk_200hz" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "TimeSet_EN " "Info: Assuming node \"TimeSet_EN\" is an undefined clock" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 14 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "TimeSet_EN" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "always1~5sexp " "Info: Detected gated clock \"always1~5sexp\" as buffer" {  } { { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "always1~5sexp" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "clk~24 " "Info: Detected gated clock \"clk~24\" as buffer" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk~24" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "clk~13 " "Info: Detected gated clock \"clk~13\" as buffer" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk~13" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_1khz register auto_disp_drive\[1\] register auto_disp_drive\[0\] 175.44 MHz 5.7 ns Internal " "Info: Clock \"clk_1khz\" has Internal fmax of 175.44 MHz between source register \"auto_disp_drive\[1\]\" and destination register \"auto_disp_drive\[0\]\" (period= 5.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns auto_disp_drive\[1\] 1 REG LC16 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC16; Fanout = 6; REG Node = 'auto_disp_drive\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { auto_disp_drive[1] } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 28 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns auto_disp_drive\[0\] 2 REG LC11 7 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC11; Fanout = 7; REG Node = 'auto_disp_drive\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "3.600 ns" { auto_disp_drive[1] auto_disp_drive[0] } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 72.22 % " "Info: Total cell delay = 2.600 ns ( 72.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 27.78 % " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "3.600 ns" { auto_disp_drive[1] auto_disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { auto_disp_drive[1] auto_disp_drive[0] } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1khz destination 1.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_1khz\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clk_1khz 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'clk_1khz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { clk_1khz } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns auto_disp_drive\[0\] 2 REG LC11 7 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC11; Fanout = 7; REG Node = 'auto_disp_drive\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "0.100 ns" { clk_1khz auto_disp_drive[0] } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "1.300 ns" { clk_1khz auto_disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk_1khz clk_1khz~out auto_disp_drive[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_1khz source 1.300 ns - Longest register " "Info: - Longest clock path from clock \"clk_1khz\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clk_1khz 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'clk_1khz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { clk_1khz } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns auto_disp_drive\[1\] 2 REG LC16 6 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC16; Fanout = 6; REG Node = 'auto_disp_drive\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "0.100 ns" { clk_1khz auto_disp_drive[1] } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "1.300 ns" { clk_1khz auto_disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk_1khz clk_1khz~out auto_disp_drive[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "1.300 ns" { clk_1khz auto_disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk_1khz clk_1khz~out auto_disp_drive[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "1.300 ns" { clk_1khz auto_disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk_1khz clk_1khz~out auto_disp_drive[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 28 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 28 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "3.600 ns" { auto_disp_drive[1] auto_disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { auto_disp_drive[1] auto_disp_drive[0] } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "1.300 ns" { clk_1khz auto_disp_drive[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk_1khz clk_1khz~out auto_disp_drive[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "1.300 ns" { clk_1khz auto_disp_drive[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk_1khz clk_1khz~out auto_disp_drive[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "Time_EN " "Info: No valid register-to-register data paths exist for clock \"Time_EN\"" {  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk_200hz " "Info: No valid register-to-register data paths exist for clock \"clk_200hz\"" {  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "TimeSet_EN " "Info: No valid register-to-register data paths exist for clock \"TimeSet_EN\"" {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "time_disp_select\[5\]~reg0 Time_EN TimeSet_EN 5.400 ns register " "Info: tsu for register \"time_disp_select\[5\]~reg0\" (data pin = \"Time_EN\", clock pin = \"TimeSet_EN\") is 5.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.100 ns + Longest pin register " "Info: + Longest pin to register delay is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Time_EN 1 CLK PIN_24 17 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 17; CLK Node = 'Time_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { Time_EN } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(3.600 ns) 4.900 ns disp_drive~39 2 COMB LC9 3 " "Info: 2: + IC(1.100 ns) + CELL(3.600 ns) = 4.900 ns; Loc. = LC9; Fanout = 3; COMB Node = 'disp_drive~39'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "4.700 ns" { Time_EN disp_drive~39 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.500 ns disp_drive\[0\]~70 3 COMB LOOP LC4 8 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.500 ns; Loc. = LC4; Fanout = 8; COMB LOOP Node = 'disp_drive\[0\]~70'" { { "Info" "ITDB_PART_OF_SCC" "disp_drive\[0\]~70 LC4 " "Info: Loc. = LC4; Node \"disp_drive\[0\]~70\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { disp_drive[0]~70 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { disp_drive[0]~70 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "4.600 ns" { disp_drive~39 disp_drive[0]~70 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 13.100 ns time_disp_select\[5\]~reg0 4 REG LC1 1 " "Info: 4: + IC(1.000 ns) + CELL(2.600 ns) = 13.100 ns; Loc. = LC1; Fanout = 1; REG Node = 'time_disp_select\[5\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "3.600 ns" { disp_drive[0]~70 time_disp_select[5]~reg0 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 57 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 83.97 % " "Info: Total cell delay = 11.000 ns ( 83.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 16.03 % " "Info: Total interconnect delay = 2.100 ns ( 16.03 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "13.100 ns" { Time_EN disp_drive~39 disp_drive[0]~70 time_disp_select[5]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { Time_EN Time_EN~out disp_drive~39 disp_drive[0]~70 time_disp_select[5]~reg0 } { 0.000ns 0.000ns 1.100ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 57 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "TimeSet_EN destination 8.500 ns - Shortest register " "Info: - Shortest clock path from clock \"TimeSet_EN\" to destination register is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns TimeSet_EN 1 CLK PIN_16 9 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_16; Fanout = 9; CLK Node = 'TimeSet_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { TimeSet_EN } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 4.800 ns clk~24 2 COMB LOOP LC13 8 " "Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC13; Fanout = 8; COMB LOOP Node = 'clk~24'" { { "Info" "ITDB_PART_OF_SCC" "clk~24 LC13 " "Info: Loc. = LC13; Node \"clk~24\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { clk~24 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { clk~24 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "4.600 ns" { TimeSet_EN clk~24 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 8.500 ns time_disp_select\[5\]~reg0 3 REG LC1 1 " "Info: 3: + IC(1.000 ns) + CELL(2.700 ns) = 8.500 ns; Loc. = LC1; Fanout = 1; REG Node = 'time_disp_select\[5\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "3.700 ns" { clk~24 time_disp_select[5]~reg0 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 57 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns 88.24 % " "Info: Total cell delay = 7.500 ns ( 88.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 11.76 % " "Info: Total interconnect delay = 1.000 ns ( 11.76 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "8.500 ns" { TimeSet_EN clk~24 time_disp_select[5]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { TimeSet_EN TimeSet_EN~out clk~24 time_disp_select[5]~reg0 } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "13.100 ns" { Time_EN disp_drive~39 disp_drive[0]~70 time_disp_select[5]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.100 ns" { Time_EN Time_EN~out disp_drive~39 disp_drive[0]~70 time_disp_select[5]~reg0 } { 0.000ns 0.000ns 1.100ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "8.500 ns" { TimeSet_EN clk~24 time_disp_select[5]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.500 ns" { TimeSet_EN TimeSet_EN~out clk~24 time_disp_select[5]~reg0 } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.700ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Time_EN time_disp_select\[0\] time_disp_select\[0\]~reg0 14.700 ns register " "Info: tco from clock \"Time_EN\" to destination pin \"time_disp_select\[0\]\" through register \"time_disp_select\[0\]~reg0\" is 14.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Time_EN source 13.200 ns + Longest register " "Info: + Longest clock path from clock \"Time_EN\" to source register is 13.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Time_EN 1 CLK PIN_24 17 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 17; CLK Node = 'Time_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { Time_EN } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(3.600 ns) 4.900 ns clk~13 2 COMB LC25 3 " "Info: 2: + IC(1.100 ns) + CELL(3.600 ns) = 4.900 ns; Loc. = LC25; Fanout = 3; COMB Node = 'clk~13'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "4.700 ns" { Time_EN clk~13 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.500 ns clk~24 3 COMB LOOP LC13 8 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.500 ns; Loc. = LC13; Fanout = 8; COMB LOOP Node = 'clk~24'" { { "Info" "ITDB_PART_OF_SCC" "clk~24 LC13 " "Info: Loc. = LC13; Node \"clk~24\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { clk~24 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { clk~24 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "4.600 ns" { clk~13 clk~24 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 13.200 ns time_disp_select\[0\]~reg0 4 REG LC7 1 " "Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.200 ns; Loc. = LC7; Fanout = 1; REG Node = 'time_disp_select\[0\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "3.700 ns" { clk~24 time_disp_select[0]~reg0 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 57 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.100 ns 84.09 % " "Info: Total cell delay = 11.100 ns ( 84.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 15.91 % " "Info: Total interconnect delay = 2.100 ns ( 15.91 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "13.200 ns" { Time_EN clk~13 clk~24 time_disp_select[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.200 ns" { Time_EN Time_EN~out clk~13 clk~24 time_disp_select[0]~reg0 } { 0.000ns 0.000ns 1.100ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 57 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.200 ns + Longest register pin " "Info: + Longest register to pin delay is 0.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns time_disp_select\[0\]~reg0 1 REG LC7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7; Fanout = 1; REG Node = 'time_disp_select\[0\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { time_disp_select[0]~reg0 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 57 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns time_disp_select\[0\] 2 PIN PIN_11 0 " "Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'time_disp_select\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "0.200 ns" { time_disp_select[0]~reg0 time_disp_select[0] } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.200 ns 100.00 % " "Info: Total cell delay = 0.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "0.200 ns" { time_disp_select[0]~reg0 time_disp_select[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { time_disp_select[0]~reg0 time_disp_select[0] } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "13.200 ns" { Time_EN clk~13 clk~24 time_disp_select[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.200 ns" { Time_EN Time_EN~out clk~13 clk~24 time_disp_select[0]~reg0 } { 0.000ns 0.000ns 1.100ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "0.200 ns" { time_disp_select[0]~reg0 time_disp_select[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { time_disp_select[0]~reg0 time_disp_select[0] } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "time_disp_select\[5\]~reg0 TimeSet_EN Time_EN 6.500 ns register " "Info: th for register \"time_disp_select\[5\]~reg0\" (data pin = \"TimeSet_EN\", clock pin = \"Time_EN\") is 6.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Time_EN destination 13.200 ns + Longest register " "Info: + Longest clock path from clock \"Time_EN\" to destination register is 13.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Time_EN 1 CLK PIN_24 17 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 17; CLK Node = 'Time_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { Time_EN } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(3.600 ns) 4.900 ns clk~13 2 COMB LC25 3 " "Info: 2: + IC(1.100 ns) + CELL(3.600 ns) = 4.900 ns; Loc. = LC25; Fanout = 3; COMB Node = 'clk~13'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "4.700 ns" { Time_EN clk~13 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 9.500 ns clk~24 3 COMB LOOP LC13 8 " "Info: 3: + IC(0.000 ns) + CELL(4.600 ns) = 9.500 ns; Loc. = LC13; Fanout = 8; COMB LOOP Node = 'clk~24'" { { "Info" "ITDB_PART_OF_SCC" "clk~24 LC13 " "Info: Loc. = LC13; Node \"clk~24\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { clk~24 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { clk~24 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "4.600 ns" { clk~13 clk~24 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.700 ns) 13.200 ns time_disp_select\[5\]~reg0 4 REG LC1 1 " "Info: 4: + IC(1.000 ns) + CELL(2.700 ns) = 13.200 ns; Loc. = LC1; Fanout = 1; REG Node = 'time_disp_select\[5\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "3.700 ns" { clk~24 time_disp_select[5]~reg0 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 57 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.100 ns 84.09 % " "Info: Total cell delay = 11.100 ns ( 84.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 15.91 % " "Info: Total interconnect delay = 2.100 ns ( 15.91 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "13.200 ns" { Time_EN clk~13 clk~24 time_disp_select[5]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.200 ns" { Time_EN Time_EN~out clk~13 clk~24 time_disp_select[5]~reg0 } { 0.000ns 0.000ns 1.100ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 57 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.400 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns TimeSet_EN 1 CLK PIN_16 9 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_16; Fanout = 9; CLK Node = 'TimeSet_EN'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { TimeSet_EN } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.600 ns) 4.800 ns disp_drive\[0\]~70 2 COMB LOOP LC4 8 " "Info: 2: + IC(0.000 ns) + CELL(4.600 ns) = 4.800 ns; Loc. = LC4; Fanout = 8; COMB LOOP Node = 'disp_drive\[0\]~70'" { { "Info" "ITDB_PART_OF_SCC" "disp_drive\[0\]~70 LC4 " "Info: Loc. = LC4; Node \"disp_drive\[0\]~70\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { disp_drive[0]~70 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "" { disp_drive[0]~70 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "4.600 ns" { TimeSet_EN disp_drive[0]~70 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 8.400 ns time_disp_select\[5\]~reg0 3 REG LC1 1 " "Info: 3: + IC(1.000 ns) + CELL(2.600 ns) = 8.400 ns; Loc. = LC1; Fanout = 1; REG Node = 'time_disp_select\[5\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "3.600 ns" { disp_drive[0]~70 time_disp_select[5]~reg0 } "NODE_NAME" } "" } } { "time_disp_select.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/time_disp_select.v" 57 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns 88.10 % " "Info: Total cell delay = 7.400 ns ( 88.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 11.90 % " "Info: Total interconnect delay = 1.000 ns ( 11.90 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "8.400 ns" { TimeSet_EN disp_drive[0]~70 time_disp_select[5]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.400 ns" { TimeSet_EN TimeSet_EN~out disp_drive[0]~70 time_disp_select[5]~reg0 } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.600ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "13.200 ns" { Time_EN clk~13 clk~24 time_disp_select[5]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.200 ns" { Time_EN Time_EN~out clk~13 clk~24 time_disp_select[5]~reg0 } { 0.000ns 0.000ns 1.100ns 0.000ns 1.000ns } { 0.000ns 0.200ns 3.600ns 4.600ns 2.700ns } } } { "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select_cmp.qrpt" Compiler "time_disp_select" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/db/time_disp_select.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/wristwatch/time_disp_select/" "" "8.400 ns" { TimeSet_EN disp_drive[0]~70 time_disp_select[5]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "8.400 ns" { TimeSet_EN TimeSet_EN~out disp_drive[0]~70 time_disp_select[5]~reg0 } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 4.600ns 2.600ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 15 21:02:18 2006 " "Info: Processing ended: Sat Jul 15 21:02:18 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}
