module second_pulse_latch(
						  Reset,
						  Clk_1Hz,
						  speed,
						  acceleration,
						  second_pulse_out 
						  );
						
output [15:0] second_pulse_out;
input  Reset;
input  Clk_1Hz;
input  [15:0] speed; //初速度
input  [16:0] acceleration;
       //最高位acceleration[16]用来表示加速度的正负，0为正，1为负

reg [15:0] second_pulse_out;

initial
begin
  second_pulse_out <= speed;
end

always @(posedge Clk_1Hz)
begin
  if(Reset == 1'b1)
    second_pulse_out <= 16'b0;
  else
  begin
    if(acceleration[16] == 1'b0)  //加速度为正
    begin
      if((second_pulse_out + acceleration[15:0]) < 16'b1111111111111111)
        //加速，且速度不超过65535
        second_pulse_out <= second_pulse_out + acceleration[15:0];
      else
        //速度超过65535，直接固定在65535
        second_pulse_out <= 16'b1111111111111111;
    end
      
    else if(acceleration[16] == 1'b1) //加速度为负
    begin
      if((second_pulse_out - acceleration[15:0]) > 16'b0)
        //减速，且速度不小于0
        second_pulse_out <= second_pulse_out - acceleration[15:0];
      else
        //减速，且速度小于0,直接固定在0，即停止
        second_pulse_out <= 16'b0;
    end 
  end
end
endmodule